JP3504838B2 - Amorphous silicon solar cell - Google Patents

Amorphous silicon solar cell

Info

Publication number
JP3504838B2
JP3504838B2 JP30048197A JP30048197A JP3504838B2 JP 3504838 B2 JP3504838 B2 JP 3504838B2 JP 30048197 A JP30048197 A JP 30048197A JP 30048197 A JP30048197 A JP 30048197A JP 3504838 B2 JP3504838 B2 JP 3504838B2
Authority
JP
Japan
Prior art keywords
layer
film
solar cell
amorphous silicon
termination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30048197A
Other languages
Japanese (ja)
Other versions
JPH11135814A (en
Inventor
章二 森田
辰史 青井
良昭 竹内
正義 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP30048197A priority Critical patent/JP3504838B2/en
Publication of JPH11135814A publication Critical patent/JPH11135814A/en
Application granted granted Critical
Publication of JP3504838B2 publication Critical patent/JP3504838B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/548Amorphous silicon PV cells

Landscapes

  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は非晶質シリコン太陽
電池に関し、特にpin接合を基本とする非晶質シリコ
ン太陽電池に関する。 【0002】 【従来の技術】非晶質シリコン(以下、a−Siと呼
ぶ)太陽電池は、ガラス、ステンレスなどの金属あるい
はポリイミド系の高分子フィルムなど、種々の材料を基
板として用いることができるとともに、低温で形成でき
るため、低コスト化が可能な太陽電池として有望視され
ている。 【0003】図3は、典型的な例として、従来技術によ
るガラス基板上のa−Si太陽電池の基本構成を示す。
図中の符番1は、例えばガラスからなる基板である。こ
の基板1上には、例えば酸化スズ(SnO2 )あるいは
ITO(Indium Tin Oxide)からなる透明電極2が
形成されている。この透明電極2は、通常、熱CVD法
あるいはスパッタ法等の手法で形成される。前記透明電
極2上には、a−Siあるいはアモルファスシリコンカ
ーバイト(a−SiC)からなるp層3、a−Siから
なるi層4、a−Si、a−SiCあるいは微細な結晶
を含むa−Siからなるn層5が順次形成されている。
前記n層5上には、銀(Ag)あるいはアルミニウム
(Al)等からなる金属電極6が形成されている。ここ
で、金属電極6は、通常、真空蒸着法、スパッタ法ある
いは印刷法等の手法で形成される。 【0004】図3の構成のa−Si太陽電池において、
入射光は基板1側から入射し、透明電極2及びp層3を
透過し、i層4で吸収され、電子・正孔対を生ずる。発
生した電子及び正孔は、各n層5及びp層3側に分極、
移動し、電流として外部回路に取り出される。 【0005】p層3、i層4及びn層5は、通常、高周
波グロー放電プラズマによってシラン(SiH4 )ある
いはジシラン(Si26 )等のSiを含む原料ガスを
分解するプラズマCVD法で形成される。p層3は、成
膜の際、原料ガスにジボラン(B26 )等を添加して
価電子制御を行い、p型半導体とする。同様に、n層5
は、成膜の際、原料ガスにフォスフィン(PH3 )を添
加して価電子制御を行い、n型半導体とする。発電層で
あるi層4は、基本的に不純物を含まない真性半導体で
ある。 【0006】p層3、i層4及びn層5の成膜では、予
め真空排気された真空容器に、シランあるいは水素(H
2 )もしくはアルゴン(Ar)、ヘリウム(He)など
で希釈したシランあるいはジシランなどの原料ガスを所
定流量導入し、圧力を調整した後、放電用電極に通常周
波数13.56MHzの高周波電界を印加し、グロー放
電プラズマを発生させ、原料ガスを分解し、基板1上に
a−Siを成膜する。成膜中、基板1は所定温度に加熱
されている。 【0007】ところで、図3の構成のa−Si太陽電池
において、光電流を発生するのは、i層4である。十分
な光を吸収するためのi層4の膜厚は、i層4内に含ま
れる不純物の量や電子的な欠陥密度など、その膜質にも
依存するが、通常300〜600nm程度である。これ
に対し、発電層であるi層4により多くの光を入射させ
るためには、集電層であるp層3及びn層5での光吸収
は、可能な限り低減する必要がある。このため、p層3
及びn層5の膜厚は、導電率にも依存するが、通常7〜
30nm程度である。従って、図3に示したpin型a
−Si太陽電池を構成する層としては、i層4が最も厚
いことになる。 【0008】pin型a−Si太陽電池の性能向上に関
しては、発電効率を向上させることが基本であることは
いうまでもないが、生産性向上即ち成膜速度向上による
コストダウンも重要な要素である。とりわけ、最も膜厚
の厚いi層4の成膜速度は、全ての工程の生産速度を律
速することが多いため、i層4の成膜速度向上について
は、プラズマ密度を増大させる方法、原料ガスとしてジ
シランを用いる方法等、多数の研究例がある。ここで生
産性向上のためにi層4を高速で成膜したpin型a−
Si太陽電池では、i層4を低速で成膜したpin型a
−Si太陽電池と比較して、下記の問題点がある。 【0009】 (1)i層4の成膜速度を増大させるに
は、前述した通りプラズマ密度を増大させ、成膜に寄与
するラジカル(活性種)密度を増大させる必要がある。
高周波グロー放電の場合、プラズマ密度を増大するに
は、プラズマを発生させる高周波電力を増加させる方法
が最も直接的かつ一般的である。しかるに、高周波電力
を増加させると、ラジカル(活性種)密度は増大する
が、それと同時にプラズマ中に存在するイオンのエネル
ギーも増大する。高エネルギーのイオンが成膜中の膜表
面に衝突すると、欠陥が発生する。このため、i層4を
高速で成膜したpin型a−Si太陽電池のp/i層界
面近傍には、高エネルギーイオンの衝突によって生じた
欠陥順位が多数発生し、i層4内で光発生したキャリア
のトラップとなるため、i層を低速で成膜した太陽電池
に比べ短絡電流が低下するという問題がある。 【0010】(2) 高速で成膜したi層4の表面は、低速
で成膜したi層に比べて、凹凸が大きい。凹凸のレベル
は、成膜条件にも依るが、数10nm程度であり、その
上に積層するn層5とほぼ同レベルである。凹凸を有す
るi層4上に膜厚30nm程度のn層5を製造すると、
凹凸の谷の部分にはn層膜が成膜せず、隙間を生じ易
い。pin型a−Si太陽電池では、基本的にp層3、
i層4及びn層5が膜厚方向に積層された部分のみが発
電機能を有するため、前述したような隙間の部分は発電
に寄与しない。従って、有効発電面積が減少するため、
発電効率が低下するという問題を生じる。また、隙間を
生じなくとも、凹凸の山の部分に成膜されるn層5は厚
く、他にの部分に成膜されるn層5は薄くなるため、n
層に膜厚分布が生じることもある。このため、i層4内
に生じる内部電界が場所によって不均一となるため、開
放電圧が低下するという問題を生じる。 【0011】 【発明が解決しようとする課題】本発明はこうした事情
を考慮してなされたもので、i層初期膜及びi層終端膜
の成膜速度をいずれもi層の成膜速度よりも低下させる
とともに、前記i層初期膜及びi層終端膜の成膜速度を
0.2nm/s以下とすることにより、p/i層界面付
近の欠陥準位を減少させ、もって短絡電流及び形状因子
を改善しうる非晶質シリコン太陽電池を提供することを
目的とする。 【0012】 【0013】本発明のその他の目的は、i層初期膜及び
i層終端膜の成膜における印加高周波電力をi層の成膜
における印加高周波電力よりも低くすることにより、i
層初期膜及びi層終端膜の成膜速度を低下させうる非晶
質シリコン太陽電池を提供することにある。 【0014】 【0015】 【課題を解決するための手段】本発明は、pin接合を
有する非晶質シリコン太陽電池の製造方法において、p
in接合はp層上にi層初期膜、i層、i層終端膜及び
n層を順次成膜してなり、前記i層初期膜及び前記i層
終端膜の成膜速度をいずれも前記i層の成膜速度よりも
低下させ、前記i層初期膜及び前記i層終端膜の成膜速
度を0.2nm/s以下とし、かつ前記i層初期膜及び
前記i層終端膜の成膜における印加高周波電力を、i層
の成膜における印加高周波電力よりも低くして成膜速度
を低下させることを特徴とする非晶質シリコン太陽電池
の製造方法である。 【0016】本発明において、i層初期膜及びi層終端
膜の成膜速度をi層の成膜速度より低下させる手段とし
ては、例えば、前記i層初期膜及びi層終端膜の成膜に
おける印加高周波電力をi層の成膜における印加高周波
電力よりも低くして成膜速度を低下させる方法、あるい
はi層初期膜及びi層終端膜の成膜時にラジカル加熱ヒ
ータに負の直流バイアス電圧を印加して成膜速度を低下
させる方法が挙げられる。 【0017】本発明において、i層初期膜及びi層終端
膜の膜厚は、5〜50nmが望ましい。その理由は、5
nm未満では実施例に記載した効果が極めて小さく、5
0nmを越えるとi層全体としての平均成膜速度が低下
して生産性が低下するからである。 【0018】 【発明の実施の形態】以下、本発明の一実施例について
説明する。まず、本発明に係る非晶質シリコン太陽電池
の製造に使用されるプラズマCVD装置について図1を
参照して説明する。 【0019】図中の符番11は反応容器である。この反応
容器11内には、基板ホルダ(図示せず)により支持され
たガラス基板12を加熱する基板加熱ヒータ13、放電用電
極14が互いに対向して配置されている。前記放電用電極
14には、インピーダンス整合器15を介して高周波電源16
が接続されている。前記基板加熱ヒータ13と放電用電極
14間には、ラジカル加熱用電源17に接続されたラジカル
加熱ヒータ18が配置されている。前記ラジカル加熱用電
源17よりラジカル加熱ヒータ18にバイアス電圧を印加で
きるようになっている。ラジカル加熱ヒータ18にバイア
ス電圧を印加することにより、プラズマとガラス基板12
との距離が変化するため、成膜速度を制御することが可
能である。前記ラジカル加熱ヒータ18は、プラズマ中の
ラジカルを活性化して、高品質のi層を形成する目的で
設けている。前記反応容器11には、前記放電用電極14部
分に原料ガスを供給する反応ガス導入管19が連結されて
いる。また、反応容器11には該反応容器11内を排気する
排気管20が連結され、該排気管20には真空ポンプ21が接
続されている。前記放電用電極14はアース線22を介して
接地されている。 【0020】次に、こうした構成のプラズマCVD装置
を用いてpin型a−Si太陽電池を製造する方法につ
いて図2を参照して説明する。 (1) まず、透明基板32として予め熱CVD法で酸化スズ
(SnO2 )を形成したガラス基板31を中性洗剤及び有
機溶剤で洗浄、乾燥した後、プラズマCVD法により、
膜厚10nmのp層33を形成した。ここで、p層33の成
膜には、原料ガスとして、シラン(SiH4 )、メタン
(CH4 )、水素(H2 )及びジボラン(B26 )を
用いた。 【0021】(2) 次に、プラズマを停止せずに、ジボラ
ンの供給を停止するとともに、メタンの流量を徐々に減
少させながら厚さ10nmのバッファ層34を形成した。
つづいて、p層33及びバッファ層34を形成したガラス基
板31を真空中で図1に示したプラズマCVD装置に搬送
し、基板加熱用ヒータ13にセットした。 【0022】(3) 次に、真空ポンプ21により、反応容器
11内に5.0×10-7Torrまで排気した後、基板加
熱用ヒータ13に通電し、基板12を所定温度、通常100
〜200℃に加熱し、温度を十分安定させた後、反応容
器11内に反応ガス導入管19を介してi層36成膜用の原料
ガスとして、シランを所定流量導入した。反応容器11内
の圧力は、図示しない圧力調整機構によって所定圧力、
通常30〜300mTorrに制御されている。 【0023】(4) 次に、ラジカル加熱用電源17により、
ラジカル加熱ヒータ18の温度が所定温度になるように通
電、加熱した。つづいて、反応容器11内の温度及び圧力
を十分安定させた後、高周波電源16から、インピーダン
ス整合器15を介して放電用電極14に10Wの高周波電力
を印加してグロー放電プラズマを発生させ、バッファ層
34上に成膜速度0.2nm以下で膜厚15nmのi層初
期膜35を成膜した。ここで、i層初期膜35の膜厚は15
nmに限定する必要はなく、5〜50nmの範囲であれ
ば、本実施例の効果がある。 【0024】(5) 次に、プラズマを停止することなく高
周波電力を徐々に60Wまで増大させ、成膜速度1.1
nm/sで膜厚300nmのi層36を成膜した。このi
層36を成膜した後、プラズマを停止することなく高周波
電力を徐々に10Wまで減少させ、成膜速度0.2nm
/s以下で膜厚15nmのi層終端膜37を成膜した。こ
こで、i層終端膜37の膜厚は15nmに限定する必要は
なく、5〜50nmの範囲であれば、本実施例の効果が
ある。 【0025】(6) 次に、i層終端膜37を成膜した基板31
をn層成膜室に搬送し、前述と同様のプラズマCVD法
により膜厚40nmのn層38を成膜した。このn層38の
成膜には、原料ガスとしてシラン及びフォスフィンを用
いた。つづいて、抵抗加熱式の真空蒸着法により、金属
電極39として膜厚400nmのアルミニウム(Al)を
n層38上に製膜し、a−Si太陽電池を製造した。 【0026】このようにして製造されるa−Si太陽電
池は、図2に示すように、ガラス基板31上に、透明電極
32、p層33、バッファ層34、成膜速度0.2nm/s以
下で成膜された膜厚15nmのi層初期層35、成膜速度
1.1nm/s/で成膜された膜厚300nmのi層3
6、成膜速度0.2nm以下で成膜された膜厚15nm
のi層終端層37、n層38及び金属電極39を順次設けた構
成となっている。しかるに、こうした構成のa−Si太
陽電池は、次のような効果を有する。 【0027】1)i層初期膜35の成膜速度を低下させたた
め、高いエネルギーを有するイオンの膜正面への衝突が
緩和され、pin型a−Si太陽電池の特性に大きな影
響を及ぼすp/i層界面付近の欠陥準位が減少する。従
って、i層36内で光発生したキャリアが消滅することな
く、有効に外部回路に取り出されるため、短絡電流及び
形状因子が改善される。 【0028】2)i層終端層37の成膜速度を低下させたた
め、i層表面の凹凸が小さくなる。従って、i層36とn
層38の密着性が向上し、隙間が少なくなり、有効発電面
積が増大するため、発電効率が向上する。また、n層38
の膜厚分布が改善され、i層36内の内部電界分布の均一
性が高まるため、開放電圧が増大する。 【0029】事実、比較例1として、i層初期膜及びi
層終端膜を用いない従来構造のa−Si太陽電池を作製
した。また、比較例2として、i層初期膜のみを用いた
a−Si太陽電池も作製した。但し、比較例1及び比較
例2において、透明電極、p層、バッファ層、i層、n
層及び金属電極の膜厚並びに各層の成膜条件は、前記し
た本実施例に係るa−Si太陽電池と全く同一とした。 【0030】以上のようにして作製した3種類のa−S
i太陽電池の模擬太陽光を照射し、その電圧−電流特性
を計測した。模擬太陽光照射条件は、下記の通りであ
る。 スペクトル:AM1.5、 照射強度:100mW/cm2 、 照射温度:25℃ 計測結果は、下記表1に示す通りである。 【0031】 【表1】 【0032】表1より、本実施例の方が、比較例1及び
比較例2と比べ、短絡電流、開放電圧、形状因子、及び
効率の値が大きく、改善されていることが確認できた。
なお、本発明において、i層初期膜及びi層終端膜の成
膜速度を制御する手段は、上記実施例に記載した高周波
電力を低下させる手法に限定する必要ない。例えば、実
施例に記載したラジカル加熱ヒータに負の直流バイアス
電圧を印加し、成膜速度を低下させる手法によっても同
様の効果が得られる。 【0033】 【発明の効果】以上詳述したように本発明によれば、i
層初期膜及びi層終端膜の成膜速度をいずれもi層の成
膜速度よりも低下させるとともに、前記i層初期膜及び
i層終端膜の成膜速度を0.2nm/s以下とすること
により、p/i層界面付近の欠陥準位を減少させ、もっ
て短絡電流及び形状因子を改善しうる非晶質シリコン太
陽電池を提供できる。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amorphous silicon solar cell, and more particularly to an amorphous silicon solar cell based on a pin junction. 2. Description of the Related Art Amorphous silicon (hereinafter referred to as a-Si) solar cells can use various materials such as glass, metal such as stainless steel, or a polyimide polymer film as a substrate. At the same time, since it can be formed at a low temperature, it is promising as a solar cell that can be reduced in cost. FIG. 3 shows, as a typical example, the basic structure of an a-Si solar cell on a glass substrate according to the prior art.
Reference numeral 1 in the figure is a substrate made of, for example, glass. On this substrate 1, a transparent electrode 2 made of, for example, tin oxide (SnO 2 ) or ITO (Indium Tin Oxide) is formed. This transparent electrode 2 is usually formed by a technique such as a thermal CVD method or a sputtering method. On the transparent electrode 2, a p layer 3 made of a-Si or amorphous silicon carbide (a-SiC), an i layer 4 made of a-Si, a-Si, a-SiC or a An n layer 5 made of -Si is sequentially formed.
On the n layer 5, a metal electrode 6 made of silver (Ag) or aluminum (Al) is formed. Here, the metal electrode 6 is usually formed by a method such as a vacuum evaporation method, a sputtering method, or a printing method. In the a-Si solar cell having the structure shown in FIG.
Incident light enters from the substrate 1 side, passes through the transparent electrode 2 and the p-layer 3, is absorbed by the i-layer 4, and generates electron-hole pairs. The generated electrons and holes are polarized on the respective n-layer 5 and p-layer 3 sides,
It moves and is taken out to an external circuit as a current. The p layer 3, the i layer 4 and the n layer 5 are usually formed by a plasma CVD method in which a source gas containing Si such as silane (SiH 4 ) or disilane (Si 2 H 6 ) is decomposed by high frequency glow discharge plasma. It is formed. The p layer 3 is formed into a p-type semiconductor by controlling valence electrons by adding diborane (B 2 H 6 ) or the like to a source gas at the time of film formation. Similarly, n layer 5
In film formation, phosphine (PH 3 ) is added to a source gas at the time of film formation to perform valence electron control, thereby forming an n-type semiconductor. The i-layer 4 which is a power generation layer is an intrinsic semiconductor basically containing no impurities. In forming the p-layer 3, the i-layer 4 and the n-layer 5, silane or hydrogen (H
2 ) Alternatively, a raw material gas such as silane or disilane diluted with argon (Ar), helium (He) or the like is introduced at a predetermined flow rate, and after adjusting the pressure, a high-frequency electric field having a normal frequency of 13.56 MHz is applied to the discharge electrode. Then, glow discharge plasma is generated to decompose the raw material gas, and a-Si is formed on the substrate 1. During film formation, the substrate 1 is heated to a predetermined temperature. In the a-Si solar cell having the configuration shown in FIG. 3, it is the i-layer 4 that generates a photocurrent. The thickness of the i-layer 4 for absorbing sufficient light depends on the film quality, such as the amount of impurities contained in the i-layer 4 and the electronic defect density, but is usually about 300 to 600 nm. On the other hand, in order to make more light incident on the i-layer 4 as the power generation layer, it is necessary to reduce the light absorption in the p-layer 3 and the n-layer 5 as the current collecting layers as much as possible. Therefore, the p layer 3
And the thickness of the n-layer 5 depends on the electrical conductivity,
It is about 30 nm. Therefore, the pin type a shown in FIG.
As a layer constituting the -Si solar cell, the i-layer 4 is the thickest. Regarding the improvement of the performance of the pin-type a-Si solar cell, it goes without saying that it is fundamental to improve the power generation efficiency, but the improvement of productivity, that is, the cost reduction by improving the film formation speed is also an important factor. is there. In particular, since the deposition rate of the i-layer 4 having the largest film thickness often determines the production rate of all the steps, the deposition rate of the i-layer 4 is improved by a method of increasing the plasma density, a source gas, or the like. There are many research examples such as a method using disilane. Here, in order to improve productivity, a pin type a-
In a Si solar cell, a pin type a in which an i-layer 4 is formed at a low speed
There are the following problems as compared with -Si solar cells. (1) In order to increase the film formation rate of the i-layer 4 , it is necessary to increase the plasma density and the radical (active species) density contributing to the film formation as described above.
In the case of high-frequency glow discharge, the most direct and general method for increasing the plasma density is to increase the high-frequency power for generating plasma. However, when the high-frequency power is increased, the radical (active species) density is increased, but at the same time, the energy of ions existing in the plasma is also increased. When high-energy ions collide with the film surface during film formation, defects occur. Therefore, in the vicinity of the p / i layer interface of the pin-type a-Si solar cell in which the i-layer 4 is formed at a high speed, many defect orders generated by the collision of high-energy ions are generated. Since the generated carriers serve as traps for carriers, there is a problem that the short-circuit current is reduced as compared with a solar cell in which the i-layer is formed at a low speed. (2) The surface of the i-layer 4 formed at a high speed has larger irregularities than the i-layer formed at a low speed. The level of the unevenness is about several tens of nm, depending on the film forming conditions, and is almost the same level as the n-layer 5 laminated thereon. When an n-layer 5 having a thickness of about 30 nm is manufactured on the i-layer 4 having irregularities,
An n-layer film is not formed in a valley portion of the unevenness, and a gap is easily generated. In a pin-type a-Si solar cell, the p-layer 3 is basically
Since only the portion where the i-layer 4 and the n-layer 5 are stacked in the film thickness direction has a power generation function, the above-mentioned gap portion does not contribute to power generation. Therefore, since the effective power generation area decreases,
There is a problem that power generation efficiency is reduced. Further, even if no gap is formed, the n-layer 5 formed on the hill portion of the unevenness is thick and the n-layer 5 formed on the other portions is thin.
A layer may have a thickness distribution. For this reason, the internal electric field generated in the i-layer 4 becomes non-uniform depending on the location, which causes a problem that the open-circuit voltage decreases. SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and the film forming speeds of the i-layer initial film and the i-layer terminal film are both higher than the i-layer film forming speed. Lower
At the same time, the deposition rates of the i-layer initial film and the i-layer termination film are reduced.
An object of the present invention is to provide an amorphous silicon solar cell in which the defect level in the vicinity of the p / i layer interface is reduced by controlling the thickness to 0.2 nm / s or less , thereby improving the short-circuit current and the form factor. Another object of the present invention is to make the applied high-frequency power for forming the i-layer initial film and the i-layer termination film lower than the applied high-frequency power for forming the i-layer.
It is an object of the present invention to provide an amorphous silicon solar cell that can reduce the deposition rate of a layer initial film and an i-layer termination film. The present invention provides a method of manufacturing an amorphous silicon solar cell having a pin junction.
in junction i layer initial film on the p layer, i layer, sequentially formed to be in the i layer termination layer and n-layer, both the deposition rate of the i layer initial film and the i layer termination layer wherein i Lower than the film formation rate of the layer, the film formation rate of the i-layer initial film and the i-layer termination film is 0.2 nm / s or less , and the i-layer initial film and
The applied high-frequency power in the formation of the i-layer termination film is converted into an i-layer
Deposition rate by lowering the applied high frequency power in
Amorphous silicon solar cell characterized by lowering
Is a manufacturing method . In the present invention, the means for lowering the deposition rate of the i-layer initial film and the i-layer termination film is lower than the deposition rate of the i-layer initial film and the i-layer termination film. A method in which the applied high-frequency power is made lower than the applied high-frequency power in the formation of the i-layer to reduce the deposition rate, or a negative DC bias voltage is applied to the radical heater during the formation of the i-layer initial film and the i-layer termination film. A method of lowering the film formation rate by applying the voltage may be used. In the present invention, the thickness of the i-layer initial film and the i-layer termination film is preferably 5 to 50 nm. The reason is 5
If it is less than 5 nm, the effects described in the examples are extremely small.
If the thickness exceeds 0 nm, the average film forming rate of the entire i-layer decreases, and the productivity decreases. Hereinafter, an embodiment of the present invention will be described. First, a plasma CVD apparatus used for manufacturing an amorphous silicon solar cell according to the present invention will be described with reference to FIG. Reference numeral 11 in the figure denotes a reaction vessel. In the reaction vessel 11, a substrate heater 13 for heating a glass substrate 12 supported by a substrate holder (not shown) and a discharge electrode 14 are arranged to face each other. The discharge electrode
14 has a high frequency power supply 16 via an impedance matching unit 15.
Is connected. Substrate heater 13 and discharge electrode
A radical heater 18 connected to a radical heating power supply 17 is disposed between the two. A bias voltage can be applied to the radical heater 18 from the radical heating power supply 17. By applying a bias voltage to the radical heater 18, the plasma and the glass substrate 12 are
Since the distance to the film changes, the film forming speed can be controlled. The radical heater 18 is provided for the purpose of activating radicals in plasma to form a high-quality i-layer. The reaction vessel 11 is connected to a reaction gas introduction pipe 19 for supplying a source gas to the discharge electrode 14. An exhaust pipe 20 for exhausting the inside of the reaction vessel 11 is connected to the reaction vessel 11, and a vacuum pump 21 is connected to the exhaust pipe 20. The discharge electrode 14 is grounded via a ground wire 22. Next, a method of manufacturing a pin-type a-Si solar cell using the plasma CVD apparatus having such a configuration will be described with reference to FIG. (1) First, as a transparent substrate 32, a glass substrate 31 on which tin oxide (SnO 2 ) has been formed in advance by a thermal CVD method is washed with a neutral detergent and an organic solvent, dried, and then subjected to a plasma CVD method.
A p-layer 33 having a thickness of 10 nm was formed. Here, silane (SiH 4 ), methane (CH 4 ), hydrogen (H 2 ), and diborane (B 2 H 6 ) were used as source gases for forming the p-layer 33. (2) Next, without stopping the plasma, the supply of diborane was stopped, and the buffer layer 34 having a thickness of 10 nm was formed while gradually reducing the flow rate of methane.
Subsequently, the glass substrate 31 on which the p layer 33 and the buffer layer 34 were formed was conveyed in a vacuum to the plasma CVD apparatus shown in FIG. (3) Next, the reaction vessel is
After evacuating the substrate 12 to 5.0 × 10 −7 Torr, the substrate heating heater 13 is energized to bring the substrate 12 to a predetermined temperature, usually 100 ° C.
After heating to about 200 ° C. to sufficiently stabilize the temperature, a predetermined flow rate of silane was introduced into the reaction vessel 11 as a source gas for forming the i-layer 36 through the reaction gas introduction pipe 19. The pressure in the reaction vessel 11 is a predetermined pressure by a pressure adjustment mechanism (not shown),
Usually, it is controlled at 30 to 300 mTorr. (4) Next, the radical heating power supply 17
Energization and heating were performed so that the temperature of the radical heater 18 became a predetermined temperature. Subsequently, after sufficiently stabilizing the temperature and pressure in the reaction vessel 11, a high-frequency power of 16 W is applied from the high-frequency power supply 16 to the discharge electrode 14 via the impedance matching device 15 to generate glow discharge plasma, Buffer layer
An i-layer initial film 35 having a film thickness of 15 nm was formed on the film 34 at a film formation rate of 0.2 nm or less. Here, the thickness of the i-layer initial film 35 is 15
It is not necessary to limit to nm, and the effect of the present embodiment is attained within the range of 5 to 50 nm. (5) Next, the high frequency power is gradually increased to 60 W without stopping the plasma, and the film forming speed is set to 1.1.
An i-layer 36 having a thickness of 300 nm was formed at a thickness of 300 nm / s. This i
After forming the layer 36, the high-frequency power is gradually reduced to 10 W without stopping the plasma, and the film forming speed is set to 0.2 nm.
An i-layer termination film 37 having a thickness of 15 nm was formed at a rate of not more than / s. Here, the thickness of the i-layer termination film 37 does not need to be limited to 15 nm, and the effect of the present embodiment can be obtained if it is in the range of 5 to 50 nm. (6) Next, the substrate 31 on which the i-layer termination film 37 is formed
Was transported to an n-layer film forming chamber, and an n-layer 38 having a thickness of 40 nm was formed by the same plasma CVD method as described above. For forming the n-layer 38, silane and phosphine were used as source gases. Subsequently, a 400 nm-thick aluminum (Al) film was formed as a metal electrode 39 on the n-layer 38 by a resistance heating type vacuum evaporation method to manufacture an a-Si solar cell. The a-Si solar cell manufactured as described above has a transparent electrode on a glass substrate 31, as shown in FIG.
32, a p layer 33, a buffer layer 34, a 15 nm thick i-layer initial layer 35 formed at a film forming rate of 0.2 nm / s or less, a film formed at a film forming rate of 1.1 nm / s / 300 nm i-layer 3
6, film thickness of 15 nm formed at a film formation rate of 0.2 nm or less
In this configuration, an i-layer termination layer 37, an n-layer 38, and a metal electrode 39 are sequentially provided. However, the a-Si solar cell having such a configuration has the following effects. 1) Since the film formation rate of the i-layer initial film 35 is reduced, the collision of ions having high energy with the front of the film is reduced, and the p / p ratio greatly affects the characteristics of the pin type a-Si solar cell. Defect levels near the i-layer interface are reduced. Therefore, the carriers generated in the i-layer 36 are effectively taken out to the external circuit without disappearing, so that the short-circuit current and the form factor are improved. 2) Since the deposition rate of the i-layer termination layer 37 is reduced, the irregularities on the i-layer surface are reduced. Therefore, the i-layer 36 and n
The adhesion of the layer 38 is improved, the gap is reduced, and the effective power generation area is increased, so that the power generation efficiency is improved. The n-layer 38
Is improved, and the uniformity of the internal electric field distribution in the i-layer 36 is increased, so that the open-circuit voltage is increased. In fact, as Comparative Example 1, the i-layer initial film and the i-layer
An a-Si solar cell having a conventional structure without using a layer termination film was manufactured. Further, as Comparative Example 2, an a-Si solar cell using only the i-layer initial film was manufactured. However, in Comparative Examples 1 and 2, the transparent electrode, p layer, buffer layer, i layer, n layer
The film thickness of the layer and the metal electrode and the film forming conditions of each layer were exactly the same as those of the a-Si solar cell according to the above-described embodiment. The three types of aS prepared as described above
The i-solar cell was irradiated with simulated sunlight, and its voltage-current characteristics were measured. The simulated sunlight irradiation conditions are as follows. Spectrum: AM 1.5, irradiation intensity: 100 mW / cm 2 , irradiation temperature: 25 ° C. The measurement results are as shown in Table 1 below. [Table 1] From Table 1, it was confirmed that the value of the short-circuit current, the open-circuit voltage, the shape factor, and the efficiency of the present example were larger and improved than those of Comparative Examples 1 and 2.
In the present invention, the means for controlling the deposition rates of the i-layer initial film and the i-layer termination film does not need to be limited to the method of reducing high-frequency power described in the above embodiment. For example, a similar effect can be obtained by applying a negative DC bias voltage to the radical heater described in the embodiment to lower the film forming rate. As described in detail above, according to the present invention, i
Both the film formation rate of the layer initial film and the i-layer termination film are made lower than the film formation rate of the i-layer, and the i-layer initial film and
Amorphous silicon solar cell capable of reducing the defect level near the p / i layer interface by reducing the deposition rate of the i-layer termination film to 0.2 nm / s or less , thereby improving the short-circuit current and the form factor Can be provided.

【図面の簡単な説明】 【図1】本発明に係る非晶質シリコン太陽電池の製造に
使用されるプラズマCVD装置の説明図。 【図2】本発明の一実施例に係るpin型a−Si太陽
電池の断面図。 【図3】従来のpin型a−Si太陽電池の断面図。 【符号の説明】 11…反応容器、 12…基板、 13…基板加熱ヒータ、 14…放電用電極、 15…インピーダンス整合器、 16…高周波電源、 17…ラジカル加熱用電源、 18…ラジカル加熱ヒータ、 19…反応ガス導入管、 20…排気管、 21…真空ポンプ、 31…ガラス基板、 32…透明電極、 33…p層、 34…バッファ層、 35…i層初期膜、 36…i層、 37…i層終端膜、 38…n層、 39…金属電極。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory view of a plasma CVD apparatus used for manufacturing an amorphous silicon solar cell according to the present invention. FIG. 2 is a cross-sectional view of a pin-type a-Si solar cell according to one embodiment of the present invention. FIG. 3 is a sectional view of a conventional pin-type a-Si solar cell. [Explanation of Signs] 11: Reaction vessel, 12: Substrate, 13: Substrate heater, 14: Discharge electrode, 15: Impedance matching device, 16: High frequency power supply, 17: Radical heating power supply, 18: Radical heater, 19 ... reaction gas introduction pipe, 20 ... exhaust pipe, 21 ... vacuum pump, 31 ... glass substrate, 32 ... transparent electrode, 33 ... p layer, 34 ... buffer layer, 35 ... i layer initial film, 36 ... i layer, 37 ... i-layer termination film, 38 ... n-layer, 39 ... metal electrode.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 竹内 良昭 長崎県長崎市深堀町五丁目717番1号 三菱重工業株式会社長崎研究所内 (72)発明者 村田 正義 長崎県長崎市深堀町五丁目717番1号 三菱重工業株式会社長崎研究所内 (56)参考文献 特開 昭62−144371(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 31/04 - 31/078 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshiaki Takeuchi 5-717-1, Fukahori-cho, Nagasaki-city, Nagasaki Prefecture Mitsubishi Heavy Industries, Ltd. Nagasaki Research Institute (72) Inventor Masayoshi Murata 5-717, Fukahori-cho, Nagasaki-city, Nagasaki Prefecture No. 1 Inside Nagasaki Research Laboratory, Mitsubishi Heavy Industries, Ltd. (56) References JP-A-62-144371 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 31/04-31/078

Claims (1)

(57)【特許請求の範囲】 【請求項1】 pin接合を有する非晶質シリコン太陽
電池の製造方法において、pin接合はp層上にi層初
期膜、i層、i層終端膜及びn層を順次成膜してなり、
前記i層初期膜及び前記i層終端膜の成膜速度をいずれ
も前記i層の成膜速度よりも低下させ、前記i層初期膜
及び前記i層終端膜の成膜速度を0.2nm/s以下と
し、かつ前記i層初期膜及び前記i層終端膜の成膜にお
ける印加高周波電力を、i層の成膜における印加高周波
電力よりも低くして成膜速度を低下させることを特徴と
する非晶質シリコン太陽電池の製造方法
(57) [Claim 1] In a method for manufacturing an amorphous silicon solar cell having a pin junction, the pin junction is formed on an i-layer initial film, an i-layer, an i-layer termination film, and an n-layer on a p-layer. Layers are sequentially formed,
The i layer initial film and the both the deposition rate of the i layer terminating layer is lower than the deposition speed of the i-layer, the i layer initial film and 0.2nm deposition rate of the i layer termination layer / less than
And forming the i-layer initial film and the i-layer termination film.
The applied high frequency power in the film formation of the i-layer
A method for manufacturing an amorphous silicon solar cell , comprising lowering the film formation rate by lowering the electric power .
JP30048197A 1997-10-31 1997-10-31 Amorphous silicon solar cell Expired - Fee Related JP3504838B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30048197A JP3504838B2 (en) 1997-10-31 1997-10-31 Amorphous silicon solar cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30048197A JP3504838B2 (en) 1997-10-31 1997-10-31 Amorphous silicon solar cell

Publications (2)

Publication Number Publication Date
JPH11135814A JPH11135814A (en) 1999-05-21
JP3504838B2 true JP3504838B2 (en) 2004-03-08

Family

ID=17885331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30048197A Expired - Fee Related JP3504838B2 (en) 1997-10-31 1997-10-31 Amorphous silicon solar cell

Country Status (1)

Country Link
JP (1) JP3504838B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001156311A (en) 1999-11-30 2001-06-08 Sharp Corp Thin-film solar battery and its manufacturing method
US6566594B2 (en) 2000-04-05 2003-05-20 Tdk Corporation Photovoltaic element
JP2003101407A (en) * 2001-09-21 2003-04-04 Sharp Corp Semiconductor integrated circuit
US20110114177A1 (en) * 2009-07-23 2011-05-19 Applied Materials, Inc. Mixed silicon phase film for high efficiency thin film silicon solar cells
TWI470818B (en) * 2010-03-24 2015-01-21 Hitachi Ltd Solar battery

Also Published As

Publication number Publication date
JPH11135814A (en) 1999-05-21

Similar Documents

Publication Publication Date Title
EP0895291B1 (en) Photovoltaic element and method of producing the same
JP4433131B2 (en) Method for forming silicon-based thin film
JP3364180B2 (en) Amorphous silicon solar cell
JPH07297421A (en) Manufacture of thin film semiconductor solar battery
EP1463126A2 (en) Stacked photovoltaic device
JP2004289034A (en) Treatment method for zinc oxide film and method for manufacturing photovoltaic element using same
JP2004014812A (en) Photovoltaic device
US8735201B2 (en) Film-forming method for forming passivation film and manufacturing method for solar cell element
EP1069625A2 (en) Microcrystalline series photovoltaic element, process for the production of said photovoltaic element, building material and power generation apparatus in which said photovoltaic element is used
JPH05110125A (en) Photovoltaic element
JP3402637B2 (en) Method of manufacturing solar cell, manufacturing apparatus thereof, and method of manufacturing long sheet substrate
JP3504838B2 (en) Amorphous silicon solar cell
JP3787410B2 (en) Deposited film manufacturing method and photovoltaic device manufacturing method
JPH08298333A (en) Semiconductor coating film forming equipment, and thin film solar cell and forming method of thin film solar cell
EP0680384B1 (en) Microwave energized process for the preparation of high quality semiconductor material
JP3027670B2 (en) Photovoltaic element
Takano et al. Excitation frequency effects on stabilized efficiency of large-area amorphous silicon solar cells using flexible plastic film substrate
JP3245111B2 (en) Amorphous silicon solar cell
JP3029169B2 (en) Photovoltaic element
JP3679937B2 (en) Amorphous silicon solar cell and manufacturing method thereof
JP2006269607A (en) Method of manufacturing photovoltaic power element
JP2000004036A (en) Forming method of fine crystal semiconductor layer and photovoltaic element
JP4012106B2 (en) Method for forming photovoltaic element
JP3272681B2 (en) Solar cell manufacturing method
JP3142682B2 (en) Solar cell manufacturing method and manufacturing apparatus

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20011016

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20031211

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071219

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081219

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091219

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091219

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101219

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101219

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111219

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111219

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121219

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees