JP3486421B2 - Method for manufacturing thin film semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film semiconductor device formed on an insulating material such as a thin film transistor or a three-dimensional LSI device applied to an active matrix liquid crystal display or the like.

[0002]

2. Description of the Related Art In recent years, with the increase in screen size and resolution of liquid crystal displays, the drive system is shifting from the simple matrix system to the active matrix system, and it is becoming possible to display a large amount of information. The active matrix method enables a liquid crystal display having more than several hundred thousand pixels, and forms a switching transistor for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused silica plate or glass that enables a transmissive display is used.

However, in order to expand the display screen and reduce the price, it is essential to use inexpensive ordinary glass as an insulating substrate. Therefore, there has been a demand for a technique capable of forming a thin film transistor for operating an active matrix type liquid crystal display on an inexpensive glass substrate with stable performance while maintaining the economical efficiency.

Amorphous silicon or polycrystalline silicon is usually used for the channel semiconductor layer of the thin film transistor. However, when the driving circuit is integrated into a thin film transistor, polycrystalline silicon having a high operating speed is used. It is advantageous.

Conventionally, in the case of forming such a thin film transistor, after forming a silicon layer of a channel portion, a substrate of oxygen (O ₂ ) or laughing gas (N ₂ ) is used to form a gate insulating layer.
O), water vapor (H ₂ O), etc., and the temperature is set to a high temperature of about 800 ° C. to 1100 ° C. to oxidize a part of the channel silicon layer to form a gate insulating layer. The oxidation method was used. On the other hand, various methods have been attempted to manufacture a thin film semiconductor device using polycrystalline silicon at a process maximum temperature of about 600 ° C. or less that can withstand the use of an inexpensive ordinary glass substrate. For example,
The channel layer semiconductor layer is formed on the channel layer by low pressure chemical vapor deposition (LPCV).
D method), a gate insulating film is formed by an electron cyclotron resonance plasma CVD method (ECR-PECVD method), and then hydrogenation treatment such as hydrogen plasma irradiation is performed. Or the channel semiconductor layer is amorphous
A silicon thin film is deposited, then heat-treated at 600 ° C. for about 24 hours, and then atmospheric pressure chemical vapor deposition (APCVD).
Method), a gate insulating film is formed, and hydrogenation treatment is performed. (Japane J, Appl, P
hys, 30L 84 '91)

[0006]

However, many problems have been pointed out in the above-mentioned conventional methods. First of all, in the formation of a SiO ₂ film by the thermal oxidation method, high temperature heat treatment of at least 800 ° C. or more accompanies the formation thereof, so that the heat resistance of a thin film layer or a substrate located below the oxide film becomes a problem. For example, when making a switching transistor of a large area liquid crystal display, a substrate such as a fused quartz plate, which is very expensive, cannot withstand such a high temperature. Further, even in a three-dimensional LSI device, the lower layer transistor is deteriorated at a high temperature, so that this thermal oxidation method is practically unusable.

Next, the channel semiconductor layer is formed by the LPCVD method, the gate insulating film is formed by the ECR-PECVD method, and further the hydrogen plasma treatment is performed, the mobility is 4 to 5 cm ² / V. It is as low as sec, which is still insufficient as a thin film semiconductor device. In addition, due to the hydrogenation process performed to improve the characteristics of the thin film semiconductor device, some of the various thin films forming the thin film semiconductor device are etched and some of the many thin film semiconductor devices are destroyed. There is a problem that I said. In addition, a method of depositing an amorphous silicon thin film on the channel semiconductor layer, then performing a heat treatment at about 600 ° C., forming a gate insulating film by the APCVD method, and further performing a hydrogenation treatment such as hydrogen plasma irradiation. Has a large interface trap level of about 10 ¹² and exhibits depletion type semiconductor device characteristics, and is still insufficient as a thin film semiconductor device. Further, as in the previous case, the problems associated with the Yahari hydrogenation treatment remain, and it has been impossible to uniformly and stably form a thin film semiconductor device over a large area.

Therefore, there is a demand for a thin film semiconductor device having a high mobility, a clean MOS interface, a low interface trap level, and no depletion, and a thin film semiconductor device is manufactured. There has been a demand for a manufacturing method that does not require hydrogenation in the process and can produce a good thin film semiconductor device as described above in a large area uniformly and stably.

The present invention has been made in view of the above circumstances, and its object is to obtain good semiconductor device characteristics in a low temperature process in which the maximum process temperature is about 600 ° C. or less in a MIS thin film semiconductor device. And a method of manufacturing such a thin film semiconductor device uniformly and stably over a large area.

[0010]

According to the present invention, a step of forming a silicon film on a substrate at 600 ° C. or lower, a step of increasing the crystallinity of the silicon film by heat treatment at 600 ° C. or lower, and a plasma irradiation are performed. The step of depositing a silicon oxide film on the silicon film and the ion of the impurity element by a mass non-separation type ion implantation apparatus using a mixture of a hydride gas of an impurity serving as a donor or an acceptor and a hydrogen gas as a source gas. And a step of accelerating ions of the hydride of the impurity element and hydrogen ions to a predetermined energy and implanting them into the silicon film through the silicon oxide film. The silicon oxide film is formed by an electron cyclotron resonance plasma CVD method.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings, but the present invention is not limited to the following embodiments.

Reference Example 1 FIGS. 1 (a) to 1 (e) are sectional views showing a manufacturing process of a silicon thin film semiconductor device constituting a MIS field effect transistor having a self-unaligned staggered structure in Reference Example 1. It is the figure shown.

In this reference example 1, as the base substrate 101, 2
35 mm square fused silica glass was used, but of course the type and size are not limited as long as it is a substrate or base material that can withstand the maximum process temperature of 600 ° C. For example, in addition to a normal glass substrate, a semiconductor substrate such as a silicon wafer and an LSI obtained by processing them, a three-dimensional LSI, or a silicon substrate.
Ceramic substrates such as carbide, alumina, and aluminum nitride can also be used as the base substrate.

First, the base substrate 101 is immersed in an organic solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, or cyclohexanone, and ultrasonic cleaning is performed. After the cleaning, drying is performed in nitrogen or under reduced pressure, ultrasonic cleaning is further performed with ethanol, and then water cleaning is performed with pure water bubbled with nitrogen. Next, the base substrate 10
1 was immersed in boiling 60% concentration of nitric acid for 5 minutes, and further washed in pure water with nitrogen bubbling. When a substance such as a metal that is corroded by acid or deteriorates and is used as a substrate is used, the cleaning by nitric acid is not required. Further, in the case of washing with this strong acid, sulfuric acid can be used as the acid in addition to nitric acid.

2000 Å of silicon dioxide film (SiO ₂ film) 102 to be a base protection film was deposited on the thus cleaned quartz substrate by atmospheric pressure chemical vapor deposition (APCVD method). The underlying SiO ₂ film 102 is necessary for stabilizing the film quality of a silicon thin film to be deposited later and the performance of a thin film transistor using the same when using various substances as described above as a substrate. At the same time, for example, when ordinary glass is used as the substrate 101, mobile ions such as sodium contained in the glass are also generated in the substrate 101.
Also, when various ceramic plates are used, they also play a role of preventing the sintering aid raw material added to the substrate from diffusing into the transistor section. In addition, the metal plate is the substrate 10
When used as 1, the base Si is used to ensure insulation.
O ₂ is essential. Moreover, in the three-dimensional LSI element,
It corresponds to an interlayer insulating film between transistors and between wirings.
The substrate temperature at the time of depositing the underlying SiO ₂ film 102 is 300 ° C.
84 silane 600 SCCM diluted to 20% with nitrogen
It was deposited by APCVD with 0 SCCM oxygen. At this time, the deposition rate of the SiO ₂ film was 3.9 Å / sec.

Then, a silicon thin film 103 containing impurities serving as a donor or an acceptor was deposited by a low pressure CVD method. In Reference Example 1, phosphorus was selected as an impurity for the purpose of producing an n-type transistor.
Group 6 and 6 elements, if P type, boron and other groups 2,
Group 3 elements can be added as impurity elements. The silicon thin film 103 containing the impurities is to be a source / drain region at a site, and the impurities are deposited by CVD as in Reference Example 1.
In addition to the method of adding impurities, first, an intrinsic silicon film containing no impurities is formed, and then the impurities are diffused and added from the vapor phase or the solid phase in contact with the intrinsic silicon film. Then, there is a method of implanting into the intrinsic silicon film. By using the method of adding impurities by the diffusion method or the ion implantation method after forming the intrinsic silicon film, it becomes possible to add the impurity only to a desired portion of the intrinsic silicon film. A self-aligned transistor in which the source end or the drain end is self-aligned becomes possible, and the current density or specific resistance in the silicon film is changed by changing the impurity concentration to be changed in each part. It is possible to flush the water. Since phosphorus was selected as the impurity in Reference Example 1, the silicon thin film 103 containing the impurity was formed by using a gas in which phosphine (PH ₃ ) and silane were mixed.
500Å accumulated.

In this reference example 1, 200 SCCM of monosilane, 6 SCCM of helium / phosphine mixed gas of 99.5% of helium and 0.5% of phosphine, and 100 SCCM of helium were placed in a low pressure CVD furnace having a volume of 184.5 l. It was flown and deposited at a deposition temperature of 600 ° C. and a furnace pressure of 100 mtorr. The deposition rate at this time was 29.6 Å / min, and the sheet resistance immediately after film formation was 2,025 Ω / □.

Next, a resist is formed on the silicon thin film, and the thin film is patterned by using a mixed plasma of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to form source / drain regions 103. (FIG. 1 (a)). Then, impurities such as residual resist are removed by washing in boiling nitric acid for 5 minutes, and then immersed in 1.67% hydrofluoric acid for 20 seconds to remove the natural oxide film on the surface of the source / drain region 103.
Immediately, a silicon thin film to serve as a channel portion was deposited by the low pressure CVD method.

At this time, the volume of the low pressure CVD reactor is 184.
At 51, the substrate is placed horizontally near the center of the reactor. The raw material gas and a dilution gas such as helium, nitrogen, argon, hydrogen, etc. are introduced into the furnace from the lower part of the reaction furnace and exhausted from the upper part of the reaction furnace as needed. Outside the reactor made of quartz glass, there are heaters divided into 3 zones,
By adjusting them independently, a soaking zone is formed at the desired temperature near the central part of the reactor. This soaking zone spreads at a height of about 350 mm, and the temperature difference within that range is, for example, 6
When set to 00 ° C, it is within 0.2 ° C. Therefore, if the distance between the inserted substrates is 10 mm, it is possible to process 35 substrates in one batch. In Reference Example 1, 17 substrates were installed in the soaking zone at intervals of 20 mm.

Exhaust was carried out by directly connecting a rotary pump and a mechanical booster pump, and the pressure in the reaction furnace was measured by a diaphragm type pressure gauge (MKS Corp. Baratron Manometer) whose measured value did not depend on the type of gas. 5 reactors
When the temperature of the reactor was kept at 50 ° C and the gas inlet valve was closed and both pumps were evacuated, the reactor internal pressure was 0 mtorr.
Therefore, the background vacuum degree is at most about 10 ⁻⁴ torr.

Source / drain regions 103 are formed,
The substrate from which the native oxide film on the surface of the region was removed was immediately inserted into the low pressure CVD furnace with the front side facing downward. The temperature inside the reaction furnace at the time of insertion is kept at about 395 ° C to 400 ° C. This is to reduce the formation of a natural oxide film on the source / drain regions 103 as much as possible.
It is desirable that the temperature inside the reaction furnace at the time of insertion is as low as possible. For example, it is possible to set the temperature in the reaction furnace at the time of insertion to room temperature, but in this case, it takes several hours or more to raise the temperature in the reaction furnace to the deposition temperature, and the number of arrows to return to room temperature after deposition. It takes time. About 4 SL in the reaction furnace when inserting the substrate
Nitrogen of M to 10 SLM is flowed to keep the inside of the reaction furnace in an inert atmosphere. Furthermore, about 6 SLM or more near the entrance of the reactor
A nitrogen curtain is formed with 20 SLM of nitrogen to minimize the flow of air into the reaction furnace when the substrate is inserted.
When moisture and oxygen in the air enter the reaction furnace, they are adsorbed by the Si layer on the inner wall of the reaction furnace or react with Si and remain in the reaction furnace, and are removed during the deposition of the silicon film that becomes the channel part. It appears as a gas and causes deterioration of the film quality of the deposited silicon film.

After inserting the substrate, vacuuming and leakage inspection were performed. In the leak test, all the valves leading to the reactor were closed to completely isolate the reactor, and the change in pressure inside the reactor was examined.
In Reference Example 1, the temperature inside the reaction furnace was 400 ° C. and, after complete isolation for 2 minutes, the pressure inside the reaction furnace was 1 mtorr or less. After confirming that there is no abnormality in the leakage inspection, the temperature inside the reaction furnace is raised from the insertion temperature of 400 ° C. to the deposition temperature. In this reference example 1, since the silicon thin film to be the channel portion was deposited at 550 ° C., it took 1 hour to raise the temperature. It takes about 35 minutes for the temperature in the furnace to reach the deposition temperature of 550 ° C., but in order to sufficiently release the degas from the reaction furnace wall, the temperature rising period of at least 1 hour or more, preferably several hours is desirable. .
During this temperature rising period, the two pumps are in an operating state and continue to flow an inert or reducing gas having a purity of at least 99.995%. These gas species can be pure gases such as hydrogen, helium, nitrogen, neon, argon, xenon, and krypton, and also mixed gases of these gases. In this Reference Example 1, helium having a purity of 99.9999% or more is used as 350
SCCM flow continues, reactor pressure is 80.7 ± 1.2 mtorr
It was.

After reaching the deposition temperature, a predetermined amount of silane, which is a source gas, or a mixed gas of silane and a diluent gas is introduced into the reaction furnace to deposit the silicon thin film 104. As the dilution gas, the same kind of combination as the gas that has been flown during the previous temperature rising period can be used, but preferably the purity of each gas is 9
9.999% or more is good. In this reference example 1, a silicon thin film 104 was deposited by using 100 SCCM of silane having a purity of 99.999% or more without using a diluent gas. At this time, the pressure inside the reactor is adjusted by adjusting the degree of opening and closing of the conductance valve installed between the reactor and the mechanical booster pump.
It was maintained at 398.6 ± 1.9 mtorr. In the first reference example, the silicon thin film 104 that becomes the channel portion is 21.2 Å / m.
It was deposited to a film thickness of 248Å at a deposition rate of in (Fig. 1
(B)).

In this reference example 1, the deposition of the silicon thin film was performed by LP.
Although the CVD method was used and monosilane was used as the source gas, the plasma CVD method, the APCVD method, the sputtering method or the like may be used instead. In addition, the source gas is not limited to monosilane, but higher order silanes such as disilane and trisilane, and dichlorosilane can also be used. Of course, it is also possible to deposit a silicon thin film by a combination of the above various CVD methods and the above various raw materials.

Next, the substrate thus obtained was subjected to heat treatment to promote crystallization of the silicon thin film 104 and increase the number of crystal grains. The heat treatment furnace is a vertical furnace, which is usually kept at 400 ° C, and nitrogen gas with a purity of 99.999% or more is used for 20 SL.
The flow of M is continued to keep the inside of the heat treatment furnace in an inert atmosphere. The substrate that had reached temperature equilibrium with room temperature was placed in a vertical heat treatment furnace at 400 ° C. for 17 minutes. Keep the temperature at 400 ° C for 30 minutes after insertion, and keep the temperature in the furnace at 400 ° C regardless of the position of the substrate.
After reaching the uniform temperature of ° C, the temperature of the heat treatment furnace is raised to 600 ° C. By holding at 400 ° C. for 30 minutes first, the same thermal history can be obtained anywhere regardless of the position of the substrate, and the crystallization of the silicon thin film can be performed uniformly. Since 20 SLM of nitrogen continues to flow into the heat treatment furnace and the volume of the heat treatment furnace is about 176 l, this 40
Preheating at 0 ° C. completely replaces the inside of the heat treatment furnace with a nitrogen atmosphere. The temperature rise from 400 ° C. to 600 ° C. is performed over about 1 hour, and after reaching the temperature equilibrium at 600 ° C., the crystallization of the silicon thin film proceeds by the heat treatment for 7 hours or more. In this reference example 1, 23 after reaching 600 ° C.
Heat treatment was applied for an hour.

The silicon thin film thus obtained was patterned with a resist and then etched by a mixed plasma of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to form a channel portion silicon thin film 105. (Fig. 1
(C)) The silicon thin film formed in Reference Example 1 was subjected to vacuum plasma discharge of 15 Pa with a ratio of CF ₄ and O ₂ of 50 SCCM to 100 SCCM, and the etching was 2.1 Å / sec when the output was 700 W. Had speed.

Next, this substrate was washed with boiling nitric acid having a concentration of 60%, and further washed with a 1.67% hydrofluoric acid aqueous solution.
Immersion for 0 seconds to remove the native oxide film on the source / drain region 103 and the channel silicon thin film 105 to expose a clean silicon surface, and immediately thereafter, an electron cyclotron resonance plasma CVD device (ECR-PECVD device)
Then, a SiO ₂ film 106 to be a gate insulating film was deposited.
(FIG. 1D) ECR-PECVD used in Reference Example 1
The outline of the apparatus is shown in FIG. At the time of depositing the gate insulating film, a microwave of 2.45 GHZ is guided to the reaction chamber 202 through the waveguide 201, and 100 SCCM of oxygen introduced from the gas introduction pipe 203 is first turned into plasma. At this time,
The microwave output is 2250 W, and the external coil 204 installed outside the reaction chamber 202 allows the reaction chamber 202
By applying a magnetic field of 875 Gauss to the oxygen plasma inside, the electrons in the plasma satisfy the ECR condition. This oxygen plasma is drawn out of the reaction chamber by the divergent magnetic field, and the substrate 205 placed vertically to the plasma is removed.
Irradiate for 0 seconds. A heater 206 is provided on the back surface of the substrate 205.
However, the entire substrate was kept at 100 ° C. At this time, the pressure in the reaction chamber was 1.85 mtorr. Immediately after the oxygen plasma outlet, another gas introducing pipe 207 is provided, and after the oxygen plasma is sufficiently stabilized for 10 seconds, the silane 60SCCM having a purity of 99.999% or more is supplied to the oxygen plasma through the gas introducing pipe 207. Mix in. The substrate thus obtained is irradiated with the oxygen-silane mixed plasma thus obtained for 30 seconds so that the SiO ₂ film 106 serving as a gate insulating layer is formed into 150
0Å was deposited (Fig. 1 (d)). At this time, the pressure in the reaction chamber was 2.35 mtorr.

Next, chrome was deposited 1500 Å by the sputtering method, and the gate electrode 107 was formed by patterning. At this time, the sheet resistance value is 1.356 ± 0.047Ω /
It was □. Chromium was used as the gate electrode material in this reference example 1, but other conductive materials can of course be used, and the formation method is not limited to the sputtering method, and the vapor deposition method or C
VD method and the like are also possible. Then, a SiO ₂ film to be the interlayer insulating film 108 was deposited by 5000 Å by the APCVD method. This deposition was performed under exactly the same conditions as the deposition of the underlying SiO ₂ film 102 in Reference Example 1, except that only the deposition time was changed. After forming the interlayer insulating film, contact holes are opened, and source / drain extraction electrodes 109 are formed by a sputtering method or the like to complete the transistor (FIG. 1E). In this reference example 1, aluminum was used as a source / drain extraction electrode material and deposited by sputtering to a film thickness of 8000Å to form a source / drain extraction electrode. At this time, the sheet resistance of the deposited aluminum film is 42.48 ± 2.0.
It was 2 mΩ / □.

An example of the characteristics of the thin film transistor (TFT) prototyped in this manner is shown by the Vgs-Ids curve in FIG.
-A. Here, the source-drain current Ids was measured at a source-drain voltage Vds = 4V and a temperature of 25 ° C. Transistor size is channel length L = 1
The width was 0 μm and the width W was 10 μm. Vds = 4V, Vg
The on-current when the transistor was turned on at s = 10V was measured on five transistors in the center and square of the 235 mm square substrate, and ION = 4.65 ± 0.39 μA. A thin film semiconductor with good transistor characteristics. The device is obtained.
Also, the field effect transfer μo and the trap density Nt (J. Levinson et.
al. J. Appl. Phys 53 . 1193.1
982) is μo = 25.85 ± 0.96 cm ² /
v. sec, Nt = (6.81 ± 0.15) × 10 ¹¹ 1
It was / cm ² . For comparison, 3-b in FIG. 3 shows the transistor characteristics of a thin film semiconductor device manufactured according to an example of the conventional technique. That is, a thin film semiconductor device was prepared by the same steps as those in Reference Example 1 except that the channel portion silicon thin film was deposited at 600 ° C. by the low pressure CVD method and the heat treatment was not performed for 24 hours. At this time, the apparatus for depositing the channel silicon thin film by the low pressure CVD method is the same as the apparatus used in this reference example 1, and the source gas monosilane is 12.
5 SCCM was flown, the pressure in the reaction furnace was 9.0 mtorr, and the deposition rate was 11.75 Å / min. The on-current of the TFT in this example of the prior art is Ids =
At 0.91 ± 0.12 μA, the field effect mobility is μo = 4.
75 ± 0.20 cm ² / v. sec, capture density Nt =
It was (5.18 ± 0.13) × 10 ¹¹ 1 / cm ² . In addition to this, the silicon thin film in the channel portion is similarly subjected to low pressure CVD.
Method, 600 ° C. monosilane flow rate 12.5 SCCM, and a gate insulating film is deposited in the same process as in Reference Example 1, and then hydrogen plasma treatment is performed by an ECR-PECVD apparatus. A thin film semiconductor device was produced in the same process as 1. This is also an example of a conventional technique for performing hydrotreating. The hydrogenation treatment was performed after the gate insulating film was deposited by the ECR-PECVD apparatus shown in FIG. 2 and then evacuated, and then the temperature of the substrate 205 was raised to 300 ° C. for 1 hour by the heater 206. 125 SCCM of hydrogen gas with a purity of 99.9999% or higher is fed into the reaction chamber 2 through the gas introduction pipe 203.
02, the hydrogen plasma was set up. The microwave power was 2000 W and the pressure in the reaction chamber was 2.63 mtorr. Hydrogen plasma irradiation was performed for 30 minutes. When the TFT characteristics of the thin film semiconductor device thus prepared were measured, the on-current Ids = 0.96 ± 0.13 μA and the field effect mobility μo = 4.68 ± 0.22 cm ² / v. sec, the trap density Nt = (5.12 ± 0.13) × 10 ¹¹ 1 / cm ² . That is, in the present invention, for example, in comparison with the prior art in which the channel silicon film is deposited by the low pressure CVD method at 600 ° C. regardless of the presence or absence of the hydrogen plasma treatment, the field effect mobility is increased by about 5 times. Bring significant improvements.

Next, another example of the prior art will be compared with the present invention. That is, as another example of the prior art, although the formation of the channel portion silicon thin film is performed in the same manner as in Reference Example 1,
We will see a great advantage of the present invention over the prior art of depositing a gate insulating film by APCVD and the prior art of depositing a gate insulating film by APCVD followed by hydrogen plasma treatment. In the conventional process of depositing a gate insulating film by the APCVD method to create a thin film semiconductor device, the thin film semiconductor device is produced by the same process as in Reference Example 1 except that the gate insulating film is deposited at 1500Å by the APCVD method. did. APC
In the VD method, the substrate temperature is kept at 300 ° C, and 20% in nitrogen
Nitrogen containing silane, a silane mixed gas of 300 SCCM and oxygen of 420 SCCM were flowed, and about 140 SLM of diluting nitrogen was flowed together with these source gases to deposit a SiO ₂ film. The deposition rate was 1.85Å / sec. Transistor characteristics of the thin film semiconductor device according to the conventional technique thus produced are shown in 3-C of FIG. The on-current of this transistor is ION = 1.49 ± 0.05 μA, field effect mobility μ
o = 24.60 ± 0.72 cm ² / v · sec, and trap density Nt = (9.20 ± 0.15) × 10 ¹¹ 1 / cm ² . Comparing the present invention with this prior art, it becomes clear that the present invention has produced a very good thin film semiconductor device in which the trap level is significantly reduced and which rises sharply near the gate voltage Ov. In the conventional technique of depositing the gate insulating film by the APCVD method, the mobility can be increased as much as in the present invention, but in fact, the minimum value of the source / drain current is around -11v and the trap density is high, so The slope of was also not practical as a thin film semiconductor device. On the other hand, an example of another conventional technique is shown in 3-d of FIG. Here, although the channel portion silicon thin film is formed in the same manner as in Reference Example 1, this is a technique in which the gate insulating film is deposited by the APCVD method and then subjected to hydrogen plasma treatment. A gate insulating film is deposited under the same conditions as described above, and immediately thereafter, ECR-PE is performed.
A thin film semiconductor device was produced through the same steps as in Reference Example 1 except that the hydrogen plasma irradiation was performed by the CVD apparatus under the same conditions as described above. The characteristics of the TFT thus obtained are shown in FIG.
3-d. The on-current is Ids = 2.91 ± 0.
30 μA, electric field effect mobility μo = 24.51 ± 0.67
cm ² / v · sec, capture density Nt = (7.94 ± 0.1
5) It was × 10 ¹¹ 1 / cm ² . It can be seen that the present invention exhibits good characteristics in all parameters even when compared with the conventional technique using this plasma treatment. Also, in the transistor manufactured by the prior art that has been subjected to the hydrogen plasma treatment, one of the five transistors measured has a deviation of the threshold voltage Vth by about + 2V. The value of is not included. That is, the conventional technique using the hydrogen plasma treatment improves the transistor characteristics as compared with the conventional technique in which the hydrogen plasma treatment is not performed, but it is difficult to form a uniform transistor in a large area uniformly. In addition, the samples subjected to hydrogen plasma treatment have large lot-to-lot variations, making stable production difficult. In particular, the shift of the threshold voltage and the variation of the gate voltage value that minimizes the source / drain current are very large between lots. On the other hand, according to the present invention,
It can be seen that the transistor which is superior to the conventional one can be uniformly formed on a large area by eliminating the hydrogenation process that causes the variation.

Reference Example 2 A thin film semiconductor was manufactured by the same steps as in Reference Example 1 except that the deposition time of the silicon thin film (FIG. 1.104) to be the channel portion was changed to change the deposited film thickness of the silicon thin film 104. Created the device. In this reference example 2, the silicon thin film 104 is set to 190
Å, 280 Å, 515 Å, 1000 Å, 1100 Å, 1
645Å and six different film thicknesses were formed, and thin film semiconductor devices were prepared. FIG. 4 shows the result of the ratio of the on-current and the off-current of the thin film semiconductor device thus obtained plotted against the film thickness of the channel portion silicon film. As can be seen from this figure, the film thickness of the channel silicon film semiconductor layer is 500.
In the thin film semiconductor device having a thickness of Å or less, the on / off ratio was drastically improved, and good characteristics of 7 digits or more were obtained.

Reference Example 3 Reference is made to a thin film semiconductor device (off-set type thin film semiconductor device) having a structure in which at least one of a source region and a drain region does not overlap with a gate electrode through a gate insulating film. It was prepared by the same manufacturing method as in Example 1. In this reference example 3, the staggered thin film semiconductor device shown in FIG. 5A was prepared as an off-set thin film semiconductor device by performing alignment with high accuracy. Other structures are possible. For example, as shown in FIG. 5B, the source / drain region 503 is formed by implanting impurity ions in the intrinsic silicon thin film using the gate electrode 504 as a mask, and the gate electrode 505 shown in FIG. 5C is on the lower side. It is also possible to use an inverted staggered thin film semiconductor device in which the source / drain regions 507 are formed using the mask material 506.

In this reference example 3, the diameter of the base substrate is 75 mm.
An off-set type thin film semiconductor device was prepared by the same manufacturing method as in Reference Example 1 except that the fused silica glass in Example 1 was used. That is, first, the substrate is washed, a base SiO ₂ film is deposited by the APCVD method or the like, and then a phosphorus-added silicon film is LPCVD-deposited.
Then, the source / drain regions 501 are formed by depositing by the method and further patterning. Here, the distance between the source and drain regions, which later becomes the channel length L, was 10.5 μm. Then, in the same manner as in Reference Example 1, a silicon thin film serving as a channel portion was deposited at a deposition rate of 21.2Å / min for 248
Deposited to a film thickness of Å. However, in Reference Example 1, the substrate was inserted into the reaction furnace with the front side facing down, but in Reference Example 3, the substrate with a diameter of 75 mm was placed on the 235 mm square dummy quartz plate with the front side facing upward and inserted into the reaction furnace. did. Reference example 1 below
A heat treatment was performed by the same manufacturing method as above, a gate insulating layer was deposited, and a gate electrode 502 was further formed. The width of the gate electrode 502 was 10.0 μm, and high precision alignment was performed so that the center of the source-drain distance of 10.5 μm and the center of the gate electrode width of 10.0 μm coincided with each other. As a result, the distance (offset distance) between the end position of the gate electrode and the end of the source region in the channel region is 0.
It becomes 25 μm. After that, an interlayer insulating film was deposited by the same manufacturing method as in Reference Example 1, a contact hole was opened, and wiring was performed using aluminum to complete a thin film semiconductor device.

An example of the transistor characteristics of the thin film semiconductor device thus prepared is shown in FIG. 6 by the Vgs-Ids curve.
shown in a. 6A shows transistor characteristics of the self-unaligned staggered structure thin film semiconductor device manufactured as a prototype in Reference Example 1. FIG. As is clear from the figure, in Reference Example 3, it is possible to significantly reduce the leak current generated when the gate voltage is negative. In fact, in Reference Example 3, the source / drain current is 0.1 when the gate voltage is −2.5 V or less.
It is suppressed to about pA. 6-b of FIG. 6 shows, for comparison, transistor characteristics obtained when an offset type thin film semiconductor device is manufactured according to the conventional technique of Reference Example 1.
That is, the silicon thin film in the channel part is a reduced pressure CV of 600 °
Deposited by D method, source-drain distance 10.5 μm
And the center of the gate electrode width of 10.0 μm are aligned with high precision alignment to produce an offset type thin film semiconductor device. Therefore, 6-b of FIG. 6 can be directly compared with 3-b of FIG. 6 of the transistor characteristics of the conventional self-unaligned staggered thin film semiconductor device. Even in the off-set type thin film semiconductor device according to the conventional technology, it is possible to keep the leakage current as low as about 0.1 pA or less. The positive characteristics of the transistor, such as frequency, have also deteriorated, and it has been impractical. For example, the on-current of the offset type thin film semiconductor device according to the conventional technique is Ids = 0.090 ± 0.01 μA, which is one or more digits lower than that of the self-unmatched thin film semiconductor device. The mobility at this time is also μo = 3.33 ±
Similar to 0.15 cm ² / v · sec, it is deteriorated by about 30%. For this reason, the manufacturing of offset type thin film semiconductor devices according to the prior art was not worth it. In contrast,
In Reference Example 3, as shown by 6-a in FIG. 6, the leak current is kept low and the on-current is kept high.
In this reference example 3, the on-current is Ids = 3.71 ± 0.
43 μA is obtained, which is almost comparable to the on-current of the self-non-matching type thin film semiconductor device. Further, in Reference Example 3, the mobility is also μo = 22.00 ± 0.95 cm ² / v · se
It showed a good value of c.

Example 1 In Reference Example 3, an offset type thin film semiconductor device was produced by performing high precision alignment. In FIG. 5B, an intrinsic silicon film is deposited and a gate electrode is patterned, An offset type thin film semiconductor device was prepared by adding impurity ions. This method will be described in detail.

FIGS. 7A to 7D are sectional views showing the structural steps of the silicon thin film semiconductor device which constitutes the MIS field effect transistor of the offset type staggered structure according to the first embodiment. First, a substrate 701 similar to that of Reference Example 1
After cleaning the SiO ₂ film, a SiO ₂ film is used as a base protective film 702.
Accumulate about 000Å. Then, the first silicon film is applied to 30
A silicon film 703 to be a pad is formed by depositing 0 Å or more and patterning. In the second embodiment, as the first silicon film, the deposition temperature of 600 is obtained by using the LPCVD apparatus in which the channel portion silicon film is deposited in the first reference example.
℃ silane flow rate 12.5SCCM deposited on 1250Å,
Other than this, the same LPCVD apparatus is used and the deposition temperature is 55
Depositing a silicon film at about 0 ° C., using disilane (Si ₂ H ₆ ) as a source gas at a deposition temperature of about 450 ° C., or depositing a silicon film at about 250 ° C. by PECVD. Is also possible. Process maximum temperature 600 ℃
Any method may be used as long as the film forming temperature does not exceed the range. Next, a second silicon film 704 is deposited. The thickness of this second silicon film is about 300 Å or more, and the resistance value of the source / drain region after the impurity implantation is in the channel region when the transistor is operated. If the resistance value is sufficiently lower than the resistance value, the first silicon film or the silicon film 703 to be the pad is not required. In the present Example 1, the second silicon film 704 was deposited by the same method as the silicon thin film to be the channel portion in Reference Example 1. That is, LPCVD
Method using monosilane as a raw material gas and a deposition temperature of 550 ° C.,
Silane flow rate 100 SCCM Deposition rate 21.2 Å / min 2
It was deposited to a film thickness of 50Å. However, the second silicon film formation method is similar to the first silicon film, and the maximum process temperature 600
Any method is possible as long as the film forming temperature does not exceed ℃. For example, the second silicon film also has a deposition temperature of 60.
0 ℃, silane flow rate 12.5SCCM, reactor pressure 9.0mt
It may be deposited by orr, or it is possible to form a film at a lower temperature by using a higher order silane such as disilane or trisilane as a source gas. In this way, the second silicon film 704 is formed by some method (FIG. 7B), and after patterning, the gate insulating layer 70 is formed by the same method as in Reference Example 1.
5 was formed. That is, SiO ₂ is formed by the ECR-PECVD method.
The film was deposited at 1500Å. As a method for forming the gate insulating layer 705, when the second silicon film 704 is a polycrystalline silicon film, it can be formed by the APCVD method. Next, a metal film or the like to be the gate electrode is formed. In Example 1, a silicon film to which phosphorus was added at a high concentration was used as the gate electrode material. Here, the deposition temperature is 600 by the LPCVD method.
℃, monosilane 200SCCM, helium 99.5% and phosphine 0.5% helium-phosphine mixed gas 6SCCM and helium 100SCCM flow, furnace pressure 100
It was deposited with mtorr to a film thickness of 3000Å. The sheet resistance value immediately after film formation was 744 Ω / □. Subsequently, a resist is applied, and after patterning the resist, CF ₄
The phosphorus-added silicon film was patterned by the mixed plasma of oxygen and O ₂ . The ratio of CF ₄ and O ₂ is 200 SCCM each
Patterning was performed with an incident wave output of 700 W at 200 SCCM. At this time, the etching rate of the phosphorus-added silicon film is 1
Etching was performed for 5 minutes and 57 seconds at 5.4 Å / sec to form a gate electrode 706. Since the film thickness of the phosphorus-added silicon film was 3000 Å, the width of the gate electrode was narrowed by 2,500 Å in each of the left and right sides as compared with the resist 707 due to this plasma etching (FIG. 7C). Next, impurity ions are added while the resist 707 used for forming the gate electrode 706 is left without being peeled off. Example 1
Then, phosphorus was selected as an impurity to aim at an n-type thin film semiconductor device, but of course other elements are possible depending on the purpose. In the present Example 1, impurity ion addition was performed using an ion implanter without a mass spectrometer. A phosphine having a concentration of 5% diluted in hydrogen was used as a source gas, and it was implanted at a concentration of 3 × 10 ¹⁵ 1 / cm ² at an accelerating voltage of 110 kV. In this way, the first silicon film and a part of the second silicon film become the source / drain regions 708, and the resist 707 used for forming the gate electrode has a film thickness of about 2
Since the thickness is about μm, the second silicon film located thereunder is not ion-added, and reaches the channel portion 709 (FIG. 7C). Further, according to this method, an offset type thin film semiconductor device is produced. Next, after removing the resist 707 for forming the gate electrode, the substrate is subjected to heat treatment at 600 ° C. for 7 hours or more to activate the additive impurity ions and crystallize when the crystallinity of the channel portion silicon film 709 is insufficient. Promote the transformation. In Example 1, the same heat treatment as in Reference Example 1 was performed at 600 ° C. for 23 hours in a nitrogen atmosphere. Then, as an interlayer insulating film, SiO ₂ 71
0 was deposited to 5000 Å by the APCVD method or the like, and further hydrogen was implanted at 5 × 10 ¹⁵ 1 / cm ² at an accelerating voltage of 80 kV by an ion implanter without a mass spectrometer.
The contact hole is opened and the wiring 711 is made of aluminum or the like to complete the offset type thin film semiconductor device.

When the transistor characteristics of the offset type thin film semiconductor device thus produced were measured, L = W = 10 μ
m, Vds = 4V, the on-current is 3.4 μA, and the minimum source / drain current is 0.09 when Vgs = −3.5V.
The off current defined by pA and Vgs = -10V is 0.2.
The leakage current when the transistor is off was kept low at 8 pA, and a good on-current could be obtained.

After the source and drain regions are formed in the offset type thin film semiconductor device as described in the first embodiment,
By applying heat treatment, a thin film semiconductor device having a high on-current and a small leak current can be produced, but the present invention is by no means limited to the method of manufacturing an offset type thin film semiconductor device described in detail in the first embodiment. There is no. For example, as the method of forming the offset type thin film semiconductor device in the first embodiment, a resist having a width wider than the gate electrode width is used as the implantation mask, but there are various other methods. For example, an offset type thin film semiconductor device can be produced by using a metal as a gate electrode, oxidizing the surface and side surfaces of the gate electrode to narrow the gate electrode, and then implanting impurity ions. Also, FIG.
As shown in (c), even in the inverted staggered structure, the offset thin film semiconductor device can be obtained by making the width of the mask material 506 wider than the gate electrode 505. The present invention is effective for offset type thin film semiconductor devices manufactured by any of these manufacturing methods.

Reference Example 4 FIGS. 8A to 8F are sectional views showing a manufacturing process of a silicon thin film semiconductor device for forming a MIS field effect transistor.

In this reference example 4, the insulating substrate 801 is 2
35 mm square quartz glass was used, but of course the type and size are not limited as long as it is a substrate or base material that can withstand a temperature of 600 ° C. For example, a three-dimensional LSI formed on a silicon wafer is also possible as the base substrate. First, a quartz glass substrate 801 that has been subjected to organic cleaning and acid cleaning
A base SiO ₂ film 802 is formed on the upper surface by atmospheric pressure chemical vapor deposition (A
PCVD method). The base SiO ₂ film 802 is formed by a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, and oxygen of 84.
It was deposited at 0 SCCM and about 140 SLM nitrogen. At this time, the deposition rate was 3.9 Å / sec, and the deposition time was 8 minutes 33 seconds. Next, a silicon thin film 803 containing impurities serving as a donor or an acceptor is formed by low pressure chemical vapor deposition (LPCV).
(D method) (FIG. 8A). In Reference Example 4, phosphorus is selected as an impurity, and phosphine (PH ₃ ) 0.0
3 SCCM and 200 SCCM of silane (SiH ₄ ) were used as source gases, and 1500 Å was deposited at a deposition temperature of 600 ° C. The deposition rate at this time was 30Å / min, and the sheet resistance immediately after film formation was 1
It was 951 Ω / □. Next, a resist is formed on the silicon thin film 803, and patterning is performed with a mixed plasma of carbon tetrafluoride (CF ₄ ), oxygen (O ₂ ), nitrogen (N ₂ ) and the like to form source / drain regions 804. . Then, after removing the dirt and natural oxide film on the surface of the region 804, the amorphous silicon thin film 805 is immediately depressurized C
It was deposited by the VD method. (FIG. 8 (b)) The low pressure CVD apparatus in Reference Example 4 is 184.5 l, and the reaction chamber is made of quartz glass. Heaters divided into three zones are installed outside the reaction chamber, and by adjusting these three heaters independently, an isothermal region is formed near the center of the reaction chamber at a desired temperature. The substrate was placed horizontally in this isothermal region and an amorphous silicon thin film 805 was deposited. For the amorphous silicon thin film 805, disilane (Si ₂ H ₆ ) 100 SCCM was used as a source gas, and helium (He) 100 SCCM was used as a diluent gas. The deposition temperature was 450 ° C. Evacuation of the low pressure CVD furnace used for depositing the amorphous silicon thin film 805 of Reference Example 4 is performed by directly connecting a mechanical booster pump and a rotary pump. Mechanical booster
A conductance valve is installed between the pump and the reaction furnace, and the pressure inside the reaction chamber can be adjusted and maintained at a desired value by adjusting the opening / closing amount of this valve. In Reference Example 4, while depositing the amorphous silicon thin film 805,
The pressure in the reaction chamber was kept at 306 mtorr. Deposition rate is 1
An amorphous silicon thin film 805 was deposited at a thickness of 307Å at 8.07Å / min. Next, a resist is formed on the thus-formed amorphous silicon thin film 805, and patterning is performed with a mixed plasma of carbon tetrafluoride, oxygen, nitrogen, etc., and a strong amorphous silicon thin film is eventually formed at a position which becomes a channel part. Leaving 806.

Next, this substrate is boiled at a concentration of 60%.
The substrate is washed with nitric acid as described above and further immersed in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to remove the native oxide film on the source / drain region 804 and the amorphous silicon thin film 806 left at a position where a channel portion will be formed. Immediately after the appearance of a clean silicon film, oxygen plasma 807 was irradiated by an electron cyclotron resonance plasma CVD apparatus (ECR-PECVD apparatus). (FIG. 8 (c)) An outline of the ECR-PECVD apparatus used in Reference Example 4 is shown in FIG. Oxygen plasma uses microwave of 2.45 GHz between waveguides 20
1 was introduced into the reaction chamber 202, and 100 SCCM of oxygen was introduced from the gas introduction pipe 203 to establish oxygen plasma. At this time, the pressure in the reaction chamber was 1.84 mtorr, and the microwave output was 2500 W. An external coil 204 is provided outside the reaction chamber, and the oxygen plasma is 875 Ga.
By applying a magnetic field of uss, the electrons in the plasma satisfy the ECR condition. The substrate 205 is placed perpendicular to the plasma, and the substrate temperature is kept at 300 ° C. by the heater 206. Oxygen plasma 807 was irradiated under this condition for 8 minutes and 20 seconds to oxidize the amorphous silicon thin film 806 left at a position which eventually becomes a channel part, and a SiO ₂ film 808 which becomes a part of the gate insulating layer was obtained. . At this time, the amorphous silicon thin film 809, which will eventually become the channel part, remains below the SiO ₂ film 808, which will become part of the gate insulating layer. (Fig. 8
(D)) Further, a SiO ₂ film 810 to be a gate insulating layer was continuously deposited without breaking the vacuum. This SiO ₂ film 810
Has a microwave output of 2250 W, a silane flow rate of 60 SCCM,
Oxygen flow rate 100 SCCM, substrate temperature 300 ° C, 18.75
Deposited for seconds. Pressure in the reaction chamber during deposition was 2.62
It was mtorr. The multi-layer film thus formed is subjected to a multi-wavelength dispersion ellipsometry (multi-wavelength spectroscopic ellipsometry: MOSPES MOSS-ES4G) to determine the film thickness of the remaining amorphous silicon film 809, which will eventually become the channel part, and the amorphous film. When the film thickness of the SiO ₂ film 808 formed by oxidizing the silicon film and the film thickness of the SiO ₂ film 810 deposited by the ECR-PECVD method were measured, the amorphous silicon thin film 809 was 205 Å, and the SiO ₂ film 8
08 was 120Å and the SiO ₂ film 810 was 1500Å. Also, at this time, SiO ₂ at a wavelength of 632.8 nm
The SiO ₂ film 808 had a refractive index of 1.42, and the SiO ₂ film 810 had a refractive index of 1.40.

Next, the substrate thus obtained was inserted into an electric heating furnace maintained at 600 ° C. and heat-treated for 48 hours.
At this time, nitrogen gas having a purity of 99.999% or more was continuously flowed in the electric heating furnace at 20 l / min to keep an inert atmosphere. By the heat treatment at 600 ° C. in the inert atmosphere, the amorphous silicon thin film remaining in the channel portion is crystallized and converted into the silicon thin film 811 forming the channel portion. (FIG. 8 (e)) Then, this substrate is again E
The substrate was placed in a CR-PECVD apparatus, and the substrate heat-treated using the apparatus was irradiated with hydrogen plasma. At this time, the substrate temperature is 300 ° C., the microwave output is 2000 W, and hydrogen is 1
Hydrogen plasma was established by flowing 00 SCCM. In this state, the pressure inside the reaction chamber was 1.97 mtorr. Hydrogen plasma irradiation was performed for 45 minutes.

Next, chromium was deposited by 1500 Å by a sputtering method, and a gate electrode 812 was formed by patterning. At this time, the sheet resistance value was 1.36 Ω / □. After that, a contact hole is formed in the gate insulating film, a source / drain extraction electrode 813 is formed by a sputtering method or the like, and patterning is performed, whereby the transistor is completed. (FIG. 8 (f)) In this reference example 4, aluminum having a film thickness of 8000Å was used as the source / drain extraction electrode material. The sheet resistance of aluminum at this time is 42
It was mΩ / □.

An example of the characteristics of the thin film transistor (TFT) prototyped in this manner is shown by the Vgs-Ids curve in FIG.
-A. Where Ids is the source-drain voltage,
It was measured at Vds = 4V and a temperature of 25 ° C. Transistor
The size of the channel part is L = 10 μm, width W = 10
It was 0 μm. The on-current when the transistor is turned on at Vds = 4V and Vgs = 10V is Ids = 34.5.
A thin film semiconductor device having good transistor characteristics of μA was obtained. Further, the field effect mobility obtained from the saturation current region of this transistor was 12.52 cm ² / v · sec. For comparison, 9-b of FIG. 9 shows the transistor characteristics of the thin film semiconductor device manufactured by the conventional technique. That is, in the prior art, a thin film semiconductor device was produced by the same steps as those in Reference Example 4 except that the channel silicon thin film was deposited at 600 ° C. by the low pressure CVD method and the oxygen plasma irradiation was not performed. . At this time, the apparatus for depositing the channel silicon thin film by the low pressure CVD method is the same as the apparatus for depositing the amorphous silicon thin film in Reference Example 4, the raw material gas monosilane is made to flow 24 SCCM, and the pressure in the reaction furnace is 13.8 mtorr. , Deposition rate is 19.00 Å / min
Deposited to a film thickness of 252Å. The on-current of this conventional TFT is Ids = 4.6 μA and the field-effect mobility is 4.40.
It was cm / v · sec. In addition to this, a silicon thin film in the channel portion is similarly deposited at 600 ° C. by the low pressure CVD method, and then oxygen plasma irradiation is performed before the gate insulating film is deposited. All other steps are the same as those in Reference Example 4. A thin film semiconductor device was prepared by using the above, and the TFT characteristics were measured. The TFT characteristics hardly changed with or without oxygen plasma irradiation, and the Vgs-Ids curve of the TFT subjected to oxygen plasma irradiation is shown in FIG.
9-b. At this time, the ON current of the TFT is Ids
= 4.7 μA, field effect mobility is 4.44 cm ² / v
It was sec. That is, the channel silicon thin film is
The effect of oxygen plasma irradiation is very small in the conventional technique of depositing by low pressure CVD at 00 ° C. 9-c in FIG. 9 shows a TFT of a thin film semiconductor device manufactured by another conventional technique.
The characteristics are illustrated. In this conventional technique, a thin film semiconductor device is manufactured by the same steps as those in the second embodiment except that the oxygen plasma irradiation is not performed in the fourth reference example. That is, this is a step in which an amorphous silicon thin film is first deposited as a channel portion silicon layer and then heat treatment at 600 ° C. is performed, but oxygen plasma irradiation is not performed before the gate insulating layer is formed. TF created by this conventional technique
T exhibits a depletion of -10V and the rising characteristic is not good. The on-current of this thin film semiconductor device is V
It was 12.1 μA at ds = 4 V and Vgs = 10 V, and the field-effect mobility was 9.94 cm ² / v · sec.

From these results, as shown in Reference Example 4, only when the amorphous silicon thin film to become the channel part is irradiated with oxygen plasma and then heat treatment is performed to crystallize the channel part silicon thin film, the thin film is formed. It can be seen that the transistor characteristics of the semiconductor device are significantly improved. This is because the surface of the amorphous silicon thin film was first oxidized by oxygen plasma, so that a clean MIS interface was formed and then crystallization proceeded. From this, it can be understood that the second embodiment of the present invention has remarkably good semiconductor characteristics as compared with the thin film semiconductor device manufactured by the conventional technique.

Example 2 After forming a silicon film and a silicon oxide film on an insulating material, impurities serving as donors or acceptors were added to the silicon film to form a conductive layer based on the silicon film.

In Example 2, a fused silica substrate having a diameter of 75 mm was used as the substrate. However, of course, any substrate may be used as long as it can withstand a heat treatment at about 600 ° C.
For example, a processed silicon substrate is also possible. First, a base SiO ₂ film is formed on the upper surface of the substrate which has been organically and acid-cleaned.
It was deposited by the PCVD method. The formation of the underlying SiO ₂ film is performed at a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, oxygen of 840 SCCM,
It was deposited with about 140 SLM of nitrogen. The deposition rate at this time is 3.
At 9Å / sec, the deposition time was 12 minutes 49 seconds. Next, a silicon film was deposited in the same manner as in Reference Example 1 by using the LPCVD apparatus used to deposit the channel portion silicon film in Reference Example 1. That is, the deposition temperature is 550 ° C., the silane flow rate is 100 SCCM, and the reaction chamber pressure is 400 mtorr.
A silicon film was deposited for 1 minute and 20 seconds. The film thickness of the silicon film thus obtained was 252Å.

Next, the substrate thus obtained was subjected to a heat treatment to enhance the crystallinity of the silicon film. This heat treatment method is the same as the heat treatment performed to increase the crystallinity of the silicon film 104 in Reference Example 1. That is, under nitrogen atmosphere at 600 ° C for 2
Heat treatment was performed for 3 hours. After the heat treatment was completed, the silicon film was patterned with a resist and further etched by a mixed plasma of CF ₄ and O ₂ to form a wiring pattern of the silicon film.

Subsequently, this substrate was washed with boiling nitric acid having a concentration of 60%, and further dipped in a 1.67% hydrofluoric acid aqueous solution for 20 seconds to remove the natural oxide film on the silicon film to reveal a clean silicon surface. And then ECR-PECVD immediately
A silicon oxide film was deposited with a device to a thickness of 1500 Å. Here, the deposition of the silicon oxide film was performed by the same method as the method of forming the gate insulating film in Reference Example 1. Next, using an ion implanter, impurities serving as a donor or an acceptor were added to the wiring formed of the silicon film. In the second embodiment, phosphorus was selected as an impurity to form the n-type conductive layer, but other elements can of course be used according to the purpose. In the second embodiment, impurity ions are added by using a bucket type non-separation type ion implanter. A phosphine having a concentration of 5% diluted in hydrogen was used as a source gas, and it was implanted at a accelerating voltage of 110 KV to a concentration of 3 × 10 ¹⁵ 1 / cm ² through a silicon oxide film. Next, this substrate was placed in a furnace kept at 300 ° C. in a nitrogen atmosphere and subjected to heat treatment. The heat treatment time was just one hour. After completion of heat treatment at 300 ° C. for one hour, contact holes were opened in the silicon oxide film, and an extraction electrode was formed from aluminum. When the resistance of the impurity-added silicon film wiring thus formed was measured, the sheet resistance value was 95% with a reliability coefficient of (71
± 15) kΩ / □ was measured. It was generally believed that it is impossible to add impurity ions to a thin film having a thickness of several hundred Å and activate the added ions at a low temperature of about 300 ° C. to obtain a conductive layer. However, in the present invention, the quality of the heat-treated silicon film is set to ECR-P on the silicon film.
By covering with a silicon oxide film deposited by the ECVD method,
Since we succeeded in improving the quality of the silicon film, such as reducing the capture density on the surface of the silicon film, the electron scattering density was lowered and it became possible for the first time to form a thin film conductive layer. By comparing this with the silicon film according to the conventional technique, the superiority of the present invention is clarified.

First, after depositing a silicon film at 600 ° C. by the LPCVD method, impurities are added to the silicon film of the prior art on which a silicon oxide film is formed by the ECR-PECVD method, and activation is performed at a low temperature of 300 ° C. An attempt was made to create a silicon film conductive layer. Here, the silicon film is made to flow at 600 ° C., the monosilane is made to flow at 12.50 SCCM, and the reaction chamber pressure is set to 9.2 mtor.
Impurity-added silicon film wiring was formed by the same process as in the present invention of Example 2 except that the film was deposited to a film thickness of 263Å by r. The sheet resistance of the silicon film of the prior art thus obtained was 1 GΩ / □ or more when measured at 5 points in the substrate, and virtually no current flowed.

Secondly, the silicon film is formed by heat treatment at 600 ° C. in the same manner as in the present invention of the second embodiment, and then A is formed.
An impurity was added to a conventional silicon film having a silicon oxide film formed by the PCVD method, and an attempt was made to form a silicon film conductive layer by activating the silicon film at a low temperature of 300 ° C. Here, the silicon oxide film is APCV
The substrate temperature was kept at 300 ° C by the D method, 300 SCCM of nitrogen / silane mixed gas containing 20% silane in nitrogen and 420 SCCM of oxygen were flowed, and about 140 SLM of diluting nitrogen was flowed together with these source gases to obtain 1500 Å. Deposited to a film thickness.
Except for this, the impurity-added silicon film wiring was formed by the same steps as those of the present invention of the second embodiment. The sheet resistance value of the conventional silicon film thus obtained was (175 ± 56) kΩ / □ with a 95% reliability coefficient. Then, this substrate was mounted on the ECR-PECVD apparatus again and subjected to hydrogen plasma treatment. Substrate temperature 30 for hydrogen plasma treatment
Flowing hydrogen 125SCCM at 0 ℃, microwave output 2000
W for 30 minutes. After the hydrogen plasma treatment, the resistance value at 5 points in the substrate was measured and the sheet resistance at 2 points was 1 GΩ.
It is above with / □, and the average value of the remaining 3 places is 158 kΩ
The standard deviation value was 68 kΩ / □.

It is understood that a high-quality silicon film can be obtained by coating the silicon film thus heat-treated at 600 ° C. or lower with the silicon oxide film formed by the ECR-PECVD apparatus. Therefore, as shown in Reference Example 1, the silicon film of the present invention is used for the channel portion of the thin film semiconductor device, and E
When a silicon oxide film formed by a CR-PECVD device is used as a gate insulating layer, a thin film semiconductor device having excellent characteristics can be obtained.
Further, as shown in the second embodiment, by adding impurity ions to the silicon film of the present invention, it becomes possible to obtain a silicon film conductive layer having a low resistance at a low temperature. Therefore, the silicon film of the present invention is not only effective for a thin film semiconductor device but also for a charge coupled device (C
It can be used very effectively as a non-single-crystal silicon film used in various electronic devices such as a gate electrode of CD) and wiring.

Reference Example 5 The mass number is changed by changing the step of adding impurity ions to the silicon film using the bucket type mass non-separation type ion implantation apparatus of the present invention in Example 2 to the mass separation type ion implantation apparatus. An attempt was made to form an impurity-doped silicon film conductive layer in exactly the same steps as in the present invention of Example 2 except that implantation of 31 monovalent ions of phosphorus was performed. In Reference Example 5, phosphorus ion is 90
I hit 3 × 10 ¹⁵ 1 / cm ^{2 with} KV. When the resistance of the thus-obtained impurity-added silicon film was measured, it was found that all 5 G locations in the substrate were 1 GΩ / □ and substantially no current flowed. This is because in the present invention of the second embodiment, impurities are added by using a mass non-separation type ion implanter and a hydrogen / phosphine mixed gas is used as a source gas, so that hydrogen ions are inevitably added when a phosphorus element is added to a silicon film. Is added simultaneously, and the defects generated during the ion addition are repaired by hydrogen ions. Therefore, the low resistance silicon conductive layer was formed at a low temperature only in the good quality silicon film of the present invention.

(Embodiment 3) FIGS. 10A to 10D are sectional views showing a process of manufacturing a silicon thin film semiconductor device constituting a MIS field effect transistor having a self-aligned staggered structure according to the third embodiment. It is the figure shown. First, after cleaning the substrate 1001 in the same manner as in Reference Example 1, a SiO ₂ film was used as the base protective film 1002.
Accumulate about 000Å. Then, the first silicon film 15
A silicon film 1003 to be a pad is formed by depositing about 00Å and patterning (FIG. 10A). In Example 3, as the first silicon film, the LPCVD apparatus in which the channel portion silicon film was deposited in Reference Example 1 was used to deposit 1500 at a deposition temperature of 600 ° C. and a silane flow rate of 12.5 SCCM.
The same LPCVD equipment was used to deposit a silicon film at a deposition temperature of about 550 ° C, but disilane (Si ₂ H ₆ ) was used as a source gas at a deposition temperature of about 450 ° C. It can be done by PECVD method 2
It is also possible to deposit a silicon film at about 50 ° C. If the film forming temperature does not exceed the process maximum temperature of 600 ° C,
Any method may be used. Next, a second silicon film 1004 is deposited. The thickness of the second silicon film is about 300 Å or more, and the resistance value of the source / drain region after the impurity implantation is in the channel region when the transistor is operated. If the resistance value is sufficiently lower than the resistance value, the first silicon film or the silicon film 1003 to be the pad is not required. In the third embodiment, the second silicon film 1004 is deposited by the same method as that of the silicon thin film which becomes the channel portion in the first reference example. That is, monosilane was used as a source gas by the LPCVD method, and the film was deposited at a film thickness of 250 Å at a deposition temperature of 550 ° C and a silane flow rate of 100 SCCM at a deposition rate of 21.2 Å / min. Then, the same heat treatment was performed as in Reference Example 1 to enhance the crystallinity of the silicon film. That is, under a nitrogen atmosphere 60
Heat treatment was performed at 0 ° C. for 23 hours. (FIG.10 (b)).
Next, after patterning the second silicon film, a gate insulating layer 1005 was formed by the same method as in Reference Example 1.
That is, the SiO ₂ film was deposited to 1500 Å by ECR-PECVD method.
Deposited. Next, a metal film or the like to be the gate electrode is formed. In Example 3, as the gate electrode material, 2000 Å
A chromium film having a film thickness of was used. The chromium film was formed by the sputtering method at a substrate temperature of 180 ° C. The sheet resistance value of chromium immediately after film formation was 994 mΩ / □. Subsequently, a SiO ₂ film of 3000 Å was deposited on the chromium by the APCVD method at a substrate temperature of 300 ° C. After that, patterning was performed with a resist to form a protective cap layer 1007 consisting of the gate electrode 1006 and the SiO ₂ film, and impurity ions were added. In the third embodiment, phosphorus was selected as the impurity to form the n-type thin film semiconductor device, but other elements can of course be used according to the purpose. In Example 3, impurity ion addition was performed by using an ion implanter without a mass spectrometer. Using phosphine having a concentration of 5% diluted in hydrogen as a raw material gas, 5 × 1 at an acceleration voltage of 110 kV
Implanted to a density of 0 ¹⁵ 1 / cm ² . In this manner, the first silicon film and a part of the second silicon film become the source / drain regions 1008, and the protective cap layer 1007 made of the SiO ₂ film is present. The film is not ion-added and reaches the channel portion 1009 (FIG. 10C). Next, the substrate was heat-treated at 350 ° C. for 2 hours in a nitrogen atmosphere to activate the added impurity ions. After that, as an interlayer insulating film, SiO
₂ Film 1010 is deposited 5000 Å, then contact
A hole is opened and wiring 1011 is made of aluminum or the like to complete a self-aligned thin film semiconductor device (FIG. 10D).

When the transistor characteristics of the self-aligned thin film semiconductor device thus produced were measured, L = W =
10 μm, Vds = 4 V, Vgs = 10 V, ON current is 4.89 μA, minimum source / drain current is Vgs
= -3.5 V, 0.21 pA, and Vgs = -10 V, the off-current defined is 2.65 pA, and the field effect mobility μo.
= 26.1 cm ² / v · sec, which is a very good self-aligned thin film semiconductor device.

For comparison, the channel silicon film is LP
A self-aligned thin film semiconductor device was manufactured by the same steps as those of the present invention of Example 3 except that the self-aligned thin film semiconductor device was manufactured by the CVD method at 600 ° C. However, as described in detail in Example 2, the conventional silicon film does not activate the doped impurity element in the thin film portion, and the resistance of the doped silicon film in the thin film portion is too high. Therefore, the on-current of the transistor is 47. It became unpractical as 0.9 pA. On the other hand, in the present invention of the third embodiment, the hydrogenated plasma treatment which is the main cause of the characteristic fluctuation is eliminated, and the good self-aligned thin film semiconductor device is successfully produced because the hydrogenated plasma treatment is limited in the low temperature process. As shown in Reference Example 2, this is because even if the film thickness of the channel portion silicon film semiconductor layer is reduced to 500 Å or less to improve the basic semiconductor characteristics, the thin film transmission according to the present invention of Example 2 is still possible. This is a result of forming the source / drain regions of the thin film portion at a low temperature easily by forming the conductive silicon film. In other words, activation of impurities serving as donors or acceptors cannot be achieved unless a silicon film having a film thickness of about 1000 Å or more is heat-treated at about 550 ° C. or more. Therefore, in the self-aligned thin film semiconductor device, the film thickness of the channel portion is necessarily 100.
It was about 0Å or more, and the characteristics were poor. In addition, after the gate insulating layer and the gate electrode are completed, heat treatment at about 550 ° C. or more is performed for the purpose of activating the additive impurity ions, so that the film quality of the gate insulating film deteriorates and hydrogenation treatment is indispensable. There was Further, since it was difficult to use a metal material as the gate electrode, the resistance of the gate line was high, and it was necessary to separately prepare the gate electrode and the gate line. However, according to the present invention, a metal material can be used as a gate electrode, and at the same time, hydrogen treatment, which is a main cause of variations, can be eliminated, and a thin film semiconductor device with high characteristics can be stably manufactured by a simpler manufacturing method. did.

[0057]

As described above, according to the present invention,
A silicon film is formed on a substrate, a silicon oxide film is formed on the silicon film, and impurities serving as donors or acceptors are mass-separated using a mixture of a hydride gas of the impurity element and a hydrogen gas as a source gas. Type ion implanter, the ions of the impurity element and the ions and hydrogen ions of the hydride of the impurity element are accelerated to a predetermined energy and implanted into the silicon film through the silicon oxide film to obtain a silicon film. The film quality can be improved, and the conductivity characteristics of the semiconductor device can be greatly improved.
It becomes possible to form a thin film semiconductor device having such excellent characteristics uniformly over a large area by a simple method.
It is possible to realize the multi-layered structure of I and the high performance and the low cost of the active matrix liquid crystal display using the thin film transistor.

[Brief description of drawings]

FIG. 1 is a sectional view of an element in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

FIG. 2 is a diagram showing an outline of an electron cyclotron resonance plasma CVD apparatus used in an example of the present invention.

FIG. 3 is a diagram showing the effect of the present invention.

FIG. 4 is a diagram showing an effect of the present invention.

FIG. 5 is an element cross-sectional view of a silicon thin film semiconductor device showing an embodiment of the present invention.

FIG. 6 is a diagram showing the effect of the present invention.

FIG. 7 is an element cross-sectional view in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

FIG. 8 is an element cross-sectional view in each step of manufacturing a silicon thin film semiconductor device showing an embodiment of the present invention.

FIG. 9 is a diagram showing the effect of the present invention.

FIG. 10 is an element cross-sectional view in each step of manufacturing a silicon thin film semiconductor device showing one embodiment of the present invention.

[Explanation of symbols]

Reference numeral 101 ... Base substrate 102 ... Base protection film 103 ... Source / drain region 104 ... Silicon thin film 105 ... Channel silicon thin film 106 ... Gate insulating film 107 ... Gate electrode 108 ... Interlayer insulating film 109 ... Source / drain extraction electrode 201 ... Waveguide Tube 202 ... Reaction chamber 203 ... Gas introduction tube 204 ... External coil 205 ... Substrate 206 ... Heater 207 ... Gas introduction tube 501 ... Source / drain region 502 ... Gate electrode 503 ... Source / drain region 504 ... Gate electrode 505 ... Gate electrode 506 Mask material 507 Source / drain region 701 Substrate 702 Base protection film 703 Pad silicon film 704 Second silicon film 705 Gate insulating layer 706 Gate electrode 707 Resist 708 Source / drain region 709 ... Channel silicon film 7 0 ... left length in the interlayer insulating film 711 ... wiring 801: insulating substrate 802 ... base SiO ₂ film 803 ... it becomes silicon thin film 804 ... source-drain regions 805 ... amorphous silicon thin film 806 ... one channel unit containing impurities position amorphous silicon thin film 807 ... oxygen plasma 808 ... SiO ₂ deposited with amorphous silicon thin SiO ₂ film 809 ... one channel unit to become remaining to have amorphous silicon thin film 810 ... ECR-PECVD method was formed by oxidizing a Film 811 ... Silicon thin film 812 constituting channel section ... Gate electrode 813 ... Source / drain extraction electrode 1001 ... Substrate 1002 ... Base protective film 1003 ... Silicon film 1004 serving as pad ... Second silicon film 1005 ... Gate insulating layer 1006 ... Gate electrode 1 07 ... protective cap layer 1008 ... source and drain regions 1009 ... channel portion silicon film 1010 ... interlayer insulating film 1011 ... wire

   ─────────────────────────────────────────────────── ─── Continued front page       (56) Reference JP-A-2-194620 (JP, A)                 JP-A 1-22027 (JP, A)                 JP 59-218728 (JP, A)                 JP-A-59-218727 (JP, A)

Claims (2)

(57) [Claims] 1. A step of forming a silicon film on a substrate at 600 ° C. or lower, a step of increasing crystallinity of the silicon film by heat treatment at 600 ° C. or lower, and a plasma irradiation to irradiate the silicon film on the silicon film. And a mixture of an hydride gas of an impurity serving as a donor or an acceptor and a hydrogen gas as a source gas, by a mass non-separation type ion implanter, the ion of the impurity element and the hydride of the impurity element are And a step of accelerating ions and hydrogen ions to a predetermined energy and implanting them into the silicon film through the silicon oxide film. 2. The method for manufacturing a thin film semiconductor device according to claim 1, wherein the silicon oxide film is formed by an electron cyclotron resonance plasma CVD method.