JP3483869B2 - Transistor characteristic evaluation circuit and characteristic evaluation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor characteristic evaluation circuit used for transistor characteristic evaluation after a semiconductor manufacturing process and a transistor characteristic evaluation method.

[0002]

2. Description of the Related Art Generally, PCM (Process Control Monitor) is used to measure transistor characteristics after a semiconductor manufacturing process.
or) or TEG (Test Elementary Group) is used for each individual transistor.

[0003]

However, although these measurements are evaluated by using a semiconductor parameter analyzer and a parametric tester, they measure only single transistors one by one. If a large number of measurements are required to examine variations in transistor characteristics and the distribution of characteristics within a wafer or lot, etc., measure a large number of single elements or measure as many shots as possible within the wafer surface (one exposure area). Was being measured. In the case of the former method, as shown in FIG.
One pad (measurement terminal) 101 is required, and even if each of them is arranged as much as possible, the number of pads is limited because the pad size is as large as 1 pad = 100 μm × 100 μm (FIG. 11). In addition, the latter method has the drawback that the number of transistors that can be measured is limited by the size of the shot, and since the transistor characteristics are measured within the entire wafer surface, even statistical variations within the wafer will occur. Could not be considered.

The present invention has been made in order to solve the above-mentioned problems, and transistor characteristics are distributed at one point on the wafer surface, distribution on the entire wafer surface, distribution between wafers, and lot-to-lot. The objective is to statistically analyze each distribution, such as the distribution in.

[0005]

SUMMARY OF THE INVENTION A transistor characteristic evaluation circuit according to the present invention comprises a plurality of transistors to be measured arranged in a matrix and one of the transistors.
Selecting means for selecting one of them, voltage applying means for applying a predetermined voltage to the specific transistor selected by the selecting means, and predetermined voltage for the specific transistor selected by the selecting means.
And a substrate voltage applying means for applying the substrate voltage , and outputs the outputs from the specific transistors individually.

Further, the selecting means selects a decoder for specifying an address of the transistors arranged in the matrix, and a row and a column line connected to the transistors based on an output from the decoder. And a selection transistor for

The selecting means includes a decoder for specifying an address of the transistors arranged in the matrix, and a selecting transistor provided adjacent to each of the plurality of transistors. Based on the output from the decoder, the select transistor is directly operated to select one of the transistors.

[0008]

Further, a ground potential applying means for applying a ground potential to the transistor not selected by the selecting means is further provided.

Further, according to the transistor characteristic evaluation method of the present invention, one of a plurality of transistors arranged in a matrix is selected, and the selected specific transistor is selected.
A predetermined substrate voltage is applied to and the operation of a selected specific transistor is individually measured.

The selection of the plurality of transistors is
This is performed using a decoder and a selection transistor.

Further , each of the plurality of transistors is
Using the selection transistor provided adjacent to this
And select one of the plurality of transistors
Of.

[0013]

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. FIG. 1 is a schematic diagram showing a measuring circuit used in a transistor characteristic evaluation method according to each embodiment of the present invention. Each of the embodiments described below uses a method of selecting a transistor under measurement in a decoder circuit used in a memory device in order to measure each of a large number of transistors. Figure 1
As shown in, the transistors to be measured are formed side by side in a matrix on the semiconductor wafer. In addition, a decoder circuit (X decoder 1, Y decoder 2) is formed around the transistor on the semiconductor wafer. Then, the address of the transistor to be measured is specified using the X decoder 1 and the Y decoder 2, and the transistor is set to 1
Select each one and measure.

Here, the number of transistors that can be arranged is
It is determined by the number of input pulses of the decoder. For example, if 5 pulses can be input in each of the X and Y directions, then 2 ⁵ ×
2 ⁵ = 1024 transistors can be measured. At this time, the number of pads is 5 + 5 = 10 in the X and Y directions. Therefore, when 1024 individual transistors are arranged, four pads are required for one transistor, and 1024 × 4 = 4096 pads are required, which requires a huge area. According to the method of the embodiment, the number of pads can be minimized and the pad area can be greatly reduced.

A pulse source for inputting a pulse is connected to the X decoder 1 and the Y decoder 2. In addition to the pulse source, the power supply voltage (D
C) and GND are provided.

Further, in this measuring circuit, a DC voltage source is separately provided for measuring the transistor. The minimum number of DC voltage sources required is three for the gate, drain and substrate of the transistor. By selecting the transistors to be measured using the X decoder 1 and the Y decoder 2 and controlling the input of the DC voltage source from the outside, the respective transistors arranged in a matrix can be measured.

FIG. 2 is a schematic diagram showing a specific measuring circuit according to the first embodiment. For the sake of simplicity, the following explanatory diagrams are illustrated with a 3 × 3 matrix. In this measurement circuit, measurement transistors 9 (NMOS transistors) to be measured are arranged in a matrix, and DC power supply units 3 and 4 for transistor measurement are arranged on the gate side and the drain side of the measurement transistor 9, respectively. There is. Also,
The source side is connected to the GND terminal 10. Selection transistors 5 and 6 are arranged between the DC power supply units 3 and 4 and the measurement transistor 9, respectively. When a transistor to be measured is selected by the X decoder 1 and the Y decoder 2, one selection transistor 5 or 6 is selected for the line to which the transistor is connected. As a result, the voltage of the DC power supply units 3 and 4 is applied only to the selected measurement transistor 9, and the measurement is performed.

Select transistors 7 and 8 are connected to the Vss terminal 11 side opposite to the DC power supply units 3 and 4.
The selection transistors 7 and 8 are NMOS transistors connected to the inverters 7a and 8a. These selection transistors 7 and 8 are connected to the X decoder 1 and the Y decoder 2 similarly to the selection transistors 5 and 6. When a line is not selected, that is, when the output of the decoder for that line is low, the selection transistors 7 and 8 include the inverters 7a and 8a. Turns on and the line is connected to the Vss terminal 11 side. vice versa,
When a certain line is selected, that is, when the output of the decoder for that line is High, the selection transistors 7 and 8 are turned off by the inverters 7a and 8a and are disconnected from the Vss terminal 11. As a result, the voltage of the DC power supply units 3 and 4 is applied only to the bit lines and word lines selected by the X decoder 1 and the Y decoder 2, and the unselected bit lines are forcibly short-circuited to the Vss terminal 11. You can

When one transistor to be measured is selected, from the bit line on the drain side of that transistor
The voltage of the DC power supply unit 4 is applied, and a current flows from the drain to the source. In order to efficiently apply the voltage of the DC power supply unit 4 to the transistor for measuring, the ON resistance of the selection transistor 6 needs to be as small as possible. For example, if the gate width of the selection transistor 6 is 1000μ
By designing m and the gate length to be about 0.1 μm, the on-resistance of the selection transistor 6 can be reduced to 1Ω or less. On the other hand, the gate width of the transistor 9 to be measured is 10μ.
When the gate length is m and the gate length is 0.1 μm, the on-resistance becomes about 100Ω, and the output voltage of the DC power supply unit 2 is almost applied to the measuring transistor 9. Since the size of the measurement transistor 9 can be freely changed, it is necessary to design the selection transistor 6 according to the ON resistance of the measurement transistor 9. The selection transistors 5, 7, 8 are not particularly limited.

The wiring between the DC power supply unit 4 and the GND terminal 10 also needs to have a reduced wiring resistance for the same reason, and may be designed with a wiring width as large as possible and a wiring length as short as possible.

In the example of FIG. 2, the selection transistors 7 and 8 are composed of NMOS transistors and inverters 7a and 8a, but as shown in FIG.
It may be replaced by using a PMOS transistor without using a. Here, FIG. 3A shows a case in which the selection transistors 7 and 8 are configured by using inverters 7a and 8a, and FIG. 3B shows an example in which the selection transistors 7 and 8 are configured by PMOS transistors. ing.

In FIG. 2, an NMOS transistor is shown as the measuring transistor 9, but even if all the measuring transistors 9 are replaced by PMOS transistors,
Similar measurements can be made. When the PMOS transistor is measured, the voltage of the DC power supply units 3 and 4 may be applied accordingly.

FIG. 4 is a schematic diagram showing a system for measuring a bipolar transistor with a circuit configuration similar to that of FIG. In this case, with the same circuit configuration as in FIG. 2, only the region of the measuring transistor 9 may be replaced with a bipolar transistor. In the example of FIG. 4, as the measurement transistor 9,
Power supply unit 3 with NPN bipolar transistor
The base electrode is connected to the side, the collector electrode is connected to the DC power supply unit 4 side, and the emitter electrode is connected to the GND terminal 10. As a result, the bipolar transistor can be evaluated as in the case of the MOS transistor of FIG. Since the power supply units 3 and 4 can be set to any voltage, it is possible to measure PNP transistors.

As described above, according to the first embodiment, the area is not increased due to the increase in the number of pads,
It is possible to evaluate a large number of transistors. With this system, it is possible to measure at a level of 1000 or more transistors, which until now could be evaluated only at a single level, and statistical analysis can be performed for the first time. Moreover, the measuring machine only needs to use the pulse source and the DC power supply units 3 and 4, and the semiconductor parameter analyzer and parametric tester used in the TEG or PCM measurement can be sufficiently used.

Embodiment 2. Next, a second embodiment of the invention will be described with reference to FIG. Embodiment 2 is
The transistor evaluation circuit is configured so that even the substrate bias effect can be measured. As shown in FIG. 5, DC power supply units 3 and 4 for transistor measurement are arranged on the gate side and the drain side of the transistor to be measured,
Select transistors 5, 6, 7, and 8 having the same functions as those in the first embodiment shown in FIG. 2 are arranged.

The DC power supply unit 12 is newly added so that the substrate voltage of the measuring transistor 9 can be freely changed.
GND unit 13 and selection transistors 14 and 15,
17 and an inverter 16 are provided. Then, the selection transistors 14 and 15 are connected so as to be synchronized with the X decoder 1, and the column (Colu
mn), a substrate bias is applied from the DC power supply unit 12.

Further, the GND unit 1 is connected to the unselected columns via the selection transistor 15 and the inverter 16 so that the substrate bias is not applied.
3 are connected. When the column is selected by the X decoder 1, the selection transistor 14 is turned on, and further, the selection transistor 17 is turned on for the row selected by the Y decoder 2, so that the output voltage of the DC power supply 12 is not output for the first time. Will be applied. When the bit is not selected, the selection transistor 15 and the inverter 16 bring the substrate potential to GND.

The operation of the transistor is the same as in the case of FIG. 2, and the substrate bias can be controlled by the DC power supply unit 12. Also, the combination of the selection transistors 7, 8 and 15, 16 can be replaced by PMOS transistors as shown in FIG.

Although FIG. 5 shows the case where an NMOS transistor is assumed as the measuring transistor 9, even when all the measuring transistors 9 are replaced by PMOS transistors,
Similar measurements can be made. When measuring the PMOS transistor, the DC power supply unit 3, 4, 1 according to it
A voltage of 2 may be applied.

As in the case of FIG. 4, the measuring transistor 9 of FIG. 5 may be replaced with a bipolar transistor. Further, the GND unit 13 for substrate bias need not be separately provided if it can be shared with the Vss terminal 11 in layout.

FIG. 6 is a schematic diagram showing another example of the evaluation circuit including the substrate bias effect. In FIG. 6, the application of the substrate bias is provided to each of the measurement transistors 9.
The AND circuit 18 and the NAND circuit 19 are used for selection. The selection transistors 20 and 21 are both NMOS transistors, and are connected to the AND circuit 18 and the NAND circuit 19, respectively. When the outputs of the X decoder 1 and the Y decoder 2 are both High, and the column and row of the measuring transistor 9 are selected, the output of the AND circuit 18 is H.
Then, the output of the DC power source 12 for substrate bias is applied to the measurement transistor 9.

At this time, since the output of the NAND circuit 19 becomes Low, the substrate potential is separated from the GND unit 13.
On the contrary, of the outputs of X decoder 1 and Y decoder 2, both are Hi
When it is not gh, the output of the AND circuit 18 becomes Low, the output from the DC power supply unit 12 is disconnected, and the output of the NAND circuit 19 becomes Hi.
Therefore, the substrate potential of the measurement transistor 9 becomes the ground potential from the GND unit 13. As described above, the transistor can be measured by applying the required voltage only to the transistor to be measured through the X decoder 1 and the Y decoder 2.

Also in the circuit of FIG. 6, measurement can be performed even if the measuring transistor 9 is a PMOS transistor or a bipolar transistor.

Embodiment 3. Next, a third embodiment of the invention will be described with reference to FIG. FIG. 7 shows another form of the measurement circuit system having the same function as in FIG. An NMOS selection transistor 22 is provided in each gate portion of the measurement transistor 9, and is connected to the gate DC power supply unit 3. In this structure, when the selection transistor 22 is turned on, the voltage of the gate DC power supply unit 3 is applied to the gate of the measurement transistor 9. The selection of the selection transistor 22 is performed by the AND circuit 24 provided in each cell 23. The AND circuit 24 is connected to the outputs of the X decoder 1 and the Y decoder 2, and the output of the AND circuit 24 becomes High only when the outputs of both the X decoder 1 and the Y decoder 2 are High. Therefore, for the cell 23 in which both the outputs of the X decoder 1 and the Y decoder 2 are High, the AN
The output of the D circuit 24 becomes High and the selection transistor 22 is turned on. In other words, cell 2 selected by the X and Y decoder
Only the measuring transistor 9 in 3 can be measured.

The merit of the measuring circuit of the third embodiment is that the DC power supply unit 4 for drain is not provided with a selection transistor. To measure the measuring transistor 9,
It is necessary to pass a current from the drain DC power supply unit 4 to the GND 10. However, unlike the case shown in FIG. 2, the system of FIG. 7 has no selection transistor in the drain current path. Therefore, there is no voltage drop from the drain DC power supply unit 4 due to the on-resistance of the selection transistor.

FIG. 8 is a schematic diagram showing another form of the measuring circuit of FIG. 7, in which the measuring transistor 9 of the unselected cell is used.
The gate of the can be forced to GND. In addition to the circuit configuration of FIG. 7, an NMOS selection transistor 25, a NAND circuit 26, and a GND terminal 27 are provided.
The method for selecting and measuring the selection transistor 22 is the same as in the case of FIG. Select transistor 2 provided separately
Reference numeral 5 is connected to the gate of the measuring transistor 9 and the GND terminal 27 and serves as a switch. The output of the NAND circuit 26 is connected to the gate of the selection transistor 25, and the NAND circuit 2
When the output of 6 is High, the selection transistor 25 is turned on and the gate of the measurement transistor 9 is forced to the GND terminal 2
Connected to 7.

The outputs of the X decoder 1 and the Y decoder 2 are connected to the input of the NAND circuit 26. The output of the NAND circuit 26 becomes Low and the selection transistor 25 is turned off only when both the outputs of the X decoder 1 and the Y decoder 2 are High.
Therefore, the gate of the measuring transistor 9 is disconnected from the GND terminal 27. Other output, that is, unit cell 2
When 3 is not selected, the output of the NAND circuit 26 is Hi
gh, and the gate of the measuring transistor 9 is the GND terminal 2
It is connected to 7. In the measurement circuit of FIG. 8, the gate potential of the measurement transistor 9 of the unselected unit cell 23 is forcibly set to GND, so that the generation of noise and the like can be suppressed and more reliable measurement can be performed.

In addition, in the measurement circuit system of FIGS.
A function of applying a substrate bias of 6 may be added.

In the above description, as shown in FIG. 9A, the output of the AND circuit is connected to the NMOS transistor,
Although the switch is used, the switch can be similarly used even when the NAND circuit and the PMOS transistor are replaced as shown in FIG. 9B. Also, as shown in FIG.
The output of the circuit was connected to the NMOS transistor and switched, but it is the same even if it is replaced by a system of an AND circuit and a PMOS transistor as shown in FIG.

[0041]

Since the present invention is constructed as described above, it has the following effects.

One of a plurality of transistors to be measured
Since one of them is selected and a predetermined voltage is applied to each of the selected transistors for individual measurement, a large number of transistors can be evaluated without causing an increase in area due to an increase in the number of pads. This enables statistical analysis of a large number of transistors.

Since the decoder for specifying the address of the transistor to be measured and the selection transistor for selecting the row and column lines based on the output from the decoder are provided, the transistor to be measured can be surely specified. it can.

The selection transistor provided adjacent to each of the transistors to be measured is directly operated to select one of the plurality of transistors, so that the line is turned on as compared with the case where the line is selected by the selection transistor. The resistance can be reduced.

Further, by grounding the unselected transistors, it is possible to suppress the generation of noise and the like and to perform stable measurement.

By making the transistor to be measured a field effect transistor, it becomes possible to statistically analyze the characteristics of a large number of field effect transistors. Further, by making the transistor to be measured a bipolar transistor, it becomes possible to statistically analyze the characteristics of a large number of bipolar transistors.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a basic configuration of a transistor measuring circuit used in each embodiment of the present invention.

FIG. 2 is a schematic diagram showing a transistor measuring circuit according to the first embodiment of the present invention.

FIG. 3 is a schematic diagram showing a configuration of a selection transistor.

FIG. 4 is a schematic diagram showing an example in which a measurement transistor is a bipolar transistor.

FIG. 5 is a schematic diagram showing a transistor measuring circuit according to a second embodiment of the present invention.

FIG. 6 is a schematic diagram showing another example of the transistor measuring circuit according to the second embodiment of the present invention.

FIG. 7 is a schematic diagram showing a transistor measuring circuit according to a third embodiment of the present invention.

FIG. 8 is a schematic diagram showing another example of the transistor measuring circuit according to the third embodiment of the present invention.

FIG. 9 is a schematic diagram showing a configuration of an AND circuit.

FIG. 10 is a schematic diagram showing a configuration of a NAND circuit.

FIG. 11 is a schematic diagram showing a conventional transistor characteristic evaluation method.

[Explanation of symbols]

1 X decoder, 2 Y decoder, 3,4,12 DC
Power supply unit, 5, 6, 7, 8, 14, 15, 17,
20, 21, 22, 25 selection transistor, 9 measurement transistor, 10, 27 GND terminal, 11 Vss terminal, 13 GND unit, 16, 7a, 8a inverter, 18, 24 AND circuit, 19, 26 NAND circuit, 23 cells.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G01R 31/26 G01R 31/28-31/3193 H01L 21/66

Claims (7)

(57) [Claims] 1. A plurality of transistors to be measured, which are arranged in a matrix, a selection unit that selects one of the transistors, and a voltage that applies a predetermined voltage to the specific transistor selected by the selection unit. and applying means, predetermined group in particular transistor selected in said selecting means
And a substrate voltage applying means for applying a plate voltage , wherein the output from the specific transistor is individually read out. 2. The selecting means selects a decoder for specifying an address of the transistors arranged in the matrix, and a row and a column line connected to the transistor based on an output from the decoder. The transistor characteristic evaluation circuit according to claim 1, further comprising: 3. The selection means includes a decoder for specifying an address of the transistors arranged in the matrix, and a selection transistor provided adjacent to each of the plurality of transistors, 2. The transistor characteristic evaluation circuit according to claim 1, wherein the selection transistor is directly operated based on an output from the decoder to select one of the transistors. 4. The transaction not selected by the selecting means
Further equipped with a ground potential applying means for applying a ground potential to the transistor
4. The method according to claim 1, wherein
Transistor characteristics evaluation circuit. 5. A plurality of transformers arranged in a matrix.
Select one of the lists and select the specific transition
The specified substrate voltage is applied to the
Transistor characterized by individually reading the output of the transistor
Method for evaluating the characteristics of the transistor. 6. Decoupling the selection of the plurality of transistors
Characterized by using a header and a selection transistor
The method for evaluating characteristics of a transistor according to claim 5, wherein 7. Each of the plurality of transistors is adjacent to each other.
Using the selection transistor provided in contact,
Characterized by selecting one of a plurality of transistors
The method for evaluating characteristics of a transistor according to claim 6.