JP3461237B2 - Computer system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system having a function of changing the frequency of an operating clock of the system according to a predetermined condition.

[0002]

2. Description of the Related Art Conventionally, a notebook type or a palm (pal)
m) A top-type personal computer generally uses a rechargeable battery as a power source for operating the system. In such a system, various power management functions have been developed in order to save power consumption of a battery having a limited power capacity.

As one of the power management functions, the frequency of the system operation clock is lowered to
As a result, there is a method of reducing the power consumption of the battery.
In this method, a system controller having a function of controlling a clock in the system (a control unit having an interface function between each element in the system) operates from a clock oscillator according to a set value set by a user by a key input of a keyboard. This is done by dividing the frequency of the clock. As a result, the CPU, the display controller, and the like, which are supplied with the clock from the system controller, operate with the low-frequency clock, and as a whole, the power consumption of the battery is reduced.

[0004]

As a power management function adopted in a conventional personal computer, there is a method of lowering the frequency of an operation clock of a CPU, a display controller or the like. However, in the conventional method, it is premised that the running application program is terminated once and the clock frequency is set by key input from the outside, and once set, it is set until it is released. The system will operate depending on the clock frequency.

Therefore, when operating an application program that requires high capability (high clock frequency), the low clock frequency remains set,
A situation occurs in which smooth operation cannot be performed. On the contrary, when the high clock frequency is set and the application program is not operating, useless power is consumed.

An object of the present invention is to enable smooth, reliable and efficient switching of clock frequencies to reduce power consumption even when various application programs and the like are operating, depending on system conditions , and to reduce communication power consumption . Maintains compatibility by ensuring reliable operation of application programs
To provide a computer system capable of doing so.

[0007]

SUMMARY OF THE INVENTION An aspect of the present invention is a clock for generating and outputting a clock necessary for system operation.
An oscillator , a CPU that operates based on the clock and executes an application program, and
When receiving the instruction to change the clock, the CP
Issue an instruction to U to change the clock.
The CPU to set the clock variable enable state.
Temporarily stop the operation of the application program
After switching the clock, after a predetermined period of time
To release the clock variable permission state,
Clock control to activate the application program
And an application program executed by the CPU
Monitor whether the ram is a communication program and
If the program is running, the CPU will
Clock hold signal to the clock controller
And a means for prohibiting the clock switching .

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining a clock control method related to this embodiment, FIG. 2 is a block diagram showing a main part of a personal computer related to this embodiment, and FIG. 3 is a block diagram of this embodiment. It is a flow chart for explaining operation. (System Configuration) As shown in FIG. 1, the system of the present embodiment has a clock controller 1 that generates a clock necessary for the operation of the system and supplies the clock to each element. It has a function of changing the frequency of the clock accordingly. The clock controller 1 divides a basic clock CP (for example, a frequency of 75 MHz) supplied from the clock oscillator 2 to generate clocks CF, CH, CM, CL having different frequencies.
To generate. Further, the clock controller 1 generates clocks CF, CH, CM, CL having different frequencies according to a specific condition that is a system condition (in other words, the clock frequency is changed).

Specifically, the clock controller is a C
PU load detector 3, remaining battery charge detector 4, CPU
When the CPU 12 receives the SMI (system management interrupt) signal from the heat generation detection unit 5 of
On the contrary, if there is an instruction from the PU 12 to change the clock, C
A signal S indicating that the clock is variable with respect to the PU 12.
Outputs I, sets the clock controller enabled state (stop ground state) the CPU 12. When such a setting is made, the CPU 12 stops the operation of the application program.

After the clock is switched by the clock controller 1, when the CPU 12 becomes stable with the frequency-switched clock, the clock controller 1 releases the stop grant state and enters the normal application program operating state. By repeating this control frequently, even when the system is operating, that is, the application program is operating, the clock frequency can be switched smoothly, reliably and efficiently to reduce the power consumption.

In this embodiment, the clock CF is a clock of the highest frequency (75 MHz) corresponding to the full power mode, the clock CH is a clock of a high frequency (about 48 MHz) corresponding to the high power mode, and the clock CM is The intermediate frequency (approximately 37 MHz) clock corresponding to the medium power mode is used, and the clock CL is the lowest frequency (24 MHz) corresponding to the low power mode.
The clock is assumed to be about MHz).

The above-mentioned specific conditions mean the load state during operation of the CPU, the remaining capacity of the battery which is the power source for operating the system, and the heat generation temperature of the CPU (surface temperature of the CPU). Therefore, the system of the present embodiment has a load detection unit 3 of the CPU, a remaining battery capacity detection unit 4, and a heat generation detection unit 5 of the CPU as specific means for judging each condition.

The system configuration when the present embodiment is applied to a personal computer will be described below with reference to FIG. The clock controller 1 is provided inside the system controller 10. The system controller 10 is a control unit having functions such as the system interface 11. The system controller 10
Clocks (CF, CH, C) necessary for operation of the CPU 12 and the display controller 14 by the clock controller 1
M, CL) is supplied or stopped.

The system controller 10 communicates with a power supply controller (power supply microcomputer) 15 for controlling the power supply from a rechargeable battery 16 which is a power supply for operating the computer, and the power supply controller 15 notifies the remaining capacity of the battery 16. . Further, the system controller 10
A temperature detection value is input from a temperature sensor 13 that detects the surface temperature of the CPU 12, and it is monitored whether the surface temperature of the CPU 12 exceeds an allowable temperature value. (Clock Control Processing) The clock control processing, which is the operation of this embodiment, will be described below with reference to the flowchart of FIG.

First, when the power source is turned on, the power source controller 15 controls the power of the battery 16 to
The operating power of the system is supplied (step S1). In the system controller 10, the clock controller 1
Is the highest frequency (75 MH) corresponding to the full power mode based on the basic clock CP from the clock oscillator 2.
The clock CF of z) is supplied to the CPU 12 (step S2). In the present embodiment, only the clock control processing supplied to the CPU 12 will be described.

The system controller 10 determines the load status of the CPU 12, which is the status of the system, the remaining capacity of the battery, C
The heat generation temperature of the PU 12 is monitored, and the clock controller 1 is instructed to change the clock frequency according to the situation.

In the present embodiment, first, the load state of the CPU 12 is detected, and the variable of the clock frequency is instructed according to the load state (step S3). The load state of the CPU 12 is an operating state when the CPU 12 is executing an application program, and corresponds to the above-described full power mode, high power mode, medium power mode, and low power mode depending on the stage. CPU
The load state of 12 is determined by the driver software attached to the OS, for example, from the number of idle states of the CPU 12 in a certain fixed time. That is, the system controller 10 sets the busy state flag every time the CPU 12 accesses the I / O or the memory. Therefore, the system controller 10 recognizes the number of idle states based on the number of times the flag is set, and the load on the CPU 12 is reduced. Detect the condition.

The system controller 10 includes a CPU 12
When the load state of is other than the full power mode, the clock controller 1 is instructed to change the clock frequency according to each mode (NO in step S4, S5).
For example, when the load state of the CPU 12 corresponds to the high power mode, the clock controller 1 changes the clock CH to a relatively high frequency (about 48 MHz). Similarly, in medium power mode,
Variable to the clock CM with an intermediate frequency (about 37 MHz), and in the low power mode, the lowest frequency (24
It is variable to a clock CL of about MHz).

Further, the system controller 10 monitors the remaining capacity of the battery 16 and instructs the clock controller 1 to change the clock frequency according to the remaining capacity (step S6). Specifically, the power supply controller 15
Indicates that the power capacity of the battery 16 is, for example, 100% to 75%.
An SMI (system management interrupt) is generated and notified to the system controller 10 every time the battery voltage is reduced from the (fully charged state) to some extent.

The system controller 10 is a battery 1
When the remaining capacity of 6 is other than 100% to 75%, the clock controller 1 is instructed to change the clock frequency according to the predetermined remaining capacity (NO in step S7, S
8). For example, the remaining capacity of the battery 16 is 74% to 50%
When it decreases to a certain degree, the clock controller 1 changes the clock frequency of the clock CH corresponding to the high power mode. Similarly, when it is reduced to about 49% to 25%, it is changed to the clock CM corresponding to the medium power mode, and when it is reduced to 24% or less, it is lowered to the lowest frequency clock CL corresponding to the low power mode. Let

The system controller 10 also monitors the heat generation temperature of the operating CPU 12 and instructs the clock controller 1 to reduce the clock frequency when the heat generation temperature exceeds the allowable temperature value (step S9). ). Specifically, the temperature sensor 13 installed on the surface of the CPU 12 constantly detects the surface temperature of the CPU 12, and the power supply controller 15 constantly monitors this detection signal. Then, when the heat generation temperature of the CPU 12 becomes a predetermined temperature below (1) to (3), the power supply controller 15 causes the interrupt signal SMI (system mana).
generation interface (CPU)
12 is transmitted. The CPU 12 instructs the system controller 10 to cause the clock controller 1 to execute clock control according to the instruction (steps S10 and S1).
1).

(1) When the temperature TA for reducing the frequency of the CPU clock is exceeded, an SMI signal is issued and the stop clock function is used to reduce the speed to reduce heat generation. (2) Temperature T to reset speed down
If the temperature falls below B, issue an SMI signal to stop the speed down and return to normal speed. (3) If the temperature continues to rise and exceeds the temperature TC even after performing the control of (1), the SMI signal is issued and the power is forcibly turned off. The relationship between each temperature is "TB
<TA <TC ”.

The allowable temperature value differs depending on the system and is determined in relation to the load state of the CPU 12, that is, the clock frequency. As described above, it takes some time (0.5 to 0.8 ms) to dynamically switch the CPU clock during system operation.
Therefore, compatibility problems may occur when the communication application program is running. Therefore, in the present invention, the CPU clock can be switched during the operation of the application program, but the clock switching is not permitted only during the communication processing. In order to realize the stop of the clock switching, the OS of the system monitors whether or not the currently running application program is the communication program. When the communication program is running, the CPU 12 outputs a clock hold signal to the clock controller 1,
Prevent clock switching.

As described above, according to this embodiment, the frequency of the clock necessary for the operation of the CPU 12 and the like is variably set according to the status of the system, so that the system can always be maintained in an appropriate state. . That is, the CPU 12
If the full power mode capability is required for the operation of the application program according to the load condition of
It is possible to supply the clock CF having the highest frequency corresponding thereto and, conversely, the clock CL having the lowest frequency when not operating. Therefore, the application program can be smoothly executed, and the power consumption of the battery 16 can be saved by lowering the clock frequency when the application program is not operating.

Further, by variably setting the clock frequency according to the remaining capacity of the battery 16, it is possible to save the power consumption of the battery 16 as a result. In particular, when the capacity is reduced to the lower limit of the allowable range (for example, 24% or less), the power consumption of the battery 16 is reduced as much as possible by reducing the clock frequency (CL) to the lowest value, for example, the resume process. It can be surely executed. This reduces the battery 16 to below the lower limit of the allowable range, causing the system to malfunction.
It is possible to prevent a situation in which data that needs to be saved is deleted.

Further, the heat generation temperature of the CPU 12 is monitored, and when the heat generation temperature exceeds the allowable temperature value, the clock frequency is forcibly lowered to thereby cause the CPU 12 to operate.
The exothermic temperature of can be lowered. Therefore, the CPU
It is possible to prevent the CPU 12 from being destroyed or going out of control due to an abnormal rise in the heat generation temperature of the CPU 12.

[0027]

According to the present invention as described in detail above, shea
Depending on the system situation, various application programs
Smooth, reliable and efficient even when the ram is operating
The power consumption can be reduced by switching the clock frequency.
To ensure reliable operation of communication application programs
A computer system that can be implemented to maintain compatibility.
A stem can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a clock control method related to the present embodiment in the present invention.

FIG. 2 is a block diagram showing a main part of a personal computer related to the present embodiment.

FIG. 3 is a flowchart for explaining the operation of this embodiment.

[Explanation of symbols]

1 ... Clock controller 2 ... Clock oscillator 3 ... CPU load detector 4 ... Remaining battery capacity detector 5: CPU heat generation detector 10 ... System controller 11 ... System interface 12 ... CPU 13 ... Temperature sensor 14 ... Display controller 15 ... Power supply controller 16 ... Rechargeable battery

Continuation of the front page (56) Reference JP-A-6-332562 (JP, A) JP-A-5-333976 (JP, A) JP-A-5-94228 (JP, A) JP-A-2-83720 (JP , A) JP-A-6-175946 (JP, A) JP-A-1-134616 (JP, A) JP-A-6-51863 (JP, A) JP-A-3-100710 (JP, A) 1-61730 (JP, U) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 1/06 G06F 1/08

Claims (3)

(57) [Claims] 1. A clock oscillator that generates and outputs a clock required for system operation, a CPU that operates based on the clock and executes an application program, and an instruction to change the clock from the CPU.
First, changing the clock for the CPU
Is output and the CPU is allowed to change its clock.
Operation of the application program
Temporarily stop, and after switching the clock,
The clock variable enable state is released after a fixed period of time.
The application program to the operating state.
The clock controller communicates with the application program executed by the CPU.
Monitoring whether the communication program is
If the CPU is running, the CPU
The clock hold signal is output to the
A computer system comprising means for inhibiting clock switching . 2. The clock variable enable state is stopped.
The ground state is according to claim 1,
Computer system. 3. The CPU has at least a load detection unit,
Either the battery remaining capacity detection unit or the heat generation detection unit of the CPU
Receives a system management interrupt signal from one
The clock controller follows the interrupt signal.
Received an instruction from the CPU to change the clock.
When the clock is variable with respect to the CPU
Is output to output a signal indicating
2. The controller according to claim 1, wherein the controller is set to a state.
Computer system.