JP3460639B2 - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as SIT (Static Induction Transistor) using silicon carbide.

[0002]

2. Description of the Related Art As a conventional SIT, Japanese Patent Laid-Open No. 10-29 is known.
The one shown in Japanese Patent No. 4471 has been proposed. A sectional structure of the SIT shown in this publication is shown in FIG.

As shown in FIG. 8, an n-type drain region 10 is formed.
1, an n-type drift region 102 is formed on top of the No. 1 region. Further, a low-resistance n-type source region 103 having a high impurity concentration is formed in the surface layer portion of the n-type drift region 102, and a low-resistance p-type having a high impurity concentration is formed so as to be in contact with both sides of the n-type source region 103. The gate region 104 is formed. The p-type gate region 104 is formed so as to extend below the n-type source region 103. Then, the gate electrode 105 and the source electrode 106 are formed so as to be in contact with the surfaces of the p-type gate region 104 and the n-type source region 103, respectively, and the drain electrode 107 is formed so as to be in contact with the back surface of the n-type drain region 101. It is composed.

[0004]

In the conventional SIT described above, two-step ion implantation is performed to form the p-type gate region 104, and the second ion implantation is performed with higher energy than the first ion implantation. By doing so, the energy loss due to the nuclear collision between the implanted ions and the atoms in the n-type drift region 102 is increased, and the lateral scattering distance of the implanted ions is increased, so that the p-type gate region 104 is made into the n-type source. It is designed to enter below the region 103.

In such a case, it is necessary to carry out the second ion implantation for forming the p-type gate region 104 so that the ions are implanted deeply while considering the energy loss due to the nuclear collision. . For this reason, ion implantation must be performed with extremely high energy. In particular,
When the semiconductor device is made of silicon carbide, it is necessary to perform ion implantation with extremely high energy as compared with the case where it is made of silicon, and an ion implantation device capable of generating such high energy is required. It

Further, in the above-mentioned conventional SIT, lateral scattering due to nuclear collision is used, and this method has a limit in narrowing the interval between the p-type gate regions 104. Therefore,
When the gate applied voltage is zero, the depletion layers extending from both sides to the n-type drift region 102 sandwiched between the p-type gate regions 104 and the p-type gate regions 104 are not connected to each other, resulting in a normally open characteristic. Such a normally open type SIT has a problem that a high voltage is required to turn it off, and it cannot be turned off even when the gate applied voltage becomes zero, which causes a fail-safe problem. .

Further, in the conventional SIT described above, since the n-type source region 103 and the p-type gate region 104 are formed in contact with each other, a leak current occurs between the PN junctions. FIG. 9 shows reverse voltage-leakage current characteristics in the case where the n-type source region 103 and the p-type gate region 104 are configured to be in contact with each other. In this figure, the above relationship is investigated in the case of using phosphorus as the impurity for forming the n-type source region and in the case of using nitrogen.
As shown in this figure, when a reverse bias is applied, a leak current occurs, and there is also a problem that the breakdown voltage at the time of reverse bias cannot be obtained.

The present invention has been made in view of the above points, and it is a first object of the present invention to make it possible to form a structure in which a gate region extends below a source region without performing high-energy ion implantation. .

A second object of the present invention is to enable a semiconductor device having a structure in which the gate region extends below the source region to have normally-off characteristics.

A third object is to obtain a withstand voltage during reverse bias.

[0011]

In order to achieve the above object, in the invention described in claims 1 to 3 , the gate region (4) is separated from the source region (3) and the surface of the drift region is formed. To the first region (4A) formed to a position where the junction depth is deeper than the source region, and the junction depth is formed deeper than the first region, and is configured to penetrate below the source region. The second region (4B) is provided, and the second region has a lower impurity concentration than the first region.

[0012] Thus, since the second region is formed so as to enter to the lower of the source region, by narrowing the interval, even when the voltage applied to the Gate electrode is zero, It is possible to pinch off the drift region between the second regions . With such a configuration
By doing so , a normally-off type device can be obtained. Therefore, it is possible to make the device advantageous in fail-safe. Further, since the impurity concentration of the second region is low, the reverse breakdown voltage of the PN junction with the drain region can be increased. That is, the gate-drain breakdown voltage can be increased.

Further, since the gate region is separated from the source region, the P formed by these is formed.
It is possible to prevent the generation of leak current due to the N-junction. Therefore, it is possible to obtain the withstand voltage during reverse bias. A silicon carbide semiconductor device.

According to a fourth aspect of the present invention, in the surface layer portion of the drift region (2), ions that are inactive at a predetermined depth deeper than the source region (3) are formed in a portion where the gate region (4) is to be formed. The step of ion-implanting the species, and the step of forming a region (4A) in the surface layer portion of the drift region into which the inactive ion species are implanted and a region (4B) deeper than the depth in which the inactive ion species are implanted. The second conductivity type impurity is activated by the step of ion-implanting the second conductivity type impurity and the heat treatment to suppress the lateral diffusion of the second conductivity type impurity up to the depth at which the inert ion species is implanted. A step of forming a gate region by laterally diffusing the impurity of the second conductivity type so as to enter below the source region in a region deeper than the depth into which the inert ion species are implanted; In the surface layer portion, it is characterized in that it includes the steps of forming a source region, a so as to be separated from the gate region.

Inert ionic species (eg C (carbon))
Is implanted, an inactive ion species enters the vacancy of the carbon site to repair crystal defects in the implanted region, and the diffusion of impurities is suppressed. Therefore, by implanting the inactive ion species into a region deeper than the source region in the gate region formation planned portion, lateral diffusion of the second conductivity type impurity is suppressed in this region, and this region is suppressed. Lateral diffusion of the second conductivity type impurity can be promoted in a deeper region. Then, the impurity concentration becomes low due to thermal diffusion in a region deeper than the region into which the inactive ion species is implanted. Thereby, the silicon carbide semiconductor device according to claim 1 is formed.

According to a fifth aspect of the present invention, in the surface layer portion of the drift region, between the planned formation portions of the gate regions arranged on both sides of the source region, the gate region is inactive to a predetermined depth deeper than the source region. The feature is that ion species are ion-implanted.

When the inactive ion species are ion-implanted between the portions where the respective gate regions are to be formed in this manner, thermal diffusion into the regions is suppressed, so that the same as in the sixth aspect of the invention. The silicon carbide semiconductor device described in 1 is formed.

In a sixth aspect of the invention, the lateral diffusion direction of the second conductivity type impurity is <112-0>. This <112-0> direction is the second one more than the other directions.
Since the conductivity type impurities are easily diffused, the distance between the second regions can be easily narrowed, and the drift region can be reliably pinched off.

According to the invention described in claim 7 , B is used as the second conductivity type impurity, and C is used as the inert ion species.

It is known that B has a large diffusion amount among the p-type dopants, so that the lateral diffusion can be made large. Further, when C is used as the inert ion species, the crystal defects in the vacancies at the carbon sites are repaired by C, which is the same element, so that it is easier to repair than other elements, and the injection amount of the element used for repair can be reduced.

The invention according to claim 8 is characterized in that Al is used as a p-type impurity even in a region deeper than the source region, and B is used as a p-type impurity in a region deeper than this region. .

In this case, since the thermal diffusion amount of Al is small and the thermal diffusion amount of B is large, the gate region is formed below the source region by lateral diffusion of B in a region deeper than the source region. To be done.

The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 shows a sectional structure of an SIT in this embodiment. This cross sectional structure is 1
This is an illustration of channels, and in reality, this SIT
Is used as a multi-channel provided with a plurality of.

As shown in FIG. 1, n-type drain region 1 formed of an n-type silicon carbide semiconductor substrate having a relatively high impurity concentration is provided. The main surface of the n-type drain region 1 is provided with a high-resistance n-type drift region 2 formed by epitaxial growth or the like and having a relatively low impurity concentration. In the surface layer portion of the n-type drift region 1,
n having low impurity concentration and higher impurity concentration than the n-type drift region 1
The mold source region 3 is formed.

On both sides of the n-type source region 3,
A p-type gate region 4 is formed so as to be separated from the n-type source region 3. The p-type gate region 4 extends almost perpendicularly to the substrate surface from the surface of the n-type drift region 1 to a position deeper than the n-type source region 3, and then enters below the n-type source region 3 by lateral diffusion. It has a shape. Of this p-type gate region 4, a region 4A extending from the surface of the n-type drift region 1 substantially perpendicularly to the substrate surface is
The region 4B formed of a low-resistance p-type semiconductor having a relatively high impurity concentration and located below the region 4A (including the region below the n-type source region 3) has a higher impurity content than the region 4A. It is composed of a high-resistance p-type semiconductor having a low concentration. The region 4A is in a state of being doped with C ⁺ as an inert ion species.

Further, a gate electrode 6 and a source electrode 7 are formed so as to contact the surfaces of the p-type gate region 4 and the n-type source region 3, respectively, and the surface of the n-type drain region 1 (n
The drain electrode 8 is formed so as to be in contact with the back surface of the silicon carbide semiconductor substrate of the type to form the SIT. A passivation film 9 is arranged between the gate electrode 6 and the source electrode 7 to insulate them.

The SIT thus constructed changes the amount of extension of the depletion layer extending from the region 4B of the p-type source region 4 toward the n-type drift region 3 by controlling the voltage applied to the gate electrode 6. Then, the amount of drain current flowing between the source and the drain is controlled by expanding and contracting the channel width.

Further, when the voltage is not applied to the gate electrode 6, the adjacent p-type source regions 4 are formed.
The depletion layer extending from the region 4B to the n-type source region 3 pinches off between the adjacent regions 4B. As a result, the SIT is of normally-off type. Therefore, the adjacent region 4B
The shortest distance d between them is set to a length such that the distance between them is pinched off, that is, equal to or less than the extension amount of the depletion layer extending from both regions 4B. In the present embodiment, since the region 4B is made of a high-resistance p-type semiconductor having a relatively low impurity concentration, the region 4B is formed.
The amount of expansion of the depletion layer extending from to the n-type drift region 1 can be increased, and it is possible to easily pinch off between the both regions 4B.

Further, since the n-type source region 3 and the p-type gate region 4 are not in contact with each other, it is possible to prevent the leak current of the PN junction portion formed by these contacting, and at the time of reverse bias. Withstand voltage can be obtained.

Next, the manufacturing process of the SIT shown in FIG. 1 will be described with reference to FIGS.

[Step shown in FIG. 2A] First, (000
1) 3 with a thickness of 400 μm cut out from the silicon surface
An n-type semiconductor substrate of C, 4H, 6H or 15R-SiC having a relatively high impurity concentration and a low resistance is prepared. At this time, as will be described later, in 4H and 6H, it is desirable that the direction in which the diffusion of B is particularly desired is <112-0>. That is, in this case, it is preferable that the direction crossing the drawing is <112-0>. This n
The type semiconductor substrate constitutes the n-type drain region 1. Then, on the main surface of this n-type drain region 1, a high-resistance n-type drift region 2 made of silicon carbide having an impurity concentration lower than that of n-type drain region 1 is formed by epitaxial growth to a thickness of about 10.0 μm. .

[Step shown in FIG. 2B] On the surface of the n-type drift region 2, an LTO film 21 having an opening in a p-type gate region formation planned portion is arranged, and the LTO film 21 is used as a mask to inactivate ions. Ion implantation of C ⁺ (carbon) as a seed is performed. At this time, the p-type gate region 4 is formed by ion implantation.
The ion implantation conditions are set so that C ⁺ is implanted to the depth of the region 4A (see FIG. 1).

As a result, C ⁺ enters the vacancies of the carbon sites, the vacancies of the carbon sites are eliminated, and the crystal defects existing in the n-type drift region 2 are repaired.

[Step shown in FIG. 3A] Using the LTO film 21 as a mask again, B ⁺ (boron) ion implantation is performed. As a result, the p-type gate region 4 is formed. In this case, as B ⁺ is injected superimposed on C ⁺ in the region 4A where C ⁺ is injected, further, B ⁺ is implanted to a region 4B of the position deeper than the region 4A of the C ⁺ is implanted The ion implantation conditions are set so that

[Step shown in FIG. 3 (b)]
Activate the injected B ⁺ . At this time, in the region A, since C ⁺ is injected together with B ⁺ to repair the crystal defect, thermal diffusion of B ⁺ is suppressed, and B ⁺ is activated almost at the position where it is injected. . On the other hand, in the region B, since C ⁺ has not been implanted, diffusion in the lateral and downward directions proceeds. As a result, in the region 4B, B ⁺ is laterally diffused to below the n-type source region 3 which will be formed in a later step (step shown in FIG. 4A). Among the p-type impurities, B ⁺ is an atom that easily thermally diffuses, and for example, A ⁺
Heat diffusion is easier than with l ⁺ (aluminum).

Thus, by the lateral diffusion of C ⁺ , p
Since the region 4B of the type gate region 4 is made to enter below the n-type source region 3, the p-type gate region 4 having the above structure can be easily formed without requiring high-energy ion implantation. .

Further, since B ⁺ is thermally diffused in the region 4B of the p-type gate region 4, it is possible to reduce the impurity concentration of the region 4B and prevent B ^{+ from} being thermally diffused in the region 4B. Therefore, the impurity concentration of the region 4A can be increased. Therefore, the adjacent region 4B
To the n-type drift region 2 between them, the depletion layer can be easily extended to have normally-off characteristics, and the region 4A can be made low in resistance, so that the contact resistance with the gate electrode can be made low.

Here, in FIG. 6, (112 of 6H--SiC is used.
-0), (11-00), (0001) plane is used to set B to 4
The profiles in the depth direction immediately after the ion implantation and after the thermal treatment after the ion implantation at 00 keV and the heat treatment at 1700 ° C. for 30 minutes are shown.

As shown in this figure, the diffusion amount of B is <112-0>, <11-00>, <0001>.
Will be in order. Therefore, in order to increase the width of the region 4B in the lateral direction, it is desirable that the direction of expansion, that is, the direction of diffusing B is <1120> because the amount of diffusion becomes maximum. From this, it is desirable that the element pattern also has a stripe cell shape in which the p-type gate regions 4 are arranged in parallel (the p-type gate regions 4 extend perpendicular to the drawing).

Further, as shown in FIG. 6, it is desirable that the direction in which B is laterally diffused is set to <112-0> because the diffusion amount becomes maximum compared to other directions.

[Step shown in FIG. 4A] After the LTO film 21 is removed, the LTO film 22 having an opening in the portion where the n-type source region is to be formed is arranged, and the LTO film 22 is used as a mask to form an N film.
Either or both of ⁺ (nitrogen) and P ⁺ (phosphorus) are ion-implanted to form the n-type source region 3. At this time, the opening of the LTO film 22 is sufficiently smaller than the distance between both regions 4A of the p-type gate region 4 so that the n-type source region 3 does not come into contact with the p-type gate region 4 in view of the mask shift. To do.

[Step shown in FIG. 4B] After removing the LTO film 22, a polysilicon film is arranged on the entire surface of the wafer, and then the polysilicon film is patterned to form the gate electrode 6.

[Step shown in FIG. 5A] After the passivation film 9 is arranged on the entire surface of the wafer, it is patterned to form a contact hole communicating with the n-type source region 3 in the passivation film 9.

[Step shown in FIG. 5B] A conductive film such as an Al film is deposited on the entire surface of the wafer to form a source electrode 7 electrically connected to the n-type source region 3.

Then, A is formed on the back surface side of the n-type drain region 1.
A conductive film such as an L film is deposited to form a drain electrode 8 electrically connected to the n-type drain region 1. In this way, the SIT shown in FIG. 1 is completed.

(Second Embodiment) In this embodiment, the manufacturing process of SIT is changed from that of the first embodiment.
Since the configuration and manufacturing process of the SIT of this embodiment are almost the same as those of the first embodiment, only different parts will be described.

The manufacturing process of the SIT according to this embodiment will be described below with reference to FIG. In the manufacturing process of the SIT in this embodiment, the same parts as those in the first embodiment will be described with reference to FIGS.

First, the process shown in FIG.
An n-type drift region 2 is formed on the type drain region 1. Then, the process shown in FIG. 7 is implemented.

[Step shown in FIG. 7A] An LTO film having an opening between the regions 4A (see FIG. 1) of the p-type gate region 4 is arranged on the surface of the n-type drift region 2, and this LTO film is formed. Ion implantation of C ⁺ (carbon), which is an inert ion species, is performed as a mask. At this time, the ion implantation conditions are set so that C ⁺ is implanted to the depth of the region 4A of the p-type gate region 4 by ion implantation.

As a result, C ⁺ enters the vacancy of the carbon site, and the crystal defect existing in the n-type drift region 2 is repaired.

Then, B ⁺ (boron) ion implantation is carried out using the LTO film 25 having an opening at the p-type gate region formation planned portion as a mask. At this time, the ion implantation conditions are set such that B ⁺ is implanted deeper than the region into which C ⁺ was implanted formed in the step of FIG. 7A. As a result, the p-type gate region 4 is formed. Thus, between the two regions 4A of p-type gate region 4, a state where a region C ⁺ is injected it is interposed, between the regions 4B and state region C ⁺ is implanted is not interposed Become.

[Step shown in FIG. 7B] Heat treatment is performed,
Activate the injected B ⁺ . At this time, in the region 4A, as between the two regions 4A, because the C ⁺ crystal defects are implanted is repaired, B ⁺ lateral diffusion is suppressed, B ⁺ is intact was almost injected Activated in position. On the other hand, in the region 4B, since C ⁺ is not injected between the both regions 4B, diffusion in the lateral direction proceeds. As a result, in the region 4B, B ⁺ is laterally diffused to below the n-type source region 3 which will be formed in a later step.

In this way, the region 4A of the p-type gate region 4 is formed.
Even if C ⁺ is ion-implanted between the regions, the lateral diffusion can be suppressed in the region 4A and the region 4B can be formed so as to penetrate below the n-type source region 3 by the lateral diffusion. The same effect as that of the first embodiment can be obtained.

After this, as in the first embodiment, as shown in FIGS.
The SIT in this embodiment is completed by carrying out the process shown in FIG.

The SIT structure of this embodiment is such that C ⁺ does not exist in the region 4A of the p-type gate region 4 and C ⁺ exists between both regions 4A. Is different from the first embodiment, but the other configurations are the same.

(Other Embodiments) In the first embodiment, C ⁺ is ion-implanted as an inert ion species into the region 4A of the p-type gate region 4, and in the second embodiment, both regions are implanted. Although C ⁺ is ion-implanted as the inactive ion species during 4A, the inactive ion species may be ion-implanted into both of them.

In each of the above embodiments, C ⁺ is used as the inactive ionic species, but other inactive ionic species,
For example, Ar (argon), He (helium), Si (silicon), or the like may be used.

Further, in the above embodiment, C ⁺ ion implantation is carried out in order to suppress thermal diffusion of B ⁺ in the region 4A of the p-type gate region 4, but other methods can be used. is there. For example, even if Al ⁺ having a very small thermal diffusion amount is used for the region 4A and B ⁺ having a large thermal diffusion amount is used for the region 4B,
Similar to the above-described embodiment, the implanted impurities are activated in the region 4A in the substantially ion-implanted state, and the impurities are allowed to enter below the n-type source region 3 in the region 4B. Therefore, the same effect as that of the above embodiment can be obtained. In addition, when indicating the azimuth, a bar (-) should normally be attached above the desired number, but due to the limitation of the expression, the bar is attached after the desired number.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional configuration of a SIT according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the SIT shown in FIG.

FIG. 3 is a diagram showing the SIT manufacturing process following FIG. 2;

FIG. 4 is a diagram showing the SIT manufacturing process following FIG. 3;

FIG. 5 is a view showing the SIT manufacturing process following FIG. 4;

FIG. 6 is a diagram showing changes in the amount of diffusion when B is thermally diffused after ion implantation. (A) shows the case where the (0001) Si plane is ion-implanted, and (b) shows (11-00). ) When ion implantation is performed on the a-plane, (c) is (112-0) a.
It is a figure which shows the case where the ion implantation was performed to the surface.

FIG. 7 is a diagram showing a manufacturing process of an SIT according to the second embodiment.

FIG. 8 is a diagram showing a cross-sectional structure of a conventional SIT.

FIG. 9 is a diagram showing a result of examining a withstand voltage at the time of reverse bias in a conventional SIT.

[Explanation of symbols]

1 ... n type drain region, 2 ... n type drift region, 3 ... n
Type source region, 4 (4A, 4B) ... p-type gate region, 6
... gate electrode, 7 ... source electrode, 8 ... drain electrode, 9
... passivation film.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-10-294471 (JP, A) JP-A-57-172765 (JP, A) JP-A-59-52882 (JP, A) JP-A-10- 308510 (JP, A) JP 59-108366 (JP, A) JP 2000-216407 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29 / 778 H01L 29/80 H01L 29/812

Claims (8)

(57) [Claims] 1. A low-resistance drain region (1) having a main surface and a surface opposite to the main surface; and a first-conductivity-type drain region (1) formed on the main surface of the drain region and having a higher resistance than the drain region. Drift region (2)
A source region (3) of the first conductivity type formed on the surface layer portion of the drift region and having a resistance lower than that of the drift region; and the source on each side of the source region in the surface layer portion of the drift region. A second conductive type gate region (4) formed apart from the region; a gate electrode (6) formed on the gate region and electrically connected to the gate region; and on the source region. A source electrode (7) formed in the drain region and electrically connected to the source region, and a drain electrode (8) formed on the opposite surface of the drain region and electrically connected to the drain region. The gate region is formed of a p-type semiconductor, and includes a first region (4A) formed from a surface of the drift region to a position where a junction depth is deeper than that of the source region, and the first region (4A). Junction depth are formed deep, the second configured to penetrate to the lower of the source region
Region (4B), the second region has a lower impurity concentration than the first region, and the first region has Al ⁺ as a p-type impurity.
Is used, wherein the second region B as a p-type impurity ⁺
Carbonization silicon semiconductor device you characterized in that is used. 2. The silicon carbide semiconductor device according to claim 1, wherein the first region is doped with an inert ion species. 3. The drift region is doped with an inert ion species between the first regions formed on both sides of the source region, respectively. 2. The silicon carbide semiconductor device according to 2. 4. A drift region (1) of the first conductivity type having a higher resistance than the drain region is provided on the main surface of a drain region (1) having a low resistance having a main surface and a surface opposite to the main surface. And a source region (3) of the first conductivity type having a resistance lower than that of the drift region is formed on a surface layer portion of the drift region, and a gate region of the second conductivity type is provided on both sides of the source region. In the method for manufacturing a silicon carbide semiconductor device including (4), an ion species that is inactive to a predetermined depth deeper than the source region is formed in a portion of the surface region of the drift region where the gate region is to be formed. A step of implanting ions, and a region (4A) of the surface layer portion of the drift region into which the inactive ionic species is implanted and a region of the second conductivity type deeper than a depth in which the inactive ionic species are implanted. Impurities The step of injecting on and the heat treatment activate the impurities of the second conductivity type, and suppress the lateral diffusion of the impurities of the second conductivity type up to the depth to which the inactive ion species are implanted. Forming a gate region by laterally diffusing the second conductivity type impurity so as to enter below the source region in a region deeper than a depth into which the active ion species is implanted; and the drift region. And a step of forming the source region on the surface layer portion so as to be separated from the gate region, the method for manufacturing a silicon carbide semiconductor device. 5. A drift region (1) of the first conductivity type having a higher resistance than the drain region is provided on the main surface of a drain region (1) having a low resistance having a main surface and a surface opposite to the main surface. And a source region (3) of the first conductivity type having a resistance lower than that of the drift region is formed on a surface layer portion of the drift region, and a gate region of the second conductivity type is provided on both sides of the source region. In the method for manufacturing a silicon carbide semiconductor device having (4) formed therein, the source region is formed between portions of the surface layer portion of the drift region where the gate regions are arranged on both sides of the source region. A step of implanting an inactive ionic species to a deeper predetermined depth, and a surface layer portion of the drift region, in a portion where the gate region is to be formed, than the depth at which the inactive ionic species is implanted. A step of implanting the second conductivity type impurity up to a certain region, and heat treating to activate the second conductivity type impurity, and to reach the depth to which the inert ion species are implanted, the second conductivity type impurity Lateral diffusion is suppressed, and in a region deeper than the depth at which the inert ion species are implanted, the second conductivity type impurity is laterally diffused and penetrates below the source region to form the gate region. And a step of forming the source region on the surface layer portion of the drift region so as to be separated from the gate region. 4. A method for manufacturing a silicon carbide semiconductor device, comprising: 6. In the step of forming the gate region, the second conductivity type impurity is laterally diffused in a <112-0> direction in a region deeper than a depth into which the inert ion species are implanted. the method for manufacturing the silicon carbide semiconductor device according to claim 4 or 5, wherein. 7. The step of implanting the second conductivity type impurity by ion implantation of B (boron) as the second conductivity type impurity, and the step of implanting the inert ion species by the ion implantation of the inert ion species. the method for manufacturing the silicon carbide semiconductor device according to any one of claims 4 to 6, characterized in that ion implantation is performed C (carbon) as active ion species. 8. An n-type drift region (2) having a higher resistance than the drain region is provided on the main surface of a low resistance drain region (1) having a main surface and a surface opposite to the main surface, An n-type source region (3) having a resistance lower than that of the drift region is formed in a surface layer portion of the drift region, and p-type gate regions (4) are formed on both sides of the source region. In the method for manufacturing a silicon carbide semiconductor device as described above, in a portion of the surface layer portion of the drift region where the gate region is to be formed, a depth A deeper than the source region is formed.
l (aluminum) is ion-implanted, and B (boron) is ion-implanted in a region deeper than the Al-implanted region in the surface layer portion of the drift region. The heat treatment activates the Al and the B,
Laterally diffusing so as to enter below the source region to form the gate region, and forming the n-type source region on the surface layer portion of the drift region so as to be separated from the gate region. A method for manufacturing a silicon carbide semiconductor device, comprising: