JP3440286B2 - Mobile terminal - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mobile terminal such as a mobile phone, and more particularly to a mobile terminal with low power consumption.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing a configuration of a general portable terminal. As shown in the figure, the mobile terminal has an antenna 71 for communicating with a base station, an RF unit 72 for high-frequency signal processing, a digital processing unit 73 for processing digital data, an operation unit 74 including push buttons, a microphone / speaker, etc. The audio unit 75 and the like are included.

The digital processing unit 73 has a high-speed CPU (central processing unit), and encodes / decodes voice signals, encodes / decodes transmission paths, TDMA timing control, protocol processing, clock control, and man-machine I. It processes digital data such as / F control and controls the entire terminal.

In a mobile terminal such as a PHS system mobile phone or a PDC system mobile phone, usually TDMA (time division multiple access)
A system is adopted, which constantly communicates with a base station using a control channel, registers its own location, and responds to a call from the base station. However, instead of always receiving continuously, for example, a PDC mobile phone receives intermittently from a base station, and in the intermittent receiving state, once at maximum 36 frames (1 subframe = 20 ms). .6 ms (= 1
(Slot) is received at the ratio of the reception period and communicates with the base station.

A mobile terminal normally uses a battery as a driving power source. Therefore, it is desired that the power consumption of the mobile terminal is as small as possible. As one of the low power consumption,
A method of setting the CPU in a sleep mode to stop the supply of the operation clock when the processing by the CPU is not necessary and a method of lowering the frequency of the operation clock are adopted.

[0006]

However, in the conventional portable terminal, even if the sleep mode state (operation stop) of the CPU continues for a long time in the intermittent reception state, the clock oscillation source is stopped in order to match the timing of the reception signal. In this case, when the oscillation is restarted, there is a problem that it takes time until stable oscillation takes place and the timing does not match. Therefore, the clock oscillation source (oscillator that oscillates a high frequency clock of several MHz to several tens MHz) constantly oscillates. Is in a state. The clock oscillation source requires a maximum current consumption of about several mA, and there is a problem in that the power of the battery, which is the driving power source of the portable terminal, is wasted.

In addition, due to the system configuration of the mobile terminal, RF / I
Even in a block having a clock oscillator such as a PLL synthesizer or VCO to the F control unit, setting the clock oscillator in the oscillating state at the time of intermittent reception requires current consumption and wastes power of a battery which is a driving power source of the mobile terminal.

The present invention has been made in view of the above points, and when the CPU is in the sleep mode during intermittent reception, C
An object of the present invention is to provide a mobile terminal capable of further reducing power consumption by stopping a high frequency clock oscillator that supplies an operation clock to a PU and a clock oscillator of another block.

[0009]

In order to solve the above-mentioned problems, the invention according to claim 1 has a CP having a sleep mode.
U, a high-frequency clock oscillation source that emits an operation clock of the CPU, and a low-frequency clock oscillation source that emits a clock of a frequency lower than the operation clock, and divides the clock of the high-frequency clock oscillation source to generate a trace clock. when a mobile terminal communicating with division method, when it enters the discontinuous reception is set in consideration of the oscillation stabilization time of the high frequency clock source at the same time return timing enters the intermittent mode at the CPU together, the high frequency Stops the clock oscillation source, puts the CPU in sleep mode, changes the clock from the high-frequency clock oscillation source to the divided clock for trace, and counts the clock from the low-frequency clock oscillation source, and generates a restoration trigger signal when the restoration timing is reached. Control for operating the high-frequency clock oscillation source to return the CPU to the normal mode Characterized in that a stage.

The invention described in claim 2 is the same as claim 1.
In the portable terminal described in the above item 1, the portable terminal includes another constituent block having a clock oscillation source, and when the CPU enters the intermittent mode, the constituent block is powered off at a predetermined timing and restored by a return trigger signal. It is characterized in that a power supply control means is provided.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration example of an intermittent control unit of a mobile terminal embodying the present invention, and FIG. 2 is a diagram showing an intermittent reception control timing of the intermittent control unit. Figure 1
In the above, the intermittent control unit is composed of a CPU 1, an intermittent enable bit 2, a receiving unit 3, a return position control unit 4 and a clock management unit 5. A 42 KHz clock obtained by dividing the output clock of 12.6 MHz from the clock management unit 5 and a 32.768 KHz clock from a clock oscillator (not shown) are input to the return position control unit 4. In addition, in FIG.
One MA data frame is set to 720 msec, and the one data frame consists of 0 to 35 slots (one slot is 20 msec).

In the above structure, when the intermittent reception is started, C
The PU outputs an intermittent command to the intermittent enable bit 2 to set the intermittent reception control unit 6 to the intermittent mode and at the same time outputs a clock stop command to the clock management unit 5 to stop the oscillation operation of the clock oscillation source of the clock management unit 5. Then, the next slot return position is output and stored in the return position (see the intermittent reception cancellation position in FIG. 2) control unit 4,
The CPU itself goes into sleep mode. In the intermittent reception, the receiving unit 3 uses a 42K slot counter that counts a 42KHz clock and a 32.768KHz, as will be described later.
It has a spare 32K slot counter that counts the clocks of.

Since the output of the 42 KHz clock from the receiving unit 3 is stopped during the intermittent reception, the 32 K slot counter counts the 32.768 K Hz clock and traces it instead of the 42 K slot counter. When the count value of the 32K slot counter reaches the slot return position, the return position control unit 4 outputs an intermittent stop signal to the intermittent enable bit 2 to cancel the intermittent mode of the intermittent reception control unit 6 and at the same time the clock management unit 5 Outputs an oscillation recovery command to and activates the clock oscillation source. This return position is set in consideration of the oscillation stabilization time during which the clock oscillation of the clock oscillation source stabilizes.

Since the 42K slot counter and the 32K slot counter of the return position control unit 4 are asynchronous,
As will be described later, the 32K slot counter corrects once every 720 msec (one data frame) with the 42 KHz clock from the receiving unit 3. As shown in FIG. 2, 0-3
Reception is performed only at the reception position in the 5 slots, and is stopped at other times.

As described above, the slot return position is always CP.
Set by U, the CPU enters the sleep mode after the setting, and the intermittent enable bit 2 and the oscillator of the clock management unit 5 are stopped until the slot return position comes. The 32.768 KHz clock oscillator is always oscillating, but its current consumption is about 10 μA and 12.6 M
The current consumption of the clock management unit 5 for Hz is very small compared to 1 mA. An RTC clock clock oscillator is used as the 32.768 KHz clock oscillator.

FIG. 3 is a diagram showing a configuration example of the return position control unit 4 of FIG. As shown, the return position control unit 4 is
2K slot counter 21, 32K slot counter 2
2, selector 23, slot counter 24, comparator 25
And a register 26, the 42K slot counter 21 counts the 42KHz clock from the receiving section 3, and the 32K slot counter 22 counts the 32.768KHz clock from the clock clock oscillator. The switching signal of the selector 23 is a signal generated at the same time as the intermittent reception of FIG.
Consists of appropriate hardware.

At the receiving position in FIG. 2, the 42K slot counter 21 counts the 42KHz clock from the receiving section 3, and the output thereof is input to the slot counter 24 through the selector 23. When the intermittent reception is started, the CPU 1 outputs the clock stop command to the clock management unit 5 at the same time as the intermittent mode is entered, the clock oscillation source is stopped, and the slot return position is set to the register 2 as described above.
Store in 6.

Upon entering intermittent reception, a switching signal is input to the selector 23, the output of the 32K slot counter 22 is input to the slot counter 24 via the selector 23, and the output of the slot counter 24 is input to the comparator 25. To be done. The comparator 25 compares the slot return position set in the register 26, and when the output of the slot counter 24 reaches the return position, outputs a return trigger TR to the clock management unit 5. The clock management unit 5 is activated, and after the oscillation stabilization time (see FIG. 2), 1
The clock signal of 2.6 MHz is supplied to the receiving unit 3. As a result, the reception state is set.

FIG. 4 is a diagram showing a configuration of a power supply control management unit of another configuration block having a clock oscillation source using the return trigger TR. As shown, VCO31
The PLL synthesizer 32 includes a clock oscillation source including an oscillation element 33. A clock is supplied from this PLL synthesizer 32 to other constituent blocks. In this case, even if it is not necessary to supply the clock to other constituent blocks, if the oscillation source is operated and kept in the operating state, the power of the battery, which is the drive power source, is consumed without permission.

Therefore, the timing generator 34 is provided, and the 42 KHz clock from the receiving unit 3 is input to start the intermittent reception, and the VCO 31 and the PLL synthesizer 32 are supplied with the power supply control signal V _VCO and the power supply control signal V at a predetermined timing. _{Set the PLL} to the L (low) level, VCO31 and PL
The L synthesizer 32 is stopped and the clock supply to other constituent blocks is stopped. When the trigger TR is output at the return position (reception position in FIG. 2), the power supply control signal V _VCO and the power supply control signal V _PLL are set to H (high) level,
The VCO 31 and the PLL synthesizer 32 are activated, and a clock signal is supplied to other constituent blocks. As a result, the constituent block having the clock oscillation source at the time of intermittent reception is stopped, so that it is possible to reduce the power consumption of the battery as the driving power source.

FIG. 5 is a diagram for explaining a method of correcting the deviation between the 42K slot counter 21 and the 32K slot counter 22 due to the intermittent reception. 42 as described above
Since the KHz clock and the 32.768 KHz clock are asynchronous, there is a deviation between the 42K slot counter and the 32K slot counter. As shown in the figure, the unique pattern SW is included in the 20-bit synchronization word of the reception slot. The synchronization word is detected bit by bit so that this bit can be detected, and correction is performed when this unique pattern SW is detected.
Correct the deviation between the K slot counter and the 32K slot counter. The reception slot of the unique pattern SW is contained in bits 117 to 137. Although there is a tolerance of ± 1 bit, when this bit is detected, the 42K slot counter and 32K slot counter are corrected.

FIG. 6 is a diagram showing operation timings of FIGS. 1, 2 and 4. As shown in the figure, the intermittent setting and reception enable (output of the intermittent enable bit 2 in FIG. 1) by the CPU 1 and the power control signals (power control signal V _VCO and power control signal V _{PLL in} FIG. 4) to other blocks are at L level. Therefore, the 42KHz clock and the 42K slot counter are stopped by stopping the oscillation source of the clock management unit 5. In addition, the 32K slot clock is counted by the 32K slot counter and is traced by the 32K slot counter instead of the trace by the 42K slot counter. Then, it returns at the return position set by the CPU 1 and supplies the 42 KHz clock after the oscillation stabilization time of the oscillation source has elapsed. Furthermore, 42K slot counter and 3 by SW detection
Correct the 2K slot counter.

[0023]

【The invention's effect】

(1) As described above, according to the invention described in claim 1, since the high-frequency clock oscillation source is stopped during the intermittent reception, it is possible to obtain an effect of suppressing the power consumption.

(2) Further, according to the invention described in claim 2, since the clock oscillation of the other blocks is also stopped during the intermittent reception, it is possible to further reduce the power consumption.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of an intermittent control unit of a mobile terminal of the present invention.

FIG. 2 is a diagram showing the intermittent reception control timing of the intermittent control unit of the mobile terminal of the present invention.

FIG. 3 is a diagram showing a configuration example of a return position control unit of the mobile terminal of the present invention.

FIG. 4 is a diagram showing a configuration example of a power supply control management unit of another configuration block having a clock oscillation source of the mobile terminal of the present invention.

FIG. 5 is an explanatory diagram of a method of correcting a deviation between a 42K slot counter and a 32K slot counter.

FIG. 6 is a diagram showing operation timing of the mobile terminal of the present invention.

FIG. 7 is a diagram showing a configuration of a general mobile terminal.

[Explanation of symbols]

1 CPU 2 Intermittent enable bit 3 Receiver 4 Return position controller 5 Clock management section 6 Intermittent reception control section 21 42K slot counter 22 32K slot counter 23 Selector 24 slot counter 25 comparator 26 registers 31 VCO 32 PLL synthesizer 33 oscillator 34 Timing Generator

Claims (2)

(57) [Claims] 1. A CPU having a sleep mode and the CPU
And a low frequency clock oscillation source that emits a clock having a lower frequency than the operation clock, and divides the clock of the high frequency clock oscillation source to generate a trace clock, which is time-division a mobile terminal communicating in a manner, both when it enters the discontinuous reception is set in consideration of the oscillation stabilization time at the same time return timing enters the intermittent mode the high frequency clock source in the CPU, the high-frequency clock oscillator Source is stopped to put the CPU in the sleep mode, the clock from the high frequency clock oscillation source is divided into a trace clock, the clock from the low frequency clock oscillation source is counted, and a restoration trigger signal is reached when the restoration timing is reached. To operate the high-frequency clock oscillation source to set the CPU to the normal mode. A mobile terminal provided with a control means for returning to. 2. The portable terminal comprises another constituent block having a clock oscillation source, and when the CPU enters an intermittent mode, the constituent block is powered off at a predetermined timing, and is restored by the restoration trigger signal. The mobile terminal according to claim 1, further comprising a power supply control means for controlling the power supply.