JP3408149B2 - Standby power consumption controller - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power consumption control device, and more particularly to a standby state power consumption control device for reducing power consumption in a standby state.

[0002]

2. Description of the Related Art Generally, the state of a device which is energized depends on the state of the power supply, that is, the operating state or the POWERON state (hereinafter, P
_ON mode) and a standby state, or a POWEROFF state (hereinafter, P_OFF mode). In P_ON mode, power is supplied to all circuits so that all operations of the device can be performed.
In the P_OFF mode, power supply to unnecessary circuits is stopped when not in operation to reduce power consumption.

FIG. 10 shows an example of the conventional technique, and the outline of the conventional technique will be described with reference to FIG.

When energized, the AT (All Time) power source 1 always supplies power. In the P_ON mode, the signal from the microcomputer 2 causes PCON (Power
rControl) SW3 is ON and P
When the CON power supply 4 is supplied with power, both the AT system circuit 5 and the PCON system circuit 6 are in the operating state.

When the P_OFF mode is entered by a request from the user request detection circuit 8 to the microcomputer 2, PCON is turned on.
Since the SW3 is turned off and the power supply to the PCON power supply 4 is stopped, the power consumed by the PCON system circuit can be suppressed.

Further, when the power supply from the outside is interrupted and a power failure occurs, the microcomputer 2 operates by the power supply from the backup power supply 7, detects the stop of the power supply from the AT power supply, and detects the AT system circuit. 5. After setting the state of the PCON system circuit 6 to the low power consumption state, the microcomputer operation reference clock is switched to a low speed, and while waiting for the energized state, the clock count or the like during a power failure is performed Power failure mode).

When the power supply from the AT power supply 1 is started, the microcomputer 2 detects that the power is on, switches the operation reference clock to the high speed mode, and then the AT system circuit 5 and the PCON system circuit 6 operate. Return the state to the energized state, P_O
It becomes FF mode.

As another conventional technique for reducing the power consumption in the standby state as disclosed in Japanese Patent Laid-Open No. 7-7696, a third economy mode other than the P_ON mode and the P_OFF mode is provided. In some cases, the operating voltage is supplied only to the remote control receiver and the filter connected to its output, and when the remote control receiver detects any input, the microcomputer power is supplied for the first time to identify the remote control code and enter the normal operation mode. is there.

[0009]

In the first conventional example, when it is desired to further reduce the power consumption in the standby mode of the device from the P_OFF mode, the control state of the circuit should be as close to the power failure state as possible. However, in the conventional power failure mode, since the circuit for inputting the user's key operation is also stopped, it is not possible to return to the P_ON mode or the like, and it cannot be handled as a normal standby state.

Further, in the second conventional example, when external light enters the remote control receiver, the power supply of the microcomputer may be frequently turned on and off and the microcomputer reset may fail, and the timer reservation may not be performed. If so, the microcomputer could not be turned off and the third economy mode could not be entered, and the power consumption in the standby state could not be reduced.

The present invention is intended to provide means for solving the above problems.

[0012]

In order to solve the above problems, the present invention has any structure.

That is, according to the present invention, first control means for controlling the power supply of the first functional block, second control means for controlling the power supply of the second functional block, and at least the first control means. A standby state power consumption control device comprising a control means, a third control means for controlling the second control means, and an operation speed switching means for switching the operation speed of the third control means. first input means for determining whether the input signal from the outside supplied, and a a / D converter that identifies a potential difference between the input signal from the external receiving power from the first function block The first control means and the second control means cut off power supply to the first functional block and the second functional block, and the operating speed switching means controls the third control. The operation speed of the means is low When the input signal from the outside is detected by the first input means in the standby state where it is controlled, the first control means supplies power to the first functional block and the operation is performed. The speed switching means controls the operating speed of the third control means to a high speed, and the A / D converter receives power supply from the first functional block.
When the potential difference of the input signal from the outside is identified by the converter and it is determined that it is valid, the second control means supplies power to the second functional block, and when it is determined that it is invalid, the standby state It is a standby state power consumption control device characterized by being returned to. Here, prior to Symbol using microcomputer third control means, said first input means has preferably be an interrupt signal input terminal of the microcomputer. In addition, when the second control unit returns to the standby state after shifting to the operating state where power is supplied to the second functional block, the second control unit causes the second control unit to return to the standby state. The timing of shutting off the power to the functional block, the timing of shutting off the power to the first functional block by the first control means, and the operating speed of the third control means by the operating speed switching means It is preferable to provide a time lag of a predetermined time at the timing of controlling at low speed. Further, it is preferable that a timer reservation unit is provided, and when there is a timer reservation when shifting from the operating state to the standby state, a warning indicating that there is a timer reservation is displayed for a predetermined time.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a first embodiment of the present invention, and description will be made based on this.

[0015] The present embodiment in FIG. 10 in the conventional example, A
A part of the T-system circuit 5 is separated as a STBY (Stand-by) system circuit 11 , and the STBY-system circuit
Reference numeral 11 corresponds to a circuit that processes an input for operating a device controlled by the STBYSW 9 that is the first control means. When there is a request to shift to a low power consumption standby state (hereinafter, P_LOW mode) by a user operation, as shown in the flowchart of FIG.
PC which is the second control means by the signal from the microcomputer 2
The ONSW 3 is turned off, the power supply to the PCON power supply 4 is stopped, and the power consumption in the PCON system circuit 6 is made zero.

Next, the signal from the microcomputer 2 turns off STBYSW9, which is the first control means.
The power supply to the power supply 10 is stopped, and the power consumed by the STBY system circuit 11 for processing the input can be suppressed.

After that, the microcomputer 2 eliminates power consumption in each circuit connected to the control terminal of the microcomputer 2,
Each control terminal is switched to “L” output or the like, the operation reference clock is normally changed from the high speed mode of several MHz to the low speed mode of several tens KHz, and then the transition to the P_LOW mode is completed.

To return from the P_LOW mode to the normal state, as shown in the flowchart of FIG. 3, the power supply to the STBY system circuit for processing the input is stopped,
Even in this state, the microcomputer 2 determines the presence / absence of a transition request to the operating state of the user by an input circuit capable of determining at least the presence / absence of an input.

When there is a request from the user to shift to the operating state, the operation reference clock is switched from the low speed mode to the high speed mode, the STBYSW 9 is turned on, and the contents of the request to shift to the operating state are confirmed. For example P
When the input of the _ON key is detected, the shift operation to the P_ON mode is performed.

Regarding the second embodiment of the present invention, the user request detection circuits 16 and 17 of the block diagram shown in FIG. 1 are used as the general-purpose input 14 of FIG. 4 (generally, a C-MOS for reducing power consumption). The case of key input by the A / D converter 15 having a switching function of the input / output of the format) and the resistance ladder shown in FIG. 5 will be described as an example.

Generally, since the time until data conversion is slower in the A / D converter than in general-purpose input, sampling for request detection is performed with the microcomputer 2 in the low speed mode of the operation reference clock. Doing so will increase the power consumption of the microcomputer.

When using the A / D converter, it is necessary to always supply power.

However, during the P_LOW mode, since the main purpose is to shift to the operation mode, the necessary keys are often limited, so that the SW that generates a voltage level that can be detected even by a general-purpose input is used. (Speaking of FIG. 5, SW1
, Etc.) is assigned with a request key for shifting to the operation mode in the P_LOW mode.

For example, if the AT power supply is 5V, SW1 to SW
If the voltage is evenly divided by 6, press SW1 to obtain 0V,
SW2 is 0.83V, SW3 is 1.67V, and these potential differences are normally identified by the A / D converter. On the other hand, in the case of a general-purpose input such as a C-MOS, it is determined to be an "L" input if it is approximately the intermediate potential of the power supply voltage, in this case lower than 2.5V, and "H" if higher than 2.5V. Therefore, if you press SW1 or SW2, 2.5V
Since it is lower, it can be determined that there is an “L” input.

By thus switching to the general-purpose input and sampling the terminal input, it becomes possible to determine the presence or absence of a request.

If a plurality of keys, such as SW1 and SW2, are regarded as a request to shift to the operation mode, such as when the voltage is equally divided by SW1 to SW6, the general input is left as it is. Since it is not possible to determine which key is input, the operation reference clock of the microcomputer 2 is switched to the high speed mode, the STBY power supply 10 is supplied with power, the A / D converter is returned to the operation state, and the SW input is performed. The voltage level at that time is identified and which SW is pressed is determined.

If the result of this determination is invalid, PCON
It is possible to return to the low power consumption standby state again before switching the state of the system circuit to the operating state. If the determination result is valid, the P_ON mode is entered. The operation of the microcomputer 2 at this time is shown in FIG.

The third embodiment of the present invention uses the interrupt request terminal of the microcomputer instead of the sampling of general-purpose input for user request detection in the second embodiment.
For example, even if the microcomputer is in the sleep mode, the presence or absence of the input can be determined by the activation by the interrupt, and the power consumption can be reduced as compared with the sampling.

In the fourth embodiment of the present invention, in the second embodiment, when the user request is detected from the remote controller, the power source of the remote controller reception signal discriminating circuit for measuring the cycle of the remote controller is used as the first power source. Even when the control means is turned off, it is determined by sampling the C-MOS input terminal whether or not there is a remote control reception signal. If it is determined, the first control means is turned on and the cycle of the remote control. The power supply of the discrimination circuit of the remote control reception signal such as measurement is turned on, the operation reference clock is set to high speed to judge the received remote control code, and the operation according to the judgment result can be performed.

The fifth embodiment of the present invention is the third embodiment of the present invention.
Similar to the embodiment of the present invention, the user request is detected by using the interrupt terminal of the microcomputer instead of the sampling of the general-purpose input. The power consumption can be reduced as compared with the case of performing it.

In the sixth embodiment of the present invention, FIG. 7 is replaced with a cassette insertion state detection circuit 12 (corresponding to a separately provided recording medium insertion detection switch) of the user request detection circuit 8 of FIG. Further, a mechanical position detection circuit 13 for adding mechanical position information to the microcomputer 2 is added.

The cassette insertion state detection circuit and the mechanical position detection circuit 13 which are originally used often use a detection circuit composed of a light emitting diode and a phototransistor.
Until now, these detection circuits were driven by the AT power supply and always operated.

The power supply of these circuits is controlled by the first control means 9 . When the cassette is not mounted and is already in the P_LOW mode, when the cassette is inserted, the separately provided cassette insertion state detection circuit 12 starts the transition to the P_ON mode. At this time, the first control means 9 is O
When the value becomes N, the conventional cassette insertion state detection circuit and the mechanical position detection circuit 13 using the detection circuit composed of the light emitting diode and the phototransistor start operating, and the normal operation is restored.

From the mechanical position detection circuit 13, the mechanical SW shown in FIG.
Signals such as (A) and (B) are obtained, and the microcomputer 2 creates information on mechanical position codes (H) and (L) based on this signal, and the mechanical position at that time is generated. It manages the state of. Further, a general tact SW is used as the cassette insertion SW, and when the cassette is not attached, the cassette insertion SW is continuously pushed by the force of the spring due to the state of the master cam.

When the cassette insertion operation is performed in the P_LOW mode in the cassette non-insertion state, the cassette insertion SW, which was pushed by the force of the spring, is released, and a microcomputer is issued as a request to shift to the operation state. 2 executes the transition processing to the operating state as described above. In addition, when it is in the P_LOW mode when the cassette is completely installed, it is easy to recognize that the cassette has been completely installed by the information of the mechanical position mode and invalidate the request to shift to the operation state by the cassette insertion SW. By providing such a SW circuit, it becomes possible to realize the transition to the operating state by the cassette inserting operation. FIG. 9 shows a flowchart of the microcomputer 2 in this case.

In the seventh embodiment of the present invention, for example, when there is a remote control input for a short time and the microcomputer operation reference clock is switched from low speed to high speed, it is generally switched after there is any input. The code can not be correctly judged at the beginning of the code, and the first code judgment result is in an error state.

Therefore, at this stage, the second control means P
Even if the power of the CON system circuit is turned on, an error state occurs immediately and the P_LOW mode is immediately returned. The same thing occurs even if the remote controller is input again for a short time, and it becomes impossible to stably shift to the P_ON mode.

Then, once the P_ON mode is entered,
That is, the operation clock of the microcomputer is high speed, the first control means 9 is ON, but immediately after that, P_LOW
Even when returning to the mode, the second control means 2 is turned off, but the operation clock of the microcomputer is kept at high speed and the first control means is kept on for a predetermined time (for example, about 5 seconds).

In this way, when the remote controller is again input for a short time, the remote controller code can be determined immediately, so that a predetermined operation can be performed without error determination.

Regarding the eighth embodiment of the present invention, in the case of a recording / reproducing device having a timer reservation function such as a VTR, when the second control means is turned off, the maximum power consumption reduction is aimed at. All the displays of the fluorescent display tube and so on will be erased, but at this time, in order to re-warn the user that the timer is reserved, the timer display blinks or lights for a predetermined time (for example, about 10 seconds). And so on.

[0041]

As described above, in the standby state power consumption control device according to the present invention, the power supply of the circuit for processing the input that cannot respond immediately to the user's operation request unless it is originally operated is turned off. It is possible to realize the low power consumption standby state in which the power consumption is further suppressed as compared with the normal standby state. Furthermore, it becomes possible to make a smooth transition in response to a transition request from the user to the operating state.

Further, in the standby state power consumption control device according to the present invention , the specifications are usually realized without increasing the power consumption so much even when the transition request from the A / D input terminal to the operating state is made. It becomes possible to do.

[0043]

[0044]

Further, in the standby state power consumption control device according to the present invention, it is possible to prevent a malfunction due to the remote controller being pushed down, etc., and to make a stable mode transition.

Further, in the standby state power consumption control device according to the present invention, it becomes possible to clearly inform the user whether or not there is a timer reservation before all the displays disappear.

[Brief description of drawings]

1 is a block diagram of an apparatus according to a first embodiment. FIG.

FIG. 2 is a flowchart showing a process of shifting to a low power consumption standby state based on the first embodiment.

FIG. 3 is a flowchart showing a process of a microcomputer at the time of shifting from a low power consumption standby state to a P_ON mode in the first embodiment.

FIG. 4 is a block diagram of a user request detection circuit according to a second embodiment.

FIG. 5 is a SW circuit for performing key input.

FIG. 6 is a flowchart showing a process of a microcomputer at the time of shifting from a low power consumption standby state to a P_ON mode when a user request detection circuit according to the second embodiment is provided.

FIG. 7 is a block diagram of an apparatus according to a sixth embodiment.

FIG. 8 is a timing chart in the sixth embodiment.

FIG. 9 is a flowchart showing a process of a microcomputer at the time of shifting from a low power consumption standby state to a P_ON mode in the sixth embodiment.

FIG. 10 is a block diagram of an apparatus based on a conventional example.

[Explanation of symbols]

1 AT power supply 2 microcomputer 3 PCON SW 4 PCON power supply 5 AT circuit 6 PCON circuit 7 Backup power supply 8 User request detection circuit 9 STBY SW 10 STBY power supply 11 STBY circuit 12 Cassette insertion status detection circuit 13 Mechanical position detection circuit 14 General-purpose input circuit 15 A / D converter 16-input detection circuit 17 Input processing circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 1/32 G06F 1/04

Claims (4)

(57) [Claims] 1. A first control means for controlling power supply of a first functional block, a second control means for controlling power supply of a second functional block, at least the first control means and the above. In a standby state power consumption control device comprising a third control means for controlling the second control means and an operation speed switching means for switching the operation speed of the third control means, a standby power supply is constantly supplied and externally supplied. identifying a first input means for determining the presence or absence of the input signal, the potential difference between the input signal from the external receiving power from the first functional block from
An A / D converter , the first control means and the second control means cut off the power supply to the first functional block and the second functional block, and switch the operating speed. When the input signal from the outside is detected by the first input means in the standby state where the operation speed of the third control means is controlled to be low by the means, the first control means Power is supplied to the first functional block, the operating speed switching means controls the operating speed of the third control means at a high speed, and the A / A is supplied with power from the first functional block.
When the D converter identifies the potential difference of the input signal from the outside and determines that it is valid, the second control unit supplies power to the second functional block, and when it determines that it is invalid, the standby state A standby state power consumption control device characterized by returning to a state. 2. A standby power consumption control device according to claim 1.
In this case, a microcomputer is used for the third control means, and the first input means is used.
The output means as an interrupt signal input terminal of the microcomputer
A standby power consumption control device characterized by: 3. The standby state according to claim 1 or 2.
In the power consumption control device, the second control means supplies power to the second functional block.
After shifting to the operating state where the
When returning to the state, the second control means supplies power to the second functional block.
The timing of shutting off the power source and the first control means
Note Timing of shutting off power to the first functional block and
And operation of the third control means by the operation speed switching means.
The timing control the speed to a low speed for a predetermined time timeline
Standby power consumption control device characterized by providing
Place 4. The standby power consumption control device according to claim 3.
In addition, a timer reservation means is provided, and the standby state is changed from the operating state.
If there is a timer reservation when transitioning to the
It is characterized by displaying a warning indicating that there is a predetermined time
Standby power consumption controller.