JP3406445B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] TECHNICAL FIELD The present invention relates to an active matrix
Display devices implemented with a liquid crystal display device
To achieve high definition display and multi-gradation display
Related to the technology. [0002] 2. Description of the Related Art FIG.
A typical prior art data bus line driving circuit 1 will be described.
Including the data bus line driving circuit 1 for
1 shows an electrical configuration of a live matrix type liquid crystal display device 2.
It is a block diagram. This liquid crystal display device 2 is generally
A display unit 4 in which a large number of picture elements 3 are arranged in a matrix,
The data bus line driving circuit 1 and a gate bus line
And a drive circuit 5. [0003] The data bus line driving circuit 1 includes a display
A plurality of m-channel data bus lines formed on the section 4
d1, d2,..., dm (when collectively referred to below,
d), predetermined sampling within one horizontal scanning cycle
The gradation corresponding to the luminance level of the image to be displayed for each period
It is for outputting a signal. Therefore, shift
A register 6 and an analog circuit provided for each channel.
Switches tr1, tr2, ..., trm (when collectively referred to as
Is indicated by a reference numeral tr) and a hold capacitor.
c1, c2,..., cm (when collectively referred to,
c). [0004] The shift register 6 is used to shift the horizontal of the video signal.
Start pulse sp created based on a synchronization signal etc.
Resetting in synchronization with
Clock input at each timing divided by channel number m
Signal ck, / ck (/ indicates an inverted signal)
In response to the signal of the analog switches tr1 to trm.
S11, s12,..., S
Output 1m. Each analog switch tr1 to tr
The source of m is a common video from a video signal source (not shown).
Signal is input, and this video signal
Sampled sequentially at switches tr1 to trm,
It is held by holding capacitors c1 to cm. Previous
Each data bus line d1 to dm is connected to each hold
The output voltages of the capacitors c1 to cm are applied as gradation signals.
Have been. The display unit 4 displays the data parallel to each other.
For the bus lines d1 to dm, a plurality of
The bus lines g1, g2,.
Are denoted by the reference numeral g) in parallel with each other.
Near the intersection of data bus line d and gate bus line g
The picture element 3 is formed, and thus the picture element 3 is
Are arranged in the shape of a circle. Each picture element 3 includes a thin film transistor 7 and a picture element
A pixel capacitor 8 composed of an electrode and a counter electrode (not shown);
It is provided with. Gate of thin film transistor 7
Is connected to the gate bus line g, and the source is
Data bus line d, and the drain
The quantity 8 is connected. [0007] The gate bus line driving circuit 5 has a shift register.
Each of the above gates is implemented every horizontal scanning period.
Scan signals are sequentially output to the bus lines g1 to gn.
You. Therefore, in each picture element 3, the scanning signal is output.
Thin film connected to gate bus line g
Transistor 7 is conducting, allowing horizontal scanning of video signals.
Accordingly, the data bus line driving circuit 1
The gradation signal output to the line d is written to the pixel capacitor 8
The contents are held until the next sampling timing.
Image display. In the above-mentioned conventional liquid crystal display device 2,
Displays high-definition television and computer images.
To increase the resolution of the displayed image and
There is a problem that it is not possible to respond to high definition
You. In other words, the high resolution and high definition
Is to increase the horizontal resolution, that is, the data bus line
It is necessary to increase several m. On the other hand, the data bus line
As the number m increases, the gradation signal to the pixel capacitor 8 is
There is a problem that writing failure occurs. For example, VGA
(Video Graffic Array) method, one horizontal scanning cycle
1H = 1 / (480 × 60) ≒ 30 μsec, and water
If the flat resolution is 640 lines, the analog switch tr
The time Ton1 that can be kept conducting is       Ton1 = 30 × 10^-6/ 640 = 46 (nsec) (1) Becomes On the other hand, when the gradation signal is
Strictly, that is, the time Ts required to write over 99%
1 requires at least 5 times the time constant,
The capacitance of the pixel capacitor 8 is set to 20 pF and the analog switch t
If the conduction resistance of r is 1 kΩ,       Ts1 = 20 × 10^-9× 1 × 10^Three× 5 = 100 (nsec) (2) Only needed. Therefore, Ts1> Ton1, and
When the analog switch tr is conducting during the sampling period
In the period Ton1, an accurate gradation signal is written into the pixel capacitor 8.
There is a problem that you can not. [0011] Another conventional method for solving such a problem is as follows.
The prior art is disclosed in Japanese Patent Publication No. 7-50389.
You. Referring to FIG. 12, the prior art data bus line
The drive circuit 11 will be described. Note that FIG.
The same reference numerals are used for the configuration corresponding to FIG.
The reference numerals are attached and the description is omitted. The data bus line driving circuit 11 has:
K-bit digital video signal from video signal source (not shown)
This digital video signal is
It is commonly provided to each cell of the road 12. Each cell
Is the sampling signal s1 from the shift register 6.
The video signal is latched in response to 1 to s1m. I
Therefore, the video signal is sequentially transmitted in response to the horizontal scanning.
For the next output sampling signals s11 to s1m
In response, the data is sequentially stored in each cell of the latch circuit 12.
go. The store contents of each cell of the latch circuit 12
Is output to each corresponding cell of the latch circuit 13. Previous
The latch circuit 13 responds to the horizontal synchronizing signal or the like.
Transfer signal is input, and the latch circuit 13
When the transfer signal is received, each cell of the latch circuit 12 is
Latch the stored contents of all at once and receive the next transfer signal.
Until it stops. The stored contents of the latch circuit 13 are compared.
Input to the circuit 14. Also, each cell of the comparison circuit 14 is
The same applies to all levels from the off-level to the on-level of the LCD.
And the k-bit gradation reference signal that periodically changes
No. is entered. Each cell of the comparison circuit 14 includes a latch circuit 13
When the gradation reference signal matches the video data from
The sampling signal is sent to the gate of the corresponding analog switch tr.
Derive the number. On the other hand, the source of each analog switch tr
The amplitude level is synchronized with the grayscale reference signal.
Analog gradation reference signals that change periodically
It is empowered. Therefore, from the analog switch tr
Each data bus line d via the hold capacitor c
Is a voltage corresponding to the luminance level of the video signal.
It is output as a tone signal. FIG. 13 shows a data bus line as described above.
FIG. 4 is a waveform chart for explaining an operation of the drive circuit 11. Floor
The key reference signal has a predetermined period, as shown in FIG.
For example, during one horizontal scanning period TH, a predetermined minimum level
Change to the maximum level 2^kThis is a gradation signal. Ma
The clock signal ck is shown in FIG.
Furthermore, it corresponds to the level of the gradation reference signal and
A gradation reference signal input in synchronization with the clock signal ck
13 (c) to 13 (f).
I will be. In FIG. 13, FIG.
FIG. 13H shows the transfer signal sp.
It is. Therefore, the start shown in FIG.
The gradation reference signal and the gradation reference signal are synchronized with a pulse.
13 (a) and FIG.
3 (c) to 3 (f). shift
The register 6 is provided with a start pulse shown in FIG.
sp and the clock signals ck and / ck,
Are sequentially shifted to output sampling signals s11 to s1m.
Strengthen. According to the sampling signals s11 to s1m,
In response, each cell of the latch circuit 12 receives the input video data.
The data is latched and output to the latch circuit 13. The 1 water
After the end of the horizontal scanning period TH, the transmission shown in FIG.
In response to the signal, the latch circuit 13 latches the video data.
Switch. Each cell of the comparison circuit 14 is shown in FIG.
As described above, the gradation reference signal being swept
In accordance with the video signal latched by the latch circuit 13
Is assigned to one gradation of the gradation reference signal
Analog switches tr1 to tr for the time Ton
m to output the sampling signals s21 to s2m, respectively.
You. As a result, the gradation reference signal is output from each analog switch.
At the time of the level corresponding to the times tr1 to trm,
And output to the data bus lines d1 to dm.
Going on. With this configuration, each data
The sampling period Ton2 of the tabus line d is equal to the 1
Horizontal scanning cycle TH and number of gradations 2^kAnd from     Ton2 = TH / 2^k                                        … (3) Becomes However, in practice, all of one horizontal scanning period TH
There is no video signal in the
The sampling period Ton2 is further shortened. As described above, the analog switch tr is activated.
And the capacitance of the pixel capacitor 8 is set to 20 pF.
Required to write the gradation reference signal to the pixel capacitor 8
Time Ts2 is 100 nsec, similarly to Ts1.
You. In contrast, in the case of the VGA method, one horizontal scan
The cycle TH is 30 μsec as described above,
If the number of gradations is 256,       Ton2 = 30 × 10^-6/ 256 = 117 (nsec) (4) And Ts2 <Ton2, and the VGA method is used.
Can be displayed with 256 gradations. Therefore, the data bus line shown in FIG.
In the driving circuit 1, one horizontal scanning period TH is applied to one line.
Time obtained by dividing by the number of pixels m
In contrast to the sampling time, this data bus
In the line driving circuit 11, the one horizontal scanning period TH
The time obtained by dividing by the key is called the sampling time.
High resolution and high definition.
You. [0021] However, the number of gradations
Is further increased to, for example, 512 gradations, T
on2 = 59 (nsec), and Ton2 <Ts2
Display is impossible. On the other hand, considering the mounting surface, FIG.
As shown, a data bus line formed in an integrated circuit is shown.
Drive circuit 21 is provided on the insulating substrate beside the display unit 22.
Be mounted. At this time, the insulating substrate is formed on the insulating substrate.
The data bus line d and the data bus line drive circuit 21
The terminal 23 is formed at the end of the data bus line d.
The terminal 23 is soldered to the contact pad 24
Are electrically connected by Contact pad 2
4 corresponds to the position shift of the data bus line drive circuit 21.
From the data bus line d,
Are also formed wide. Therefore, increase the resolution
Even if the width of the contact pad 24
It is said that it will be difficult to secure the predetermined interval
Problem. In order to solve such a problem, FIG.
A configuration as shown by 5 is conceivable. In this configuration,
The terminals of the data bus line drive circuit 25 are arranged in a staggered pattern
And the odd-numbered data bus lines d1, d3,
.. Correspond to the data bus line.
Are arranged on one side of the
. Corresponding to the data bus lines d2, d4,.
The tact pad 27 is connected to the data bus line drive circuit 25.
It is arranged on the other side. FIG. 16 is an enlarged view of the portion J in FIG.
As shown, the width is smaller than the width W1 of the contact pad 27.
W2 data bus line d
High resolution is achieved by routing between
I have. However, trying to further improve the resolution
Also, the distance W3 between the contact pads 26 is
Cannot be made smaller than the width W2 of the line d,
It is possible. Further, considering power consumption,
For example, an analog device comprising an NPN-type field-effect transistor
In the log switch tr, the gate-source voltage V
gs and the drain current Id, as shown in FIG.
Have such a relationship. That is, the drain current Id,
Therefore, in order to be able to supply the gradation signal sufficiently,
The potential Vg of the gate terminal is calculated from the potential Vs of the source terminal by
The threshold voltage Vth and the margin α required for conduction are required.
You. Therefore, the gradation reference signal and the sampling signal
Is represented by reference numerals β1 and β2 in FIG.
And the amplitude of the sampling signal Vs
Is given assuming that the maximum value of the amplitude of the gradation reference signal is Vmax.       Vs = Vmax + Vth + α (5) Only needed. That is, the sun to the analog switch tr
The pulling signals s21 to s2m pass through the data bus line d.
Must be higher than the voltage applied to the pixel capacitor 8 through the
It is necessary to lower the drive voltage to reduce power consumption.
There is also a problem that can not answer the demands. Further, the driving voltage is reduced to reduce power consumption.
In order to achieve the maximum value, the maximum value Vmax is reduced.
For example, if Vmax = 5V, the number of gradations is 512 as described above.
Sometimes, the gray scale voltage per gray scale is 10 mV or less.
Therefore, it becomes difficult to control the gray scale reference signal, and accurate gray scale
There is also a problem that it is difficult to generate a voltage. It is an object of the present invention to provide a multi-channel output line.
Multi-level output can be derived
Voltage output circuit operable with voltage and display using the same
It is to provide a device. [0029] Means for Solving the Problems A table according to the invention of claim 1
The display device is connected to each output line of a plurality of channels at predetermined intervals.
In addition, individually, a desired variable within a predetermined voltage range.
For display devices that use a voltage output circuit to output voltage
The predetermined period is one horizontal scanning period,
Using the voltage output circuit as a data bus line drive circuit
And two voltage output circuits are provided, and
Each of these two voltage output circuits has a video signal and
A gray scale reference signal, and the two voltage outputs
The output lines from the circuit have the same data
Connected to the bus line, and connected to the two voltage output circuits.
The output of one of the voltage output circuits is selectively gray scale.
Signal, and the two voltage output circuits
The gradation reference signal input to each of the roads has a gradation number of 2
In the case of j (j is a positive integer), one is for one horizontal scanning period.
From the gradation level “0” of the video data to the gradation of the video data
One signal that is a signal of j gradation that changes to level “j−1”
One for the one horizontal scanning periodSame timingso
From the gradation level “j” of the video data to the gradation level of the video data
The signal of the j gradation that changes to the bell "2j-1"Before
Of two j gradations indicating different gradation levels of the video data
Each sampling time in the signal is equal to one horizontal scanning cycle.
In the period, the gradation level of the video data from “0” to “2j−1”
Each sampling time required when changing to
Be twiceIt is characterized by. According to the above configuration,Two voltage output circuits
The output lines from
Connected between the two voltage output circuits.
The output of one of the voltage output circuits is selectively used as a gradation signal.
Is output as. Therefore, for example, the display medium is driven by alternating current.
The operation can improve reliability. Ma
In addition, the output voltage of about 1/2 of the predetermined voltage range is
Power supply can be used, power consumption by lower voltage
Data bus line drive
The withstand voltage of the driving circuit can be reduced, reducing the circuit area.
You can also.In addition, individual output lines for multiple channels
In order to output the desired variable voltage separately,
The sampling time of each output line is determined by the number of gradations
Each output such as a hold capacitor
While maintaining sufficient power to be supplied to the load connected to the line.
Corresponding to the resolution in the matrix display device.
The number of output lines can be increased. [0032] [0033] [0034] [0035] [0036] [0037] [0038] [0039] [0040] [0041] [0042] [0043] [0044] [0045] [0046] [0047] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described.
The following is a description based on FIGS.
You. FIG. 1 shows a voltage according to the first embodiment of the present invention.
The electric circuit of the data bus line driving circuit 31 which is an output circuit
FIG. 3 is a block diagram illustrating a configuration. This data bus line drive
The driving circuit 31 is an active matrix type liquid crystal display device.
Each picture element used for
The output lines of the multi-m
, Dm (collectively referred to as data bus lines D1, D2,..., Dm)
When you do, one horizontal
For each scanning cycle, it corresponds to the brightness level of the image to be displayed.
This is for outputting a gradation signal. This data bus line driving circuit 31 is
Generally, a shift register 32 serving as a scanning unit and a store
Latch circuits 33 and 34 as means for comparison and a ratio
Comparison circuit 35 and an analog switch as switching means.
TR1a, TR1b; TR2a, TR2b; ...; TR
ma, TRmb (when collectively referred to as TR,
), And holding capacitors C1, C2,..., Cm
(Collectively referred to as C below).
It is configured. The shift register 32 is provided for storing the video signal water.
Start pulse S created based on flat sync signal
Reset in synchronization with P
The clock input at each timing divided by the number of channels m
In response to the clock signals CK and / CK,
A sampling signal, which is a scanning signal, is sequentially transmitted to each cell of the channel.
.., S1m are output.
Good. A video signal (not shown) is supplied to the latch circuit 33.
If a k-bit digital video signal is input from the signal source,
This digital video signal is applied to each cell of the latch circuit 33.
Are commonly given to Each of the cells is
The sampling signals S11 to S1m from the register 32
In response, the video signal is latched. Therefore
Video signals are sequentially output in response to the horizontal scanning.
Latch corresponding to the sampling signals S11 to S1m.
The data is sequentially stored in each cell of the circuit 33. Store contents of each cell of the latch circuit 33
Is output to each corresponding cell of the latch circuit 34. Previous
The latch circuit 34 responds to the horizontal synchronization signal or the like.
Transfer signal is input, and the latch circuit 34
When the transfer signal is received, each cell of the latch circuit 33 is
Latch the stored contents of all at once and receive the next transfer signal.
Until it stops. The stored contents of the latch circuit 34 are compared.
Input to the circuit 35. Further, each cell of the comparison circuit 35 is
Are commonly used from the off-level of the liquid crystal, which is the display medium.
It corresponds to the on-level, changes periodically, and
The k-bit gradation reference signal is a reference data output
It is input from a counter (not shown) which is a means. Each cell of the comparison circuit 35 includes a latch circuit 34
When the gradation reference signal matches the video data from
The sampling signal is sent to the corresponding analog switch TR gate.
Derive the number. On the other hand, each analog switch TR1a, T
R2a,..., TRma (when collectively referred to as
TRa) via a reference signal line La
A voltage generating circuit (not shown) that is a reference signal output means.
And the amplitude level is synchronized with the gradation reference signal.
Analog is changing periodically in the first voltage range.
The gradation reference signal is commonly input. On the contrary,
Each of the analog switches TR1b, TR2b,..., TRmb
(Collectively referred to as TRb below)
Connected to the voltage generating circuit via a reference signal line Lb.
Therefore, the oscillation is performed in a second voltage range different from the first voltage range.
The gradation reference signal whose width level changes periodically is common
Has been entered. Output from each cell of the comparison circuit 35
The sampling signal is applied to the output of the latch circuit 34.
At the timing when the levels of the gradation reference signals match.
And one of the analog switches TRa and TRb
Output only to Therefore, the analog switch TRa
Or from TRb via a hold capacitor C
The data bus line D has a luminance level of the video signal.
The corresponding voltage is output as a gradation signal. FIG. 2 shows the unit cell in the comparison circuit 35.
FIG. 2 is a block diagram showing an electrical configuration of the
Now, the configuration related to the data bus line D1 is shown.
You. The cell 41 includes a comparator 42 and a pair of AND gates G.
a, Gb and an inversion buffer 43.
You. One input of the comparator 42 is connected to the latch
From the corresponding cell of the circuit 34, the lines F1, F2,.
K-1 bits of video data are input via (k-1)
Have been. The other input of the comparator 42 has a line
Through the counters f1, f2,..., F (k-1).
The gray scale reference signal is input from the data. The comparator 42 is
The period during which the video data and the gradation reference signal match each other
Only to the input of one of the AND gates Ga and Gb.
Output level. On the other hand, the latch circuit 34
Of the most significant bit input from the device via the line Fk
Data is input to the other input of the AND gate Ga.
And an AND gate via an inversion buffer 43
Gb is input to the other input. Therefore, the video data of the most significant bit is
When "1", the video data and the gradation reference signal
And from the AND gate Ga only during the period when
Sampling signal to the gate of analog switch TR1a
Is input, and the gray scale reference signal via the reference signal line La is supported.
And a gradation signal is supplied to the data bus line D1.
And output. In contrast, the top of the video data
When the order bit is “0”, the video data and the gradation
Only during the period when the quasi-signal matches, the AND gate Gb
To the gate of the analog switch TR1b.
Signal is input, and the gray scale reference signal via the reference signal line Lb is
It is sampled and the gray scale signal is sent to the data bus line D1
Is output as Thus, the first voltage range is swept.
The gray scale reference signal that has been swept in the second voltage range
One of the gray scale reference signals
And output. FIG. 3 shows a data bus line drive as described above.
FIG. 4 is a waveform diagram for explaining the operation of the driving circuit 31. this
In FIG. 3, when the number of gradations is 512, that is, k = 9
Is shown. Output to the reference signal lines La and Lb
The gray scale reference signals shown in FIG.
As shown by reference numerals γ1 and γ2 in FIG.
In a fixed horizontal scanning period TH, a predetermined minimum value
From the maximum value to the maximum value. Reference signal
In the gradation reference signal of signal line La, the minimum value is
Level "256" (video data: 10000000
0), and the maximum value is the level of the video data.
Corresponds to "511" (video data: 111111111)
are doing. Further, in the gradation reference signal of the reference signal line Lb,
The minimum value is the level "0" of the video data (video data:
0000000000), the maximum value is the level
Corresponds to "255" (video data: 0111111111)
are doing. Note that FIG. 3A and FIG.
The data bus line of the prior art shown in FIG.
Drive circuit 11 realizes the same 512-level gradation signal.
The change in the level in the case of the occurrence is indicated by reference numeral γ3. The clock signal CK is shown in FIG.
Indicated by Furthermore, the level of the gradation reference signal is
And is input in synchronization with the clock signal CK.
The waveform of each bit of the gradation reference signal is shown in FIGS.
As shown in FIG. The start pulse SP is
This is shown in FIG. Thus, the data bus according to the present invention
The line drive circuit 31 sets the reference signal line to two of La and Lb.
3 (a) and 3 (b).
As shown in the figure, the voltage range Vmax in which the gradation signal should change
Is divided into two voltage ranges Va and Vb.
Selective switching with analog switches TRa, TRb
To generate a gray scale signal. Therefore, the analog switch TR
The sampling time TON of the gradation reference signal is the same as that of FIG.
Sampling of the data bus line drive circuit 11 indicated by 2
It can be twice the time Ton. Therefore, the floor
Securing the same sampling time even if the key number is doubled
Can output the hold capacitor C
A sump that can be fully charged to the signal level
The resolution can be improved while securing the ring time.
You. Thus, the multi-level data bus line D
A tone signal can be output. In particular, such a data bus line driving circuit
The circuit is connected to the active element of the display
When the film is formed in a
The analog switch TR is made of polycrystalline silicon or the like.
And a drive circuit is formed on a single-crystal silicon substrate
Although the operating speed and driving capacity are lower than in the case,
By using the present invention, sufficient sampling time
Can be ensured, and it is
Can be. In the above embodiment, the number of reference signal lines is
Though it was two, the sump of analog switch TR
Select the number of rings that will provide the desired time for the ring time.
I just need. In this case, assuming that the number of reference signal lines is N,
The sampling time TON can be N times. The number of gradations is also limited to 512 gradations where k = 9.
Alternatively, more or less may be selected. On the spot
In this case, the most significant bit of the video data depends on the number of reference signal lines.
N analyzers per channel based on data from
It is possible to decide which of the log switches to select
Needless to say. That is, when N = 4
In this case, four
Is selected. FIG. 4 shows a second embodiment of the present invention.
It is as follows if it explains based on. FIG. 4 shows a liquid crystal according to a second embodiment of the present invention.
FIG. 2 is a front view illustrating a configuration of a display device 51. This liquid crystal display
The device 51 is based on the data bus line driving circuit 31 described above.
The reference signal lines are set to La and Lb by using
With the reference signal lines La and Lb, respectively.
Uses two data bus line drive circuits 31a and 31b
are doing. Data bus line drive circuits 31a, 31b
Is the display section where the active element for each picture element is formed
52 are arranged on both sides, respectively.
Output lines connected to a common data bus line D
Have been. The data bus line drive circuit 31a has
Analog switch in the data bus line drive circuit 31 of FIG.
Switch TRa, and a data bus
An analog switch TRb is provided in the line drive circuit 31b.
Have been killed. Remaining shift register 32, latch circuit
33, 34, etc. are provided in common. The data bus line driving circuit 31b
Are applied with the low-level power supply voltages Vee to Vss.
The data bus line driving circuit 31a has a high level
Bell-side power supply voltages Vss to Vcc are applied. Previous
The power supply voltages Vee to Vss and the power supply voltages Vss to Vc
c is created by the power supply circuit 53 from the input voltage Vcc.
Is done. Similarly, the voltages Vee to Vss and the voltage V
The gray scale reference signal changing in the range of ss to Vcc is shown in FIG.
In the above voltage generating circuit, from the input voltage Vcc,
Created. Generally, in a liquid crystal display device, the reliability of the liquid crystal is high.
The liquid crystal capacitance forming the display section 52 is positive or negative
It is necessary to drive AC with both polarities. Therefore, this liquid crystal
In the display device 52, the voltage Vss is set to 0, that is,
The ground level, the voltage Vcc is positive, and the voltage Vee
Negative polarity enables such AC drive
It works. Also, reduce the power supply voltage to approximately half
Power consumption can be reduced.
The circuit in the data bus line driving circuits 31a and 31b
Circuit voltage can be reduced, and the circuit area can be reduced.
Can also be. Incidentally, the configuration as shown in FIG.
The digital data bus shown in FIGS.
In addition to being performed in connection with the sling drive circuit, FIG.
Analog data bus line drive circuit indicated by 1
Can be used. FIG. 5 shows a third embodiment of the present invention.
This will be described below with reference to FIG. FIGS. 5 and 6 show a third embodiment of the present invention.
The mounting structure of the data bus line driving circuit 61 will be described.
FIG. 5 is a front view of the integrated circuit chip.
The data bus line driving circuit 61 is formed in a display section.
FIG. 6 shows a state of being mounted on an insulating substrate 62 to be
Insulation where data bus line drive circuit 61 is not mounted
Only the substrate 62 is shown. Both sides 6 of data bus line drive circuit 61
1a and 61b are connected to the data bus line D.
Terminals 63a and 63b are respectively extended. each
The terminals 63a and 63b are arranged at every arrangement pitch P1.
The terminal 63a on one side 61a side and the other
The terminal 63b on the side 61b side is not P1 / 2 with each other.
They are staggered and are arranged in a staggered manner. Correspondingly, the substrate 62 has
Contact pads 64a corresponding to the child 63a are in front of each other.
The terminals 63b are formed at every arrangement pitch P1.
The contact pad 64b corresponding to each of the arrangement pitches P1
Is formed. Also, the contact pad 64a
The contact pad 64b is shifted by P1 / 2 from each other.
Are arranged. It should be noted that in the present invention, FIG.
Thus, one of the contact pads 64a is an odd number
Are directly connected to the data bus lines D1, D3,.
While the other contact pad 64b is
Contact pads 64a, 64b and data bus line
A conductive layer different from the surface of the insulating substrate 62 on which the
Through the bypass wiring 65 formed at the even-numbered
Connected to data bus lines D2, D4, ...
It is. That is, the bypass wiring 65 is
When the edge substrate 62 is a single-layer substrate, the insulating substrate 62
The insulating substrate 62 is formed of a multi-layer substrate.
When formed, the contact pads 64a, 64
b and the surface on which the data bus line D is formed
Formed on different layer surfaces. This bypass wiring 65 and
The contact pad 64b is formed by the contact hole 66.
The wiring 6 for the bypass
5 and the data bus lines D2, D4,.
Are electrically connected by a screw 67. Therefore, the arrangement pins of data bus line D
Contact P2 with respect to the
Terminals 64a and 64b can be arranged.
a, 63b and contact pads 64a, 64b
Ensure sufficient soldering strength and
For mounting the integrated circuit chip of the dynamic circuit 61 on the insulating substrate 62
Data while ensuring that there is room for
The arrangement pitch P2 of the bus lines D can be reduced,
It is possible to cope with higher resolution. Incidentally, such a mounting structure is a liquid crystal display device.
The present invention can be widely applied not only to the location but also to other fields. FIG. 7 shows a fourth embodiment of the present invention.
It is as follows if it explains based on. FIG. 7 shows a liquid crystal according to a fourth embodiment of the present invention.
FIG. 2 is a block diagram illustrating an electrical configuration of a display device 71. note
It should be noted that in this liquid crystal display device 71, the display unit 72
And the mounting area 73 of the data bus line drive circuit
Analog switches Q1 and Q
2, ... (collectively referred to as Q below)
It is being. Each analog switch Q
Are provided corresponding to each data bus line D individually.
The data bus line D is connected to the output side.
Have been. The input side of the analog switch Q is
The odd-numbered analog switches Q1, Q3,.
The following even-numbered analog switches Q2 and Q4
Input lines that are paired and connected in common, and are output lines
Are connected to H12, H34,. The input lines H12, H34,.
The data bus line driving circuit mounted on the mounting area 73
Road terminals are individually connected. In addition,
At the control terminal of the log switch Q,
Are common to the control signal line CTL1
And the even-ranked analog switches Q2, Q4,
Are connected to the control signal line CTL2. In the liquid crystal display device 71, one horizontal scanning cycle
Period TH is divided into two and used.
The input lines H12, H34,...
The gray scale signal is updated and output every two. Corresponding to this
The control signal lines CTL1 and CTL2
In the first half of the horizontal scanning period TH, for example, the control signal line
When CTL1 is set to the high level, the analog
The switches Q1, Q3,.
During the latter half of TH, the control signal line CTL2 is at a high level.
Analog switches Q2, Q4,
Are conducted. With this configuration, the data
While maintaining the number of bus lines D, that is,
Output terminal of the data bus line drive circuit without
The number can be reduced by almost half. In this liquid crystal display device 71, two
The data bus line is shared by the data bus line drive circuit.
Although it was connected to the output terminal, the control signal line
By increasing the number, three or more data bus
It is important to note that the
Needless to say. The present invention also relates to a collection mounted on a substrate.
Circuits from integrated circuit chips to multiple output lines formed on the substrate
Widely used for configurations that periodically update and derive output
be able to. FIG. 8 shows a fifth embodiment of the present invention.
It is as follows if it explains based on. FIG. 8 shows a liquid crystal according to a fifth embodiment of the present invention.
FIG. 2 is a block diagram showing an electrical configuration of a display device 81. This
The liquid crystal display device 81 is similar to the liquid crystal display device 71 described above.
Corresponding parts have the same reference characters allotted.
Is omitted. It should be noted that this liquid crystal display device 81
Is between the display section 72 and the data bus line driving circuit.
Analog switches R1, R2, ... intervening
, And odd-numbered analog switches R1, R3,.
The analog switches R2, R4,...
That is, they are formed in different conductive types. That is,
For example, if the analog switches R1, R3,.
Formed by MOSFET (metal oxide semiconductor),
The analog switches R2, R4,... Are p-channel MOS
It is formed by FET. With this configuration, the analog
, And analog switches R2,
R4,... Operate complementary to common control signals
Therefore, the number of control signal lines CTL is reduced to one.
Can be. These analog switches R1, R3,
…; R2, R4,... Are TH / 2 periods as described above.
It is only necessary to perform ON / OFF operation every time, and therefore, relatively
Operation is possible even at low speeds.
Monolithic on an insulating substrate together with the resistor 82
Can be achieved. FIG. 9 shows a sixth embodiment of the present invention.
The following is a description based on FIG.
You. FIG. 9 shows a sixth embodiment of the present invention.
FIG. 3 is an electric circuit diagram for explaining a pulling circuit 91.
This sampling circuit 91 is, for example, an analog circuit shown in FIG.
Log switch TRa, TRb and hold capacitor
This corresponds to a sampling circuit composed of a capacitor C. However
In FIG. 9, the analog switch is one of TRa.
Of the reference signal. It should be noted that this sampling circuit 91
Then, the gate of the analog switch TRa has the AN
The sampling signal from the D gate Ga is a series capacitor
92 from the reference signal line La.
Key of the analog switch TRa to which the key reference signal is input.
A resistor 93 is interposed between the gate and the gate.
And The sampling signal is an analog switch
When conducting TRa, it becomes high level and cuts off.
Sometimes it is low level. Therefore, the potential of the gate is applied to the resistor 93.
Therefore, it is held almost equal to the source potential,
While the signal is low, the series capacitor 92
It is charged to that potential. Where the sampling signal
At the high level is Vth + α from FIG.
The sampling signal goes high.
Then, as shown in FIG.
Assuming that the level of the gradation reference signal is Vmax,
Means that Vth + α + Vmax is applied,
The log switch TRa becomes conductive. Therefore, in FIG.
The level Vs of the sampling signal shown in FIG.
Regardless of the level of the illumination signal, if Vth + α or more,
The analog switch TRa can be turned on. this
Can reduce the amplitude of the sampling signal.
Can generate a sampling signal for the comparing circuit 35 and the like.
Voltage can be reduced for
Reduce the voltage of the line drive circuit, that is, lower power consumption
Can be possible. Note that such a configuration is not suitable for a liquid crystal display device.
Not only for sampling of grayscale signals for
Can be [0095] The display device according to the first aspect of the present invention
The predetermined period is one horizontal scanning period as in
Voltage output circuit used as data bus line drive circuit
And two voltage output circuits are provided.
Each of these two voltage output circuits has a video signal and a floor
And the two voltage output circuits
The output line from the road is the data that the corresponding output line
Connected to a bus line and connected to the two voltage output circuits.
The output of one of the voltage output circuits is selectively gray scale.
Signal, and the two voltage output circuits
The gradation reference signal input to each of the roads has a gradation number of 2
In the case of j (j is a positive integer), one is for one horizontal scanning period.
From the gradation level “0” of the video data to the gradation of the video data
One signal that is a signal of j gradation that changes to level “j−1”
One for the one horizontal scanning periodSame timingso
From the gradation level “j” of the video data to the gradation level of the video data
The signal of the j gradation that changes to the bell "2j-1"Before
Of two j gradations indicating different gradation levels of the video data
Each sampling time in the signal is equal to one horizontal scanning cycle.
In the period, the gradation level of the video data from “0” to “2j−1”
Each sampling time required when changing to
It is twice as large as Therefore, for example, the display medium is driven by AC.
By doing so, the reliability can be improved. Ma
In addition, the output voltage of about 1/2 of the predetermined voltage range is
Power supply can be used, power consumption by lower voltage
Data bus line drive
The withstand voltage of the driving circuit can be reduced, reducing the circuit area.
You can also. The voltage output circuit is connected to the data bus line.
Increase the number of data bus lines.
Addition, that is, even if the resolution is improved,
The drop can be compensated.In addition, multiple channels
It is possible to output the desired variable voltage individually to each output line.
The sampling time of each output line
Is determined by the
Sufficiently supply power to the load connected to each output line
While maintaining the resolution of the matrix display device.
The corresponding number of output lines can be increased. [0097] [0098] [0099] [0100] [0101] [0102] [0103] [0104] Further, the display device according to the invention of claim 4 is as follows.
As above,In the above display device,The voltage output
The odd-numbered data bus lines adjacent to each other
Pair with even-numbered data bus lines
Switching elements provided with data bus lines respectively
Connected to the output line of the data bus line drive circuit via
The switching element is １ ／ of the predetermined period.
The grayscale signal output is driven to open and close complementarily in each period of. [0106] [0107] [0108] [0109] [0110]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an electrical configuration of a data bus line drive circuit which is a voltage output circuit according to a first embodiment of the present invention. FIG. 2 is a block diagram showing an electrical configuration per unit cell in a comparison circuit in the data bus line driving circuit. FIG. 3 is a waveform chart for explaining an operation of the data bus line driving circuit shown in FIG. 1; FIG. 4 is a front view illustrating a configuration of a liquid crystal display device according to a second embodiment of the present invention. FIG. 5 is a front view for explaining a mounting structure of a data bus line driving circuit according to a third embodiment of the present invention. 6 is a front view of only an insulating substrate for describing a mounting structure of the data bus line driving circuit shown in FIG. FIG. 7 is a block diagram illustrating an electrical configuration of a liquid crystal display device according to a fourth embodiment of the present invention. FIG. 8 is a block diagram illustrating an electrical configuration of a liquid crystal display device according to a fifth embodiment of the present invention. FIG. 9 is an electric circuit diagram for explaining a sampling circuit according to a sixth embodiment of the present invention. FIG. 10 is a waveform chart for explaining the operation of the sampling circuit shown in FIG. 9; FIG. 11 is a block diagram showing an electrical configuration of a liquid crystal display device including a typical conventional data bus line driving circuit. FIG. 12 is a block diagram showing an electrical configuration of another conventional data bus line driving circuit. FIG. 13 is a waveform chart for explaining the operation of the data bus line drive circuit shown in FIG. FIG. 14 is a front view of a liquid crystal display device for describing a mounting structure of still another conventional data bus line driving circuit. 15 is a front view of the liquid crystal display device for describing a mounting structure of the data bus line driving circuit shown in FIG. FIG. 16 is an enlarged front view showing a portion J in FIG. 15; FIG. 17 is a graph showing characteristics of an analog switch that outputs a gray scale signal to the data bus line. FIG. 18 is a waveform chart for explaining the operation of the sampling circuit including the analog switch. [Description of Signs] 31 Data bus line drive circuit (voltage output circuit) 31a Data bus line drive circuit (voltage output circuit) 31b Data bus line drive circuit (voltage output circuit) 32 Shift register (scanning means) 33 Latch circuit (store) Means) 34 latch circuit (store means) 35 comparison circuit (comparison means) 51 liquid crystal display device 52 display unit 53 power supply circuit 61 data bus line drive circuit 62 insulating substrate 63a terminal 63b terminal 64a contact pad 64b contact pad 65 bypass wiring 71 Liquid crystal display device 72 Display unit 73 Mounting area 81 Liquid crystal display device 91 Sampling circuit 92 Series capacitor 93 Resistor C Hold capacitor CTL Control signal line CTL1 Control signal line CTL2 Control signal line D Data bus line La Reference signal line Lb Reference signal line Analog switch R analog switch TR analog switch

Continuation of the front page (56) References JP-A-7-219484 (JP, A) JP-A-7-64511 (JP, A) JP-A-5-35218 (JP, A) JP-A-5-35200 (JP) , A) JP-A-64-86197 (JP, A) JP-A-5-173509 (JP, A) JP-A-61-223791 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) G09G 3/36 G02F 1/133

Claims (1)

(57) Claims 1. A voltage output circuit for outputting a desired variable voltage within a predetermined voltage range individually for each predetermined period to each output line of a plurality of channels. In the display device, the predetermined cycle is one horizontal scanning cycle, the voltage output circuit is used as a data bus line driving circuit, the two voltage output circuits are provided, and the two voltage output circuits are provided. , A video signal and a gradation reference signal are input to each of the two output lines from the two voltage output circuits, the corresponding output lines are connected to a common data bus line, Among the output circuits, the output of one of the voltage output circuits is selectively output as a gray scale signal, and the gray scale reference signal input to each of the two voltage output circuits is: When the number of gradations is 2j (j is a positive integer), one of them is the gradation level “0” of the video data during one horizontal scanning cycle.
From the image data to the gradation level “j−1” of the video data
The other is a signal of a gray scale that changes from a gray scale level “j” of video data to a gray scale level “2j−1” of video data at the same timing during the one horizontal scanning cycle. The respective sampling times of the two j-gradation signals indicating different gradation levels of the video data are from the gradation level “0” to “2j−” of the video data during the one horizontal scanning cycle.
The display device is characterized in that the sampling time is twice as long as each sampling time required when changing to "1".