JP3406123B2 - Specific pattern detection device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a specific pattern detecting device for detecting a specific pattern from input data, and is applicable to, for example, a digital subscriber circuit.

[0002]

2. Description of the Related Art In a digital transmission device such as a digital subscriber circuit, a specific pattern is often transmitted / received to / from an opposite device in order to establish synchronization or control a call sequence.

FIG. 2 is a block diagram showing the structure of a conventional specific pattern detecting apparatus for detecting a specific pattern from such input data, and FIG. 3 shows a detection procedure for each 1-bit input by the specific pattern detecting apparatus. It is a flowchart shown.

The input data is taken into the data receiving register 22, which is, for example, a shift register, right-shifted bit by bit in synchronization with the signal from the shifter 21 (S1),
The serial / parallel converted n-bit parallel data is applied to the comparison operation register 27 (S2).
The comparison calculation register 27 takes in an n-bit specific pattern (expected value) to be detected, which is stored in advance in the expected value register 28 (S3), performs a comparison calculation (collation) with the received data (S4), and outputs the result. Comparison result register 2
6 (S5).

When such a specific pattern detection device is applied to a synchronization establishment device, a synchronization establishment control unit (not shown) captures the contents of the comparison result register 26 and determines the synchronization establishment. Data reception counter 23 that counts up each shift by the shifter 21
To reset. In such a synchronization established state, every time the data reception counter 23 detects the shift of n times, the switch 25 is closed to store the input data in the data memory 24 every n bits.

[0006]

However, the conventional specific pattern detecting device has the following problems.

FIG. 2 shows a functional block diagram,
When such a specific pattern detection device is to be realized on a digital subscriber circuit, a digital signal processor (D
It is often realized by software such as SP) or CPU. As described above, in the conventional device realized by the DSP or the like, there are many processing steps for detecting the specific pattern, and a long time is required for detecting the specific pattern. Therefore, the processing capability of the DSP or the like can be fully exhibited. It was difficult.

For example, in the case of the predetermined procedure shown in FIG.
Each time one bit of input data is received, steps S1 to S1
Step S5 is repeated to determine whether the input data matches the specific pattern. Therefore, the number of processing steps until the specific pattern is detected becomes large.

However, since the processing in the DSP or the like generally operates by pipeline processing, it is not possible to proceed to the next processing until all the processing steps are completed, and the DS
It has been difficult to effectively use P and the like. The pipeline process is a process of simultaneously performing a plurality of processes within the execution time of one instruction, and is composed of three cycles of instruction reading, instruction analysis, and instruction execution. As described above, the DSP or the like has a branching process (although the branching step is not visible because FIG. 3 is described simply) even though a plurality of processes can be performed at the same time. , The process must be stopped. Therefore, there is a time when only a part of the functions such as the DSP is used.

There may be a case where a program is converted into firmware to detect a specific pattern. In the conventional detection method shown in the functional block diagram of FIG. 2, various registers are not provided as dedicated registers. ,
It is not preferable from the viewpoint of effective use of registers. Therefore, a general-purpose register is usually used, and this is set and used under conditions suitable for the processing content. Therefore, the time (overhead) to execute the processing step that sets the condition
Becomes necessary, which is a big problem in an environment where the processing time is severe.

Therefore, there is a demand for a specific pattern detection device having a simple detection processing procedure and requiring a small number of registers.

[0012]

To solve SUMMARY OF THE INVENTION The above object, the present invention provides a specific pattern detecting unit for detecting a specific pattern from the input data, in response to (1) the address number <br/>, next and address number basic data used as a reference when generating the read address numbers of the detection of a specific pattern, a memory storing a word consisting of a detection result flag indicating a non-detection, the address number basic data a read address number history given to the memory at the time of input of a particular pattern, a memory in which is a read address number history given to the memory at the time of non-input of a specific pattern in different, is (2) input data given for each shorter m bits than the length of a particular pattern of interest, and the input data of m bits, the address number And the data synthesized by the basic logic operations, and an address number generating means for generating a read <br/> and address number for reading the word from the memory, (3) lower the address number basic data m bit
Is fixed to a predetermined logical value .

[0013]

[Action] In certain pattern detection apparatus of the present invention, the address number generation means, each time the input data m bits is given, based on the address number basic data being output at that time and its m-bit input data By logical operation
Then, they are combined and given to the memory as a read address number , and the memory outputs the address number basic data and the detection result flag, which are 1-word components, and repeats the memory read operation. Here, the data stored in the memory is set as data that makes the address number history given to the memory when the specific pattern is input different from the address number history given to the memory when the specific pattern is not input, and the input of the specific pattern is performed. At the end, a detection result flag indicating detection is output. Also
Lower number m bits of address number basic data are given logical values
By fixing to, processing in the address number generation means
Is very simple.

As described above, the processing by the specific pattern detecting apparatus of the present invention is very simple, and even if it is configured by hardware, it is easy, and it is also suitable for configuring by software or firmware. .

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a specific pattern detecting device according to the present invention will be described below in detail with reference to the drawings. Here, FIG.
FIG. 3 is a block diagram showing the configuration of this embodiment.

The specific pattern detection device of this embodiment is installed in a digital subscriber circuit,
The transmitted AMI (Alternate Mark Inve) that takes one of "0", "1", and "-1".
region) signal sequence, the specific pattern “000100
"00" or "000-10000" is to be detected. However, in the specific pattern detection device of this embodiment, the three values of the AMI signal “0”, “1”, and “−1” are converted into “00”, “01”, and “11”, respectively.
A value signal is input. Therefore, the specific pattern detection device of this embodiment directly determines the specific pattern "0000000100000000" or "00" in the binary signal.
By detecting "0000100000000", the specific pattern "0001000" in the AMI signal is detected.
0 "or" 000-10000 "is detected.

In FIG. 1, the specific pattern detection apparatus of this embodiment comprises a data reception register 1, an address generator 2, a pattern change history memory 3, a memory output data register 4 and a judgment result register 5.

It should be noted that in FIG. 1, serial / serial data for receiving the input data Di and storing it as parallel data.
The parallel converter 6 and the data reception memory 7 are also described. The data described in the data receiving memory 7 can be used for reconfirmation of the specific pattern.

The data reception register 1, the memory output data register 4, and the judgment result register 5 are all set to 0 in the initial state.

The data reception register 1 receives the input data Di
Is received and held, and is output to the address generator 2 by m bits that are sufficiently shorter than the specific pattern length (16 bits in this case). In this embodiment, the data reception register 1 outputs the received input data Di by 2 bits each corresponding to one code of the AMI signal.

The address generator 2 is also supplied with n-bit (here, 6-bit) address basic data held in the memory output data register 4. The address generator 2 synthesizes 6-bit address basic data and 2-bit input data to generate a read address for the pattern change history memory 3, and supplies the read address to the pattern change history memory 3. In this example,
The address generator 2 sets the logical OR of each of the lower 2 bits of the 6-bit address basic data and the corresponding bit of the 2-bit input data to the lower 2 bits of the read address, and the upper 4 bits of the address basic data. A process of setting the upper 4 bits of the read address is performed to form a 6-bit read address.

As shown in FIG. 4, which will be described later, since the lower 2 bits of the address basic data are "00", the 2-bit input data appears as they are in the lower 2 bits of the read address.

The pattern change history memory 3 is, for example, RO
As shown in FIG. 4 which will be described later, 8-bit data is stored in correspondence with the address, and the upper 6 bits are the address basic data for the next read, The lower 2 bits are a detection result flag indicating whether or not a specific pattern is detected.

The memory output data register 4 holds the upper 6 bits of the 8-bit data read from the pattern change history memory 3, that is, the basic address data for the next read, and as described above, This address basic data is supplied to the address generator 2.

The judgment result register 5 holds the lower 2 bits of the 8-bit data read from the pattern change history memory 3, that is, a detection result flag indicating whether or not a specific pattern is detected. The detection result flag held in the determination result register 5 is referred to by a control unit or the like (not shown) that uses the detection result.

FIG. 4 shows the structure of the pattern change history memory 3. As described above, the pattern change history memory 3 stores 6-bit basic address data at the time of the next read and 2-bit detection result flag total 8-bit data corresponding to each address.

The structure of the pattern change history memory 3 shown in FIG. 4 is based on the following concept.

Two types of specific patterns "0000000100000000" (hereinafter,
Called the first specific pattern) or "000000110
000000 ”(hereinafter referred to as the second specific pattern)
Is 16 bits, and the pattern change history memory 3 is read for every 2 bits of the input data. Therefore, in order to detect the first or second specific pattern, 8 times (8 steps) of read operation are required. is necessary.

In each stage where the first specific pattern is input by 2 bits, addresses A11 to A1 unique to each stage are input.
8 is also assigned to each stage in which the second specific pattern is input by 2 bits.
~ A28 are assigned. Further, in order to clearly distinguish each step for the first and second specific patterns, the upper 4 bits of the address are given individual values at each step for the first and second specific patterns. Since the first 6 bits input in the first and second specific patterns are the same "000000", the unique addresses A11 to A13 and A21 to A23 in up to three stages are the same.

Naturally, it is not necessary to judge whether or not 2 bits of the specific pattern of the (x + 1) th stage are input unless the specific pattern has been followed up to the xth stage.

Therefore, the address basic data of the unique addresses A1x and A2x assigned to the specific pattern in the x stage is unique to the x + 1 stage when it is combined with the correct 2 bits of the x + 1 stage by the address generator 2. Data for address A1 (x + 1) and A2 (x + 1) is stored. On the other hand, even if a specific pattern is followed up to the x-1 stage, if the address input this time is not a unique address, it returns to the initial state. Address A11-A
In the address basic data of addresses other than 18 and A21 to A28, "000000" corresponding to the initial state (other values may be selected as the initial state value) is stored.

Final 8-step unique addresses A18 and A
Since the detection is completed, the address basic data at the time of the next read of 28 stores "000000" corresponding to the initial state so that the next detection can be executed.

Further, since the detection of the specific pattern has reached the 8-stage unique addresses A18 and A28, 2 bits indicating detection are stored in the detection result flags of the unique addresses A18 and A28. Two bits "00" indicating non-detection are stored in the detection result flags of addresses other than these (including unique addresses of other stages). Here, "01" is stored in the detection result flag of the unique address A18, "11" is stored in the detection result flag of the unique address A28, and the detected specific pattern is the first or second specific pattern. It is possible to identify which is which.

In FIG. 4, the address whose lower 2 bits are "10" is not prepared.
This is because the specific pattern obtained by converting the AMI signal in which the ternary signal is not converted to “10” is the detection target.

Hereinafter, the first specific pattern "000000"
The detection procedure of "01000000" will be described.

This first specific pattern "0000000"
When "100000000" is input, two bits "00", "00", "0" are received from the data reception register 1.
"0", "01", "00", "00", "00", "0"
"0" is sequentially output.

In the initial state, the memory output data register 4 stores "0000" as basic address data.
0 ”is stored, and when the first-stage 2-bit“ 00 ”is output from the data reception register 1, the address A 11“ 0
0000000 "is output, whereby the address basic data" 000100 "and the detection result flag" 00 "are output from the pattern change history memory 3 and stored in the memory output data register 4 and the determination result register 5, respectively.

In this state, the second stage 2 bits "00"
Is output from the data reception register 1, the address generator 2 outputs the address A12 “000100”, which causes the pattern change history memory 3 to output the address basic data “001000” and the detection result flag “00”. , And are stored in the memory output data register 4 and the judgment result register 5, respectively.

In this state, the second stage 2 bits "00"
Is output from the data reception register 1, the address generator 2 outputs the address A12 “001000”, which causes the pattern change history memory 3 to output the address basic data “001100” and the detection result flag “00”. , And are stored in the memory output data register 4 and the judgment result register 5, respectively.

From the data reception register 1, the following two bits “01”, “00”, “00”, “00”,
A similar memory read operation is repeated every time "00" is output, and the address from the address generator 2 is the address A13, A14, ..., A1 unique to the first specific pattern.
It changes in sequence at 8.

When the unique address A18 is input to the pattern change history memory 3, the address basic data "000000" and the detection result flag "01" are output and stored in the memory output data register 4 and the judgment result register 5, respectively. To be done.

A control unit (not shown), for example, captures the contents of the determination result register 5 every time 2 bits are output from the data reception register 1 and when it is determined that "01" is stored, Recognize that the first specific pattern has been received.

Second specific pattern "000000110"
The detection procedure when "0000000" is input is also the same. That is, two bits “00”, “00”, “00”, “01”, “00”, from the data reception register 1
Every time “00”, “00”, or “00” is output, the memory read operation similar to the above is repeated, and the address generator 2
, A28 are changed at the step addresses A21, A22, ..., A28 peculiar to the second specific pattern, and when the peculiar address A28 is input to the pattern change history memory 3, the basic address data "000000" is entered.
And a detection result flag “11” are output and stored in the memory output data register 4 and the determination result register 5, respectively, and a control unit (not shown) or the like catches that “11” is stored in the determination result register 5. When the second
Recognize that the specific pattern was received.

When the first and second specific patterns are not input, even if the same 2-bit input data arrives halfway, the unique address is input when 2-bit input data deviating from the pattern is input. A11-A1
8, an address different from A21 to A28 is output from the address generator 2 to return to the initial state, and the detection result flag output during this time is always "00" indicating non-detection.

According to the above-described embodiment, a specific pattern is obtained by a simple processing procedure in which the operation of reading the basic address data and the detection result flag from the pattern change history memory is repeated by the address obtained by synthesizing the input data and the basic address data. Can be detected. Also, the number of registers required is reduced.

As a result, even if the apparatus is constructed by hardware, it becomes simple. Further, even if it is constructed by software or firmware by a DSP or the like, since it is a simple process without branching, the capability of the DSP or the like can be exerted for other processes. Further, since the number of registers is small, even if a general-purpose register is used, it is possible to reduce the overhead such as the condition setting time for the register, and from this point as well, the capability of the DSP or the like can be exerted for other processing.

Although the memory output data register 4 is provided in the above embodiment, the basic address data may be directly output from the pattern change history memory 3 to the address generator 2.

The method of synthesizing the basic address data and the input data is not limited to that in the above embodiment. For example, a method of adding input data to the lower order of the address basic data or a logical operation different from that in the above embodiment may be used.

Further, it goes without saying that the number of bits of various data is not limited to that in the above embodiment.
In the above embodiment, since the AMI signal is detected from the signal converted into the binary signal, the data reception register 1 outputs it in units of 2 bits. However, it is generally output in units of 1 bit. It seems that there will be more things to do.

Furthermore, in the description of the above-mentioned embodiment, the pattern change history memory 3 has been described as being composed of, for example, a ROM, but it may be composed of a RAM. That is, data for pattern detection may be set in the pattern change history memory 3 from another device. In this case, the number of specific patterns that can be detected by the same specific pattern detection device increases.

The device that can use the specific pattern detection device of the present invention is not limited to the digital subscriber circuit, but can be widely applied to devices that require detection of the specific pattern.

Further, the detection result flag may be provided with a value indicating that the particular pattern is being detected (“10” in the example of FIG. 4). For example, the values related to the detection result flags of the unique addresses A11 to A17 and A21 to A27 in FIG. 4 may be set.

[0053]

As described above, according to the specific pattern detecting apparatus of the present invention, the processing is very simple, the hardware is simple, and it is suitable for the software and the firmware. Will be things.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment.

FIG. 2 is a conventional block diagram.

FIG. 3 is a flowchart showing a conventional specific pattern detection procedure.

FIG. 4 is a configuration diagram of a pattern change history memory according to the embodiment.

[Explanation of symbols]

1 ... Data reception register, 2 ... Address generator, 3 ... Pattern change history memory, 4 ... Memory output data register, 5 ... Judgment result register.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Chiyomi Nakano 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Yasushi Endo 1-7-12 Toranomon, Minato-ku, Tokyo Oki Denki Kogyo Co., Ltd. (72) Inventor Takama Kakinuma 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) Reference JP-A-1-302929 (JP, A) Japanese Patent Laid-Open No. 4-171579 (JP, A) Japanese Patent Laid-Open No. 3-147438 (JP, A) Japanese Patent Laid-Open No. 1-292920 (JP, A) Japanese Patent Laid-Open No. 62-169539 (JP, A) Japanese Patent Laid-Open No. 2-196535 (JP , A) JP-A-5-260035 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 7/08

Claims (3)

(57) [Claims] 1. A specific pattern detecting unit for detecting a specific pattern from the input data, corresponding to each address number, the next read address number
Address number basic data that is used as a reference when generating
A memory storing a word consisting of a detection result flag indicating detection or non-detection of a specific pattern, wherein the address number basic data is a read address number history given to the memory when the specific pattern is input, and a specific address. The memory, which makes the read address number history given to the memory different when the pattern is not input, and the input data are given for every m bits shorter than the length of the target specific pattern. Input data,
And the address number Basic data <br/> synthesized by the basic logical operations, and an address number generating means for generating a <br/> read address number for reading the word from the memory, the address number base The lower m bits of data are specified
A specific pattern detection device characterized by being fixed to a theoretical value . Wherein said memory is a unique address number is assigned to a specific pattern for each input stage divided into individual m-bit address number unique address number corresponding to a certain input stage
No. The basic data is stored unique address numbers become address number basic data corresponding to the next input stage when it is combined with the correct m-bit input data of the next input stage, the address number other than the unique address number the address number based <br/> the data, stored address numbers basic data <br/> data for the initial state, the unique address number of the detection result flag corresponding to the last input stage only, a value representing the detected The specific pattern detection device according to claim 1, wherein the specific pattern detection device is stored. 3. A unique address number corresponding to the final input stage
Address for the initial state as the issue of the address number Basic data
The specific pattern detection device according to claim 2, wherein basic number data is stored.