JP3349413B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a resistive element having a self-aligned silicide process and using an impurity diffusion layer.

[0002]

2. Description of the Related Art In a recent fine MOS transistor, a metal silicide film is formed on the surface of a source / drain region as a method for reducing the area of a source / drain diffusion region and keeping a contact resistance and a diffusion resistance low. A method is used. FIG. 3 is a cross-sectional view of a semiconductor device in a state where a metal silicide film is formed by using a conventional technique. In FIG. 3, 31 is a silicon substrate, 32 is an element isolation region, 33 is a gate oxide film, 34 is a gate electrode, 35 is a side wall, 36a is a low concentration source region, 36b is a low concentration drain region, and 37a is a high concentration source. The region, 37b is a high concentration drain region, and 38 is a metal silicide film.

Specifically, using polysilicon as a gate material, a sidewall 35 is provided on the side wall of a gate electrode 34 of a MOS transistor formed by a normal LSI process by using an insulating film, and a poly-silicon layer on the gate electrode 34 is formed. Silicon and source / drain regions 37a, 37b
A high melting point metal film such as titanium, tungsten, cobalt, nickel, etc. is formed on the entire surface in a state where the upper surface is exposed, and then heat of about 600 to 900 ° C. is applied for about 10 seconds to 1 minute to obtain silicon. The metal silicide film 38 is formed only on the portion where the metal and the metal are in contact, that is, only on the gate electrode 34 and the source / drain regions 37a and 37b, and thereafter, the unreacted high melting point metal film is removed by etching.

[0004] In this process, only the metal that is in contact with silicon reacts to form a silicide,
Since a metal silicide film can be formed only in a portion corresponding to a gate electrode and a source / drain region without going through a photolithography process, it is generally called a self-aligned silicide process.

[0005]

However, it is a feature of the self-aligned silicide process that metal silicide is formed only in the impurity diffusion region and the polysilicon wiring without adding a mask forming step as described above. In other words, unless a special mask is prepared and a method of suppressing the generation of metal silicide by a self-aligned silicide process is used, the diffusion portion and the polysilicon wiring are all reduced in resistance. .

Incidentally, in an actual LSI, there is a portion which needs to have an electric resistance by using a diffusion portion or a polysilicon thin film from a function intended for its operation. An example of such a circuit is a circuit for protecting noise near input / output pads of an LSI.

When such an LSI is manufactured by using a self-aligned silicide process and a resistive element is formed by using a diffusion portion or a polysilicon thin film,
Conventionally, measures have been taken to prevent the formation of a metal silicide film by a self-aligned silicide process, so that a portion serving as an electric resistance element is covered with an insulating film or the like which does not generate silicide by reacting with a resist or metal. Since a lithography process needs to be added, manufacturing a LSI using a self-aligned silicide process causes a problem that the cost is increased due to the complexity of the process.

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a high melting point metal film on a silicon substrate and / or a silicon layer; And a step of forming a metal silicide film, a method for forming a first oxide film and an oxidation-resistant film on a silicon substrate sequentially, and then forming a resistive element on a region serving as an element isolation region. A step of removing the oxidation-resistant film on a predetermined region of the region to be formed; and performing a heat treatment to form a second oxide film serving as an element isolation film and one or more third oxide films of a predetermined size. Forming, forming an impurity diffusion region in a region including the third oxide film, removing the first oxide film, forming a refractory metal film over the entire surface, and performing a heat treatment to at least perform the heat treatment. Impure It is characterized in that a step of forming a refractory metal silicide film in a portion where the diffusion region is exposed.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the present invention, after forming the element isolation film and the third oxide film, a gate electrode and a source made of polysilicon are formed in an element formation region of the silicon substrate. / Drain region,
Forming a MOS transistor in which the third oxide film is formed on the drain region;
An oxide film is formed and etched back to form a sidewall on the side wall of the gate electrode.
After the silicon substrate is exposed by removing the oxide film, a refractory metal film is formed on the entire surface, and heat treatment is performed to form a refractory metal film on the source / drain regions and the gate electrode upper surface where the silicon substrate is exposed. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a silicide film.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a view showing a process simulation in a local oxide film forming process for element isolation. 1 and 2, 1 and 21 are silicon substrates, 2 and 22 are silicon oxide films, 3, 23a and 23c,
23e is a silicon nitride film, 4, 24a, 24c, 24e
Is an element isolation film, 5 is a minute oxide film, 6 is a gate oxide film, 7
Is a gate electrode, 8 is a sidewall, 9a is a low-concentration drain region, 9b is a low-concentration source region, 10a is a high-concentration drain region, 10b is a high-concentration source region, 11 is a refractory metal film, and 12 is a metal silicide film. Show.

First, when fabricating an LSI combining MOS transistors, an element isolation film for isolating each transistor is required. At this time, as a structure generally used as an element isolation film, there is a local oxide film formed by a local oxidation method. According to this method, a thin film that does not allow oxygen to pass, such as SiN, is formed in advance on the entire wafer, the thin film is removed only in a portion corresponding to an element isolation portion, and oxidation is performed. An oxide film grows due to oxidation, and an element isolation region is formed.

The shape of the element isolation oxide film depends on the process conditions of the oxidation step, the difference in the thickness of the SiN thin film,
In the etching step for partially removing the iN thin film, the silicon substrate under the SiN substrate may be variously shaped depending on whether the silicon substrate is dug or not. This means that the film thickness is the thickest at the center and gradually decreases toward the end. The width of the thickest portion at the center of the element isolation portion is smaller than the width from which the SiN thin film has been removed before oxidation. This is because the oxidation is performed in a state where pressure is applied by the SiN thin film remaining on the left and right, so that the growth of the oxide film at the end portion is suppressed, or the oxygen necessary to convert Si into the oxide film is converted to the SiN thin film. Si through the oxide film exposed at the end
Since the required oxygen also spreads to the lower portion of the SiN thin film through the oxide film exposed at the edge of the SiN thin film, the oxygen concentration becomes relatively low near the edge and the required oxygen concentration becomes lower.
This is due to physical causes such as the progress of oxidation of Si being slower than the central portion of the removed portion of the N thin film.

In the diffusion region, there is no SiN thin film,
Below the oxidized portion, the diffusion resistance increases. Further, if the width of this portion is increased, the resistance value can be increased accordingly. Therefore, the resistance value can be adjusted by adjusting the width.

Considering the case where the width of the removed portion of the SiN thin film is reduced in the formation of the device isolation oxide film, if the width of the removed portion of the SiN thin film becomes smaller, the width of the device isolation formed naturally also decreases. However, if the width is further reduced, the oxide film thickness also decreases at the central portion of the element isolation portion. That is, by reducing the removed portion of the SiN thin film, a local oxide film having a small thickness as well as a width can be formed using the same oxidation process.

FIG. 2 shows the result of verification using the process simulation. 2 (a), 2 (c),
In FIG. 2E, an 18 nm SiO ₂ film 22 and a 25 nm SiN films 23a and 23 are formed on a silicon substrate 21.
After the formation of the SiN films 23a, 23b,
A part to be removed is formed in 3c. The width of the removed part is on the left (Fig. 2
(A)) is 1.0 μm, and the center (FIG. 2 (c)) is 0.1 μm.
μm, the right side (FIG. 2 (e)) is 0.05 μm. Thereafter, by performing an oxidation step, the local oxide films 24a, 24a
4c and 24e are formed. The maximum thickness of the local oxide film on the left side (FIG. 2B) is about 550 nm, while the maximum thickness of the local oxide film on the center (FIG. 2D) is about 160 n.
m, the thickness of the local oxide film on the right side (FIG. 2F) is about 90 n.
m.

The thickness of the oxide film when the entire wafer is oxidized using the same process without covering the surface with the SiN thin film is about 600 nm. d), the maximum thickness of the local oxide film in FIG.
92% and 27% respectively when oxidizing without N thin film
% And 15%. These film thicknesses are
By changing the width of the removed portion formed on the N thin film,
In addition to the example shown here, it is possible to obtain a local oxide film having a desired thickness. As a method of forming the removed portion of the SiN thin film, there is a method of simply forming the portion as shown in FIGS. 2A, 2C, and 2E. In this case,
It is conceivable that it is limited by the minimum processing size on the process. In addition, by using a method such as etching the SiN thin film at an angle or performing a process of forming a sidewall at the end of the SiN thin film, the SiN thin film is not necessarily limited to the minimum processing size. It is possible to form a removed part.

By using the above method, the local oxide film having a small thickness can be formed by adjusting the width of the removed portion of the SiN thin film. Then, in the subsequent transistor forming step, particularly in the ion implantation step for forming source / drain regions and the subsequent heat treatment step, the impurity concentration immediately below the local oxide film is lower than that of the source / drain regions, and The structure can be electrically connected. For example, when impurities are implanted in the shape shown in FIG. 2F under ion implantation conditions generally used for forming source / drain regions, the impurities can be introduced also to the lower portion of the oxide film.

When a metal silicide is formed using a self-aligned silicide process after the transistor is formed, no metal silicide is formed over the local oxide film, so that the metal silicide does not cover the entire impurity diffusion region. And a moderate diffusion resistance can be realized.

Hereinafter, the self-aligned silicide process will be described in more detail with reference to FIG.

First, after a silicon oxide film 2 and a silicon nitride film 3 are formed on a silicon substrate 1, a minute opening (eg, 0.05 μm wide) is formed in the silicon nitride film on the drain region.
m) are formed (FIG. 1A), and then a local oxide film and a minute oxide film 5 to be the element isolation films 4 are formed by an oxidation process (FIG. 1B).

In the present embodiment, the width of the minute opening is set to 0.05 μm, but the following factors can be considered as factors that determine the width of the minute opening.

First, the metal silicide on the drain region is not continuous. This is an object of the present invention, and for this purpose, the larger the width and height of the minute oxide film 5, the more advantageous. The formation of the minute oxide film 5 is an initial stage of the wafer process, and it is considered that the oxide film is reduced by etching or the like before the transistor is formed and the metal silicide formation step is performed. It is necessary to make the width and height of the minute oxide film 5 somewhat large in anticipation of this. This factor determines the lower limit of the width of the minute opening.

Second, the drain region under the minute oxide film 5 becomes a continuous diffusion region. For this purpose, it is most preferable to perform ion implantation (N ⁻ implantation (implantation for forming a low concentration impurity region in the case of the LDD structure) for forming the drain region) or source / drain implantation (in the case of the LDD structure). In this case, the ions pass through the fine oxide film 5 and reach the silicon substrate. However, after the source / drain implantation, there is always a heat treatment step for activating the impurity, and the impurity is diffused at that time, so that the impurity region is wider than immediately after the ion implantation. In consideration of this, it is possible to make the ions directly continuous by diffusion in the subsequent heat treatment even if the ions do not reach the silicon substrate after passing through the minute oxide film in the ion implantation immediately below the minute oxide film. This factor defines the upper limit of the width of the minute opening.

The width of the minute opening is determined mainly by taking the above factors into account. However, in practice, the amount of film reduction varies depending on the process conditions, and the impurity species (source / drain is Usually using arsenic,
The N ⁻ region may be arsenic or phosphorus. Phosphorus has a greater diffusion in the heat treatment than arsenic), and the width of the minute opening required depends on the heat treatment conditions for activation.

Next, after removing the silicon nitride film 3 and the silicon oxide film 2 under the silicon nitride film 3, a gate oxide film 6, an N-type polysilicon film are formed, and a gate electrode 7 is formed by patterning. N ^- ion implantation with low concentration drain region 9a, to form a lightly doped source region 10a, the deposition of the oxide film to form sidewalls 8 by etching back. Thereafter, a high-concentration drain region 9b and a high-concentration source region 10b are formed by arsenic implantation. Note that the present invention is not limited to the LDD structure.

In this embodiment, three openings are formed at equal intervals. However, since arsenic is not sufficiently implanted under the minute oxide film 5, the diffusion resistance in that portion is large. The effect can be expected sufficiently even with three or less.
The number also depends on the width of the drain region. To increase the resistance, the interval between the openings may be narrowed so that the fine oxide film 5 comes into contact after thermal oxidation. FIG. 1C is a cross-sectional view at the stage when the formation of the transistor is completed.

At this time, the source / drain regions 9b, 1
Normally, a thin film of an insulator such as an oxide film is attached to the upper surface of the gate electrode 7 or the gate electrode 7. Therefore, prior to forming a metal thin film for silicidation, the high-concentration drain region 9b, the high-concentration source region 10b, and the insulating film on the upper surface of the gate electrode 7 are removed so that the surfaces of silicon and polysilicon are exposed. To Patterning for this purpose is not necessary, and the oxide film is etched on the entire silicon substrate 1 until the oxide film covering the high-concentration drain region 9b and the high-concentration source region 10b is removed. Although the sidewalls 8 are formed between the high-concentration source region 10b and the gate electrode 7 and between the high-concentration drain region 9b and the gate electrode 7, this sidewall 8 may be slightly Even if there is loss, it is not completely removed.

Also, with respect to the minute oxide film 5 formed on the high-concentration drain region 9b, if the appropriate oxide film thickness is selected, the minute oxide film 5 can be prevented from being completely removed. Thereafter, a high-melting-point metal film 11 is formed for silicidation. Thereafter, by performing a heat treatment at a temperature of about 600 to 900 ° C. for about 10 seconds to about 1 minute, only the high melting point metal in contact with silicon reacts with silicon to form silicide, thereby forming a metal silicide film 12 ( FIG. 1 (e)).

Finally, only the high-melting-point metal film which has not been silicided is removed by etch-back to complete a transistor having a metal silicide film 12 formed in a necessary portion (FIG. 1 (f)). Here, a thick insulator called a sidewall 8 is provided between the metal silicide film 12 on the high-concentration source region 10b and the gate electrode 7 and between the metal silicide film 12 and the gate electrode 7 on the high-concentration drain region 9b. As a result, the metal silicide film 12 and the gate electrode 7 are electrically separated from each other,
There is no electrical short circuit between the drain region and the gate electrode.

Further, since the metal silicide film 12 separated by the minute local oxide film is formed on the drain region, the potential of the drain current is obtained by forming a contact electrode at the end of the drain and applying the potential. Thus, a necessary diffusion resistance is maintained between the drain portion near the gate electrode.

[0032]

As described in detail above, by using the present invention, a fine oxide film for preventing the formation of a metal silicide film formed in an impurity diffusion region is required for manufacturing an LSI. In the step of forming a local oxide film for isolation, the LS film can be formed at the same time.
A resistive element can be formed in I.

In particular, in a manufacturing process of a MOS transistor in which a metal silicide film is formed on the upper surface of a gate electrode and on a source / drain region by using a self-alignment process, the resistance of the resistance element on the drain region is increased without increasing the cost. You can control the value.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a simulation of a local oxide film size with respect to a size of an opening of a silicon nitride film in a local oxide film forming process for element isolation.

FIG. 3 is a cross-sectional view of a conventional semiconductor device having a metal silicide film formed thereon.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 21 Silicon substrate 2, 22 Silicon oxide film 3, 23a, 23c, 23e Silicon nitride film 4, 24a, 24c, 24e Element isolation film 5 Micro oxide film 6 Gate oxide film 7 Gate electrode 8 Side wall 9a Low concentration drain region 9b Low concentration source region 10a High concentration drain region 10b High concentration source region 11 Refractory metal film 12 Metal silicide film

Claims (2)

(57) [Claims] A method of manufacturing a semiconductor device, comprising: forming a high melting point metal film on a silicon substrate and / or a silicon layer; and reacting silicon with the high melting point metal film by heat treatment to form a metal silicide film. A step of sequentially forming a first oxide film and an oxidation-resistant film on a silicon substrate, and then removing the oxidation-resistant film on a region to be an element isolation region and a predetermined region in a region to be a resistance element Forming a second oxide film serving as an element isolation film and one or more third oxide films having a predetermined size by performing a heat treatment; and forming an impurity diffusion region in a region including the third oxide film. After the first oxide film is removed, a high-melting-point metal film is formed on the entire surface and heat-treated to form a high-melting-point metal silicide film at least in a portion where the impurity diffusion region is exposed. And having a degree, a method of manufacturing a semiconductor device. 2. After the device isolation film and the third oxide film are formed, a gate electrode and source / drain regions made of polysilicon are provided in a device formation region of the silicon substrate.
Forming a MOS transistor in which the third oxide film is formed on the drain region; forming a fourth oxide film on the entire surface; and etching back to form a sidewall on the side wall of the gate electrode. Then, after removing the first oxide film to expose the silicon substrate, a refractory metal film is formed on the entire surface, and then heat-treated to form a source / drain region and a gate where the silicon substrate is exposed. Forming a refractory metal silicide film on the upper surface of the electrode,
A method for manufacturing a semiconductor device according to claim 1.