JP3332180B2 - Image vertical enlargement device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image vertical enlargement device which can be used in a display device for non-interlaced display and which can arbitrarily enlarge an image in a vertical direction.

[0002]

2. Description of the Related Art In a variable scan display device, various horizontal frequencies (the number of scanning lines) are input.
Different scan line densities. In the case where a predetermined image is displayed on-screen, the resolution (dot size) can be kept constant by a PLL or the like in the horizontal direction, but the dot size in the vertical direction depends on the density of scanning lines. Will change. In an on-screen display in a conventional variable scan display device, an image which can be enlarged and displayed at an integral multiple is somewhat effective, and is effective against a change in the number of scanning lines which is an integral multiple. However, if the number of scanning lines is 4
Assuming that normal display can be performed with 00 lines, if the number of scanning lines reaches 600, the character size becomes ２. When the number of scanning lines becomes 800, the character size can be made twice as large as the number of scanning lines by expanding the character size twice. However, when the number of scanning lines is 600, the character size is doubled. , Character size is 400 scanning lines
This is 4/3 times the size of a book, and the character size increases.

Accordingly, in such a case, it is necessary to set the enlargement magnification by a magnification below the decimal point (2- ⁿ times: n is a positive integer). As an example of a conventional image vertical enlargement device that can set an enlargement magnification at a magnification below the decimal point,
There is one disclosed in JP-A-2-110497.

[0004]

However, the conventional vertical image enlargement device disclosed in the above publication is of the type in which overlapping scan line addresses are set in registers. Is required, and two scan lines can be overlapped, but 3
There is a problem that the book cannot be overlapped and the image cannot be vertically enlarged at an arbitrary magnification below the decimal point.
The present invention has been made in view of such problems,
It is an object of the present invention to provide an image vertical enlargement device capable of vertically enlarging an image at an arbitrary magnification below a decimal point.

[0005]

According to the present invention, there is provided a video RAM which receives a display clock and image data and outputs the image data as serial data according to the display clock. ,
A K-bit magnification data n having an integer part of K1 bits and a decimal part of K2 bits and a clock of 2 ^K2 times the horizontal synchronization signal are inputted, and a magnification for outputting a line count clock of 2 ^K2 / n times the horizontal synchronization signal A counter, a vertical blanking signal and the line count clock, and a line address counter for generating and outputting a line address for reading the image data written in the video RAM;
An address for writing the image data is input to M, and an address multiplexer for switching between the line address and the address for writing the image data and inputting to the video RAM is provided. To provide a vertical image enlargement device.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image vertical enlarging apparatus according to the present invention will
This will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of an image vertical enlarging apparatus of the present invention, FIG. 2 is a block diagram showing a specific configuration of a magnification counter 4 in FIG. 1, and FIG. 3 is an operation of the image vertical enlarging apparatus of the present invention. A diagram for explaining the
FIG. 4 is a diagram showing an enlargement operation by the image vertical enlargement device of the present invention.

In FIG. 1, a video R as an image memory
The AM 1 includes a serial access memory (SAM) 1a and a random access memory (RAM) 1b. A display clock is input to the SAM 1a of the video RAM 1, and image data for on-screen display is input to the RAM 1b from a CPU (not shown). On the other hand, magnification data n for setting an arbitrary magnification from the CPU is input to the magnification counter 4 and a clock 2 ^K2 fh of 2 ^K2 times (K2 is a positive integer) of the horizontal synchronization signal fh is input. . The magnification counter 4 generates a line count clock (2 ^K2 / n) fh obtained by dividing the clock 2 ^K2 fh by the magnification data n and supplies it to the line address counter 3 as described in detail later.

The line address counter 3 receives a vertical blanking signal VBLK. Then, the line address counter 3 is reset by a vertical blanking signal VBLK during a blanking period, sequentially generates line addresses during a non-blanking period, and inputs the line addresses to the address multiplexer (MPX) 2. The MPX 2 switches between an address for writing image data in the video RAM 1 input from the CPU and a line address input from the line address counter 3 and supplies the video RAM 1 to the video RAM 1.
The line address counter 3 updates the line address line by line with respect to one scan address in the display device, so that the image data (bit image) written in the RAM 1b of the video RAM 1 becomes SAM 1a line by line.
And converted to serial for output. SAM1
The data output from a is converted by the D / A converter 5 into D / A
A conversion is performed and displayed on a display device (not shown).

In the vertical image enlargement apparatus of the present invention having the above-described configuration, in order to enlarge the image data in the vertical direction, the line address output of the line address counter 3 overlaps the scan lines of the display device. In this case, the same display data is displayed on successive scan lines, and is enlarged in the vertical direction on the screen. The magnification counter 4 controls the count of the line address counter 3. The line address counter 3 counts the clock output from the magnification counter 4. Accordingly, the clock output from the magnification counter 4 is counted not only by an integer multiple but also by a fractional part, whereby the magnification can be controlled in units of 2 ⁻ⁿ times.

Here, the magnification counter 4 is configured as shown in FIG. 2, and operates as follows. Magnification counter 4
Comprises a counter 41, a comparator 42, a magnification setting register 43, a NAND circuit 44, and an inverter 45. 2, a counter 2 receives a clock 2 ^K2 fh that is 2 ^K2 times the horizontal synchronizing signal fh, and a magnification setting register 43 receives magnification data n. The comparator 42 compares the magnification data set in the magnification setting register 43 with the count of the clock 2 ^K2 fh by the counter 41, and outputs a line count clock (2 ^K2 / n) fh when the values match. The NAND circuit 44 is a NAN of a pulse obtained by inverting the clock 2 ^K2 fh by the inverter 45 and a line count clock (2 ^K2 / n) fh.
D is taken and a counter reset pulse (negative pulse) is input to the counter 41 to clear the counter 41. When the counter 41 is reset, the comparator 42 sets the line count clock (2 ^K2 / n) fh to “L (low)”.
Hold the line count clock (2 ^K2 / n) fh at “L” until the next matching condition is satisfied.

Further, as an example, the counter 41, the comparator 42, and the magnification setting register 43 have 8 bits, the lower 3 bits of the counter 41 and the magnification setting register 43 are a decimal part (K2 bit), and the upper 5 bits are an integer part (K1 bit). ). Here, since K2 is 3, it becomes 8 from 2 ³ , and 8 clocks are necessary for the counter 41 to count the integer value 1 in one horizontal period. Therefore, in this case, 8fh is given to the counter 41. Thus, the counter 41 counts eight times in one horizontal period. As shown in FIG. 2, the magnification setting register 43 stores “00001” in binary.
Assuming that a magnification of 100 ″ is set, the lower 3 bits are a decimal part, so that 1 + 2 ⁻¹ = 1.5, and 10
In other words, a magnification of 1.5 times is set.

Here, the lower 3 bits of the 8 bits are set as the decimal part, but the present invention is not limited to this, and the lower 4 bits may be set as the decimal part. In this case, 16f from 2 ⁴ = 16
h is given to the counter 41. That is, if the magnification data n is K bits, of which the upper K1 bit is an integer part and the lower K2 bit is a decimal part, the counter 41
Is supplied with a clock which is 2 ^K2 times the horizontal synchronizing signal fh.

In such a configuration, when a magnification of 1.5 is set, the line counter clock (2 ^K2 / n) fh is generated by the magnification counter 4 at a period of 1.5H, and 1.75. If the magnification is set to
Line count clock (2 ^K2 / n) fh is 1.75H
It is generated by the magnification counter 4 in a cycle. Therefore, the relationship between the scan line and the value of the line address counter 3 is 1.5 times and 1.75 times,
3A and 3B respectively.

Then, the addresses input to the video RAM 1 are increased while overlapping according to the designated magnification, so that the images displayed on the display device are 1.5 times magnification and 1.75 times magnification, respectively. FIG. 4 as an example
The image is enlarged and displayed as shown in (A) and (B). Accordingly, even in a display device having different scanning line densities, it is actually possible to display an on-screen display image with a substantially constant size. As described above, in the image vertical enlarging device of the present invention, the image data can be enlarged at an arbitrary magnification below the decimal point only by inputting the magnification data n to the magnification counter 4. In addition, according to the configuration of the present invention, since the setting can be set to 1 or less, the image data can be reduced by thinning out the line addresses.

[0015]

As described in detail above, the image vertical enlarging apparatus of the present invention can vertically enlarge an image at an arbitrary magnification below the decimal point only by inputting magnification data. Therefore, if the image vertical enlargement device of the present invention is used for a variable scan display device that performs non-interlaced display, an image can be displayed with a substantially constant size even if the density of scanning lines is different.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a magnification counter 4 in FIG.

FIG. 3 is a diagram for explaining the operation of the present invention.

FIG. 4 is a diagram showing an enlarging operation according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Video RAM 2 Address multiplexer 3 Line address counter 4 Magnification counter 5 D / A converter

Continuation of the front page (56) References JP-A-61-139163 (JP, A) JP-A-4-53347 (JP, A) JP-A-4-204999 (JP, A) JP-A-5-158464 (JP) , A) JP-A-6-161881 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5/00-5/40 G06T 3/40 H04N 1/393

Claims (1)

(57) [Claims] 1. A display clock and image data are input,
A video RAM that outputs the image data as serial data in accordance with the display clock; a K-bit magnification data n having an integer part of K1 bits and a decimal part of K2 bits; and a clock of 2 ^K2 times the horizontal synchronization signal, A magnification counter for outputting a line count clock of ^2K2 / n times the horizontal synchronizing signal; a vertical blanking signal and the line count clock being inputted; and a line address for reading the image data written in the video RAM. A line address counter for generating and outputting, the line address and an address for writing the image data in the video RAM are input, and switching between the line address and the address for writing the image data is performed by switching the video address. Address multiplexer to input to RAM And a vertical enlargement device for an image.