JP3328958B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device capable of suppressing generation of crystal defects.

[0002]

2. Description of the Related Art Sources of transistors in semiconductor devices
Ion implantation is performed to form a drain region or to lower the contact resistance of the contact hole after the formation of the contact hole.

For example, in order to form a source / drain region of a transistor portion, first, a gate electrode provided with an LDD structure having sidewalls made of SiO ₂ is formed. Then, As ⁺ , BF ₂ ⁺ , P ⁺ , B ⁺
Ion implantation at a high concentration of × 10 ^{15 to} 1 × 10 ¹⁶ / cm ² , followed by FA (Furnace Annealing) method or RTA (Rap
id Thermal Annealing)
The ion-implanted impurities are activated by thermal diffusion.
The annealing condition is, for example, 800 in the FA method.
゜ 900 ° C., 20-60 minutes. In the RTA method, the temperature is 900 to 1100 ° C. for about 10 seconds. In such a method, as shown in FIG. 10A, at the time of annealing, dislocations 50 are generated in the silicon substrate starting from the sidewall end portions 30 (hereinafter, such crystal defects are referred to as sidewall edge defects). Alternatively, dislocation loops 52 occur in the silicon substrate near the concentration peak of the implanted ions.

In FIG. 10A, reference numeral 1 denotes a silicon substrate, reference numeral 10 denotes an element isolation insulating region having a LOCOS structure, reference numeral 20 denotes a gate electrode, and reference numeral 2
2 is a gate oxide film, reference numeral 24 is a polysilicon layer, ginseng
Reference numeral 26 is a silicide layer, reference numeral 28 is a sidewall made of SiO ₂ , reference numeral 30 is an end portion of the sidewall, reference numeral 32 is a thermal oxide film formed on a source / drain formation region, and reference numeral 40 is a source.・ Drain area
Area .

The same applies to the contact hole. That is, high-concentration ions are implanted into the lower portion of the contact hole portion such as the source / drain region through the contact hole portion, and then the ion-implanted impurity is activated by thermal diffusion. In such a method, at the time of annealing, crystal defects 70 such as dislocation loops are generated in the silicon substrate region 64 below the contact hole 62 formed in the interlayer insulating film 62 made of, for example, SiO ₂ (FIG. 10B )reference).

On the other hand, a shallow trench is formed in a silicon substrate to form an element isolation region, and then an insulator such as SiO ₂ is buried in the shallow trench.
A technique for forming a so-called trench element isolation region is known. In a later step, ions are implanted into the silicon substrate 1 to form source / drain regions, and then an annealing process is performed. Then, as shown in FIG.
A crystal defect 80 is generated in the source / drain region 40 adjacent to. When an experiment was performed in which ion implantation was performed on the silicon substrate 1 in a state where SiO ₂ was not buried in the shallow trenches and then annealing treatment was performed, crystal defects were found to be the same in the source / drain regions adjacent to the trench element isolation regions. Therefore, it is considered that this phenomenon also contributes to the shape of the shallow trench. In the semiconductor device having the structure shown in FIG. 11, dislocation loops are generated in the silicon substrate near the sidewall edge defect and the concentration peak of the implanted ions. Illustration of crystal defects is omitted.

It is well known that the occurrence of these crystal defects can be suppressed to some extent by, for example, the following method. (A) Damage to the silicon substrate during ion implantation is reduced by lowering the energy of ion implantation. (B) The recovery annealing temperature after ion implantation is increased. (C) A part of the sidewall is removed by etching. (D) The knock-on phenomenon of oxygen is prevented. (E) The dose during ion implantation is reduced.

Performing the ion implantation in a plurality of times is as follows.
For example, it is known from JP-A-62-200723. The method described in this publication is characterized in that ion implantation at a small dose obtained by dividing a required dose is performed in a plurality of times, and heat treatment is performed immediately after each of the plurality of times of ion implantation. And Total dose is 10 ¹⁴
/ Cm ² order.
0 ° C., time 20 to 40 minutes, and the ion species used is B
⁺ . In this method, the generation of crystal defects is suppressed by performing ion implantation at a small dose obtained by dividing the required dose in a plurality of times. Heat treatment is
High temperature and long time.

[0009]

The above-described method for lowering the energy of ion implantation has a problem that the sheet resistance of the diffusion layer increases. In addition, it becomes more difficult to increase the ion current as the ion acceleration energy becomes lower, and as a result, there is a problem that the throughput is reduced. Further, since the concentration of the impurity implanted into the silicon substrate is reduced, the driving capability of the transistor is reduced.

The method of increasing the temperature of the recovery annealing after the ion implantation has a problem that the junction depth in the source / drain region becomes deep due to thermal diffusion, and as a result, it is impossible to cope with miniaturization of a semiconductor device. Reducing the temperature of the recovery anneal to avoid this problem causes an increase in the residual rate of crystal defects, or a decrease in the activation rate of the ion-implanted impurities. As a result, the junction leakage current increases. Connect.

[0011] If the annealing treatment is performed in the presence of the stress caused by the edge of the sidewall, a crystal defect occurs near the edge of the sidewall. Therefore, if a part of the sidewall is removed by etching, the stress due to the sidewall end can be removed, and as a result, the generation of crystal defects near the sidewall end can be prevented. However, the method of removing a part of the sidewall by etching is not effective in preventing the generation of secondary defects (dislocation loop) due to ion implantation.

Normally, ion implantation for forming source / drain regions is performed by using a Si substrate formed on the surface of a silicon substrate.
This is performed through an O ₂ film. At the time of ion implantation, a phenomenon in which O ₂ in the SiO ₂ film collides with ions and enters the silicon substrate is called a knock-on phenomenon of oxygen. This phenomenon also causes crystal defects. This knock-on phenomenon of oxygen can be prevented by using a silicon nitride through film. However, a method of forming an extremely thin (about 10 nm) silicon nitride film under accurate control is not known, and therefore, this method also has a problem that it is difficult to cope with miniaturization of a semiconductor device.

In the method of reducing the dose at the time of ion implantation, a sufficient amount of impurities cannot be introduced into the silicon substrate, resulting in an increase in the sheet resistance of the diffusion layer and a decrease in the driving capability of the transistor.

In the ion implantation method disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 62-72323, the heat treatment temperature is too high and the junction depth in the source / drain region becomes deep due to thermal diffusion. There is a problem that can not cope with. In addition, a single dose amount is 10 ¹⁴ / c.
Since m is ² orders, the total dose to the 10 ¹⁵ / cm ² order, must be performed ion implantation corresponding number is not practical. Further, when an attempt is made to obtain a total dose of the order of 10 ¹⁵ / cm ² by about two or three ion implantations, the dose per ion implantation becomes large, and crystal defects are generated by the ion implantation. However, such crystal defects cannot be removed.
There is no technical idea that crystal defects generated in the previous ion implantation step are removed in the subsequent ion implantation step.

As the cell size of a semiconductor memory decreases, the introduction of a higher concentration of impurities is required. The reason is,
This is because the amount of charge that must be stored per memory cell does not change, but the area of the memory cell must be surely reduced.

In order to solve the above-mentioned problems, the temperature in the steps from the ion implantation of the impurity to the activation process can be kept as low as possible, and moreover, the impurity at a higher concentration can be introduced into the silicon substrate. There is also a need for an ion implantation method that does not cause crystal defects in a silicon substrate.

Accordingly, it is an object of the present invention to effectively prevent crystal defects caused by ion implantation, sufficiently cope with miniaturization of a semiconductor device, without lowering the throughput, and reducing the temperature of the entire process. An object of the present invention is to provide a method for manufacturing a semiconductor device, which can be suppressed as low as possible.

[0018]

The above objects are achieved by (a) a first ion implantation step of implanting impurities into a silicon substrate and (b) a first annealing step of annealing at a temperature of 600 to 800 ° C. A second ion implantation step of ion-implanting an impurity into a region of the silicon substrate which has been ion-implanted in the first ion implantation step;
And a second annealing step of performing short-time annealing.

The second annealing step is desirably performed by the RTA method. The annealing conditions are 900 to 11
It is desirable that the temperature be 00 ° C and 1 to 60 seconds.

In the first preferred embodiment of the method of the present invention, it is preferable to select the ion implantation conditions in the second ion implantation step as follows. That is, (a) the depth D ₂₀ of the amorphized region formed in the silicon substrate by the second ion implantation step is equal to the depth D _{10 of} the amorphized region formed by the first ion implantation step. 1 (A) and (C) of FIG. 1 and (b) the depth D _{20 of the} region to be amorphized formed in the silicon substrate by the second ion implantation step is equal to the first depth. deeper than the depth D ₁₁ of the crystal defect region formed by the annealing process (FIG. 1 (B) and (C)
reference).

In the second preferred embodiment of the method of the present invention, it is preferable to select the ion implantation conditions in the second ion implantation step as follows. In other words, the second region is formed such that the depth of the amorphized region formed in the silicon substrate by the second ion implantation process is approximately the same as or shallower than the depth of the amorphized region formed by the first ion implantation process. An ion implantation condition in the ion implantation step is selected. More specifically, the depth of the amorphized region formed in the silicon substrate by the second ion implantation process is about the same as the depth of the amorphized region formed by the first ion implantation process to about 1.3 times. The ion implantation conditions in the second ion implantation step are selected so as to be deep or shallow to about 0.4 times.

[0022] This may for example be achieved ion acceleration energy in the second ion implantation step, 50 to 130% of the ion acceleration energy in the first ion implantation step, more preferably by 50 to 100% Can be. Alternatively, it can be achieved by setting the ion dose in the second ion implantation step to 20 to 100% of the ion dose in the first ion implantation step.

In the method of the present invention, in the second ion implantation step, As ions, P ions, and BF ₂ ions can be used, but electrically neutral ions such as Si ions are implanted. Can also.

It is desirable that the first ion implantation step, the first annealing step, and the second ion implantation step are continuously performed so that no interlayer film or the like is formed on the surface of the silicon substrate. The reason is that, when the interlayer film is formed, the ion implantation region at the time of the first ion implantation
This is because the ion implantation region at the time of the ion implantation step does not match.

In the method of the present invention, the first ion implantation step can be divided into a plurality of ion implantation steps.
In this case, a first annealing step is performed after each ion implantation step. When the first ion implantation step is divided into a plurality of times as described above, in the above-described preferred first embodiment, the depth D _{10 of} the amorphized region formed in the first ion implantation step is equal to the depth D ₁₀ . refers to D ₁₀ at the completion of the first ion implantation process. Further, the depth D ₁₁ of the formed crystal defect region in the first annealing step, refer to D ₁₁ at the completion of the first ion implantation process.

Also in the second preferred embodiment, the first ion implantation step can be divided into a plurality of ion implantation steps. In this case, a first annealing step is performed after each ion implantation step. In this case, the ion acceleration energy in the first ion implantation step is the maximum ion during a plurality of ion implantations in the first ion implantation step.
It means acceleration energy . Then, the ion acceleration energy in a certain ion implantation, 50 to 130% of the ion acceleration energy in the previous ion implantation, and more preferably it is desirable to 50-100%. Alternatively, the ion dose in the first ion implantation step means the maximum ion dose during a plurality of times of ion implantation in the first ion implantation step. It is desirable that the ion dose in a certain ion implantation be 20 to 100% of the ion dose in the previous ion implantation.

In a second preferred embodiment, for example, A is used as a dopant in the first ion implantation step.
When s ⁺ , BF ₂ ⁺ , and P ⁺ are used, the same dopant as that used in the first ion implantation step or Si ⁺ is used as the dopant used in the second ion implantation step. It is desirable to do. The ion dose in each of the first and second ion implantation steps is preferably 1 × 10 ¹⁵ / cm ² or more.
When dividing the first ion implantation step into a plurality of ion implantation steps, the ion dose amount at each ion implantation is set to 1
It is preferably at least 10 ¹⁵ / cm ² .

In the second preferred embodiment, the ion species implanted in the first ion implantation step and the second ion implantation step can be As ⁺ . Ion accelerating energy of the second ion implantation step is 50 to 130% of the ion acceleration energy in the first ion implantation step, and more preferably from 50 to 100%. More preferably, the total As ion dose is 2 × 1
0 ¹⁵ / cm ² or more, and the As ion dose in the second ion implantation step is 1 × 10 ¹⁵ / cm ² or more. Also in this aspect, the first ion implantation step can be divided into a plurality of ion implantation steps, and the first annealing step can be performed after each ion implantation step. In this case, the ion acceleration energy in the first ion implantation step
“-” Means the maximum ion acceleration energy during a plurality of ion implantations in the first ion implantation step. Then, the ion acceleration energy in a certain ion implantation is
50 of ion acceleration energy in previous ion implantation
To 130%, more preferably 50 to 100%. In addition, the second and subsequent As ion doses in the first ion implantation step are set to 1 × 10 ¹⁵ / cm ²
It is desirable to make the above.

[0029]

According to the present invention, the high-concentration ion-implanted region which has been made amorphous by the first ion-implantation step is solid-phase grown in the first annealing step at a low temperature to recover the crystallinity. At the time of this first annealing step, a crystal defect region occurs in the silicon substrate depending on the conditions of the first ion implantation. However, by performing the second ion implantation, such a crystal defect region is destroyed or removed.
Next, activation of impurities and recovery of crystallinity can be performed by a second annealing step of performing high-temperature, short-time annealing. As a result, generation of crystal defects in the semiconductor device can be effectively suppressed.

The first annealing step is performed between 600 and 80 so that the diffusion depth does not change in the first annealing step.
It must be performed at a temperature of 0 ° C. If the temperature exceeds 800 ° C., the diffusion depth becomes deep. If the temperature is less than 600 ° C,
The recovery of the crystallinity by solid phase growth of the amorphized high-concentration ion-implanted region is not sufficient.

It is important that the temperature of the second annealing step is higher than the temperature of the first annealing step. This is because it is desirable to activate the impurities in a later step. In order to keep the diffusion depth unchanged, it is necessary to perform annealing for a short time.

In the method of the present invention, if electrically neutral ions are used in the second ion implantation step,
Resist treatment in the ion implantation process of
The ion implantation may be performed only once on the entire surface of the wafer, and the process can be simplified.

That is, impurities such as As ⁺ , P ⁺ , BF ₂ ⁺ , and B ⁺ have a difference in p-type and n-type conductivity. Therefore, resist treatment must be performed on the source / drain regions for each conductivity type to implant these ions. Therefore, when ion species having p-type and n-type conductivity are used in the second ion implantation step,
Times of resist processing and ion implantation must be performed.

On the other hand, when electrically neutral ions, for example, Si.sup. ⁺ Are implanted in the second ion implantation step, there is no need to perform two ion implantations, and the entire surface of the wafer can be ion implanted. Therefore, no resist treatment is required, and the process can be simplified. Furthermore, when electrically neutral ions are implanted, there is little possibility of fluctuating the junction depth when activated in the second annealing step due to lack of conductivity. Therefore, there is an advantage that the degree of freedom of implantation energy (acceleration voltage) and dose is large.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The principle of the method of manufacturing a semiconductor device according to the present invention will be described first with reference to FIGS. 1 to 4, and then a specific example of the method of manufacturing a semiconductor device according to the present invention will be described.

(Principle of the Present Invention) The semiconductor device manufacturing method of the present invention is applied to the manufacture of a semiconductor device having a 0.5 μm rule. FIG. 2 is a schematic partial cross-sectional view of a semiconductor element used for manufacturing a semiconductor device. Gate electrode 20 of semiconductor element
Has an LDD structure. The thickness of the element isolation insulating region 10 having the LOCOS structure was 290 nm. Gate electrode 20 is formed of a polycide structure made of WSi / phosphorus (P) -doped polysilicon. The thickness of each of the WSi layer 26 and the phosphorus-doped polysilicon layer 24 was 100 nm. The thickness of the gate oxide film 22 is 11 nm. LD
The spacer in the D structure was constituted by a sidewall 28 made of SiO ₂ . A 10-nm thermal oxide film 32 is formed on the surface of the silicon substrate serving as the source / drain regions.

Using this semiconductor device, a first ion implantation step was performed through the thermal oxide film 32. In the first ion implantation step, the implantation dose of As ⁺ is fixed (5 ×
10 ¹⁵ / cm ² ), and the acceleration energy was changed from 20 keV to 50 keV. Thereafter, a first annealing step was performed by the FA method. Annealing conditions were 800 ° C. for 30 minutes.

The depth of the amorphized region 100 of the silicon substrate formed by the first ion implantation step (hereinafter, also referred to as a first damage layer depth) D ₁₀ (FIG. 1) (A), and the depth of a sidewall edge defect 50 generated in the first annealing step (hereinafter, also referred to as a first defect layer depth) D ₁₁ (FIG. 1B).
(See Reference). The result is shown in FIG. These depths increase as the implantation energy (acceleration voltage) during ion implantation increases. As apparent from FIG. 3, the first damaged layer depth D ₁₀ represent respectively the particle diameters also about three times the first defect layer depth D _11.

If an amorphous region 10 of the silicon substrate formed in the second ion implantation step
2 (hereinafter also referred to as the second damage layer depth) D
₂₀ (shown in FIG. 1 (C) see) is, if deeper than the first defective layer depth D _11, can be removed crystal defects generated in the first annealing step by the second ion implantation.

[0040] Moreover, if the second damaged layer depth D ₂₀ is sufficiently shallower than the first damaged layer depth D _10, it is possible to reduce or eliminate crystal defects generated in the second annealing step (Fig. 1 (D)). This is because, as is clear from FIG. 3, the shallower the depth of the amorphized region of the silicon substrate formed by ion implantation, the smaller the depth of crystal defects generated in the annealing process. Because.

Summarizing the above depth relationship, D ₁₀ > D ₂₀ ≧ The D _11. If the conditions for the second ion implantation are determined so as to satisfy such conditions, it is possible to suppress the occurrence of crystal defects in the silicon substrate.

Based on the above findings, the conditions of the ion implantation in the first ion implantation step and the second ion implantation step were examined in more detail as follows, and D ₁₀ = D
Even in the case of ₂₀ or D ₁₀ <D _20, was found to be effective in suppressing the crystal defects in the semiconductor device.

That is, the first ion implantation step was performed through the thermal oxide film 32 using the semiconductor device having the structure shown in FIG. In the first ion implantation step, As ⁺
Implantation dose of 5 × 10 ¹⁵ / cm ² and acceleration energy
The energy was set to 40 keV. Thereafter, a first annealing step was performed by the FA method. 800 ° C, 3
0 minutes.

An amorphous region of the silicon substrate formed by the first ion implantation of the sample thus obtained (hereinafter also referred to as a first amorphous region)
When the boundary portion between 110 and a region 110A of the silicon substrate that was not amorphized (hereinafter also referred to as a crystal region) 110A was examined in detail, as shown in a schematic partial cross-sectional view in FIG. It was found that interstitial Si was ejected from the first amorphized region 110 to the crystal region 110A. In FIG. 4A, the interstitial Si is indicated by black dots. Then, by performing the first annealing step, as shown in a schematic partial cross-sectional view of FIG. It was found that a crystal defect, which is a type of dislocation, was formed. In FIG. 4B, the interstitial type dislocations are indicated by crosses. It is considered that this interstitial type dislocation located at a position where the depth of the first amorphized region is shallow causes sidewall edge defects and the like.

[0045] In the second ion implantation step, the implantation dose of As ⁺ and 3 × 10 ¹⁵ / cm ^2, an acceleration energy
Chromatography was used as a 40keV. That is, the ion acceleration energy in the second ion implantation process was the same as the ion acceleration energy in the first ion implantation process. afterwards,
The second annealing step was performed by the RTA method. The annealing condition was 1050 ° C. for 10 seconds.

The sample thus obtained has an amorphous region (hereinafter, also referred to as a second amorphous region) of the silicon substrate formed by the second ion implantation.
When the boundary portion between the silicon substrate 120 and the non-amorphized silicon substrate region (crystal region) 120A was examined in detail, as shown in a schematic cross-sectional view in FIG.
It was found that interstitial Si protruded from the amorphized region 120 to the crystal region 120A was small, and many vacancy-type defects were formed in the second amorphized region 120. In FIG. 4C, vacancy-type defects are indicated by white circles.

After the second annealing step, the crystal region 120A
, Crystal defects had disappeared. This is the crystal region 120
It is considered that interstitial Si existing in A and vacancy-type defects formed in second amorphized region 120 interact with each other, and interstitial Si disappears from crystal region 120A.

Example 1 A semiconductor device was manufactured based on the method of the present invention using the semiconductor element shown in FIG. The fabrication conditions are as follows. First ion implantation step is performed through the thermal oxide film 32. Ion species used As ⁺ acceleration energy 20 keV dose 5 × 10 ¹⁵ / cm ² First annealing step: FA method 800 ° C. × 30 minutes Second ion implantation step: ion species used P ⁺ acceleration energy 10 keV dose 3 × 10 ¹⁵ / cm ² Second annealing step: RTA method 1100 ° C. × 10 seconds

The first ion implantation step, the first annealing step, and the second ion implantation step were continuously performed so that an interlayer film or the like was not formed on the surface of the silicon substrate.

In order to evaluate the state of occurrence of crystal defects in the semiconductor device obtained through the above steps, the incidence of side wall edge defects was measured. As shown in the plan view of FIG.
Of L ₀ the entire length of the end portion 30 of the sidewall 28, the region 50A of the crystal defects generated in the source and drain regions 40 after activation annealing length _{L 1, L 2, L 3} , L 4 such as the length of the If the sum is L, it is defined by L / L _0. Note that FIG.
The illustration of the side wall edge defect in the source / drain region on the left side of FIG. As a result of the measurement, the incidence rate of sidewall edge defects was 0%.

Example 2 A semiconductor device was manufactured under the same conditions as in Example 1 except that Si ⁺ was used in place of P ⁺ in the second ion implantation step. The occurrence rate of sidewall edge defects of the semiconductor device thus obtained was measured. As a result, even when Si ⁺ was used, the incidence of sidewall edge defects was 0%.

(Comparative Example 1) When the second ion implantation step was omitted from the steps described in Example 1, the occurrence rate of sidewall edge defects of the obtained semiconductor device was about 7-1.
2%. When the order of the steps described in Example 1 was changed to the first ion implantation step, the second ion implantation step, the first annealing step, and the second annealing step, the obtained semiconductor was obtained. Occurrence of sidewall edge defects was observed in the device.

(Embodiment 3) In the second ion implantation step, accelerated energy of P ⁺ or As ⁺
A semiconductor device was manufactured by the same manufacturing method as in Example 1, except that the energy was constant (10 keV) and the implantation dose of P ⁺ or As ⁺ was changed, and the incidence rate of sidewall edge defects was measured. did. FIG. 5 shows the relationship between the ion implantation dose and the incidence of sidewall edge defects. As is apparent from FIG. 5, as the ion implantation dose in the second ion implantation step increases, the incidence of sidewall edge defects decreases. However, if the ion implantation dose is excessively increased, crystal defects occur again.

FIG. 5 shows that it is preferable that the ion dose in the second ion implantation step be approximately 20 to 100% of the ion dose in the first ion implantation step. When As ⁺ is used in the first and second ion implantation steps, the total As ⁺ dose is 2 × 10 ¹⁵
/ Cm ² or more and A in the second ion implantation step.
The s ⁺ dose is desirably 1 × 10 ¹⁵ / cm ² or more.

(Embodiment 4) In the second ion implantation step, the implantation dose of P ⁺ was made constant (3 × 10 ¹⁴ / cm ² ) and the acceleration energy of P ⁺ was changed. A semiconductor device was manufactured by the same manufacturing method as in Example 1, except that the temperature in the second annealing step was changed, and the incidence of sidewall edge defects was measured. FIG. 6 shows the relationship between the ion implantation energy (acceleration voltage) and the incidence of sidewall edge defects. As is clear from FIG. 6, as the ion implantation energy (acceleration voltage) in the second ion implantation step increases, the incidence of sidewall edge defects decreases. If the ion implantation energy (acceleration voltage) is excessively increased, crystal defects are generated again.

Example 5 A semiconductor device was manufactured based on the method of the present invention using the semiconductor element shown in FIG. The fabrication conditions are as follows. First ion implantation step is performed through the thermal oxide film 32. Ion species used As ⁺ dose 5 × 10 ¹⁵ / cm ² Acceleration energy 20 keV 30 keV and 40 keV First annealing step: FA method 800 ° C. × 30 minutes Second ion implantation step: ion species used As ⁺ dose 3 × 10 ¹⁵ / cm ² Various changes in acceleration energy Second annealing step: RTA method 1050 ° C × 10 seconds

(Comparative Example 2) For comparison, the second
Excluding the first ion implantation step,
A semiconductor device having undergone the annealing step and the second annealing step was manufactured.

The incidence of sidewall edge defects of each of the semiconductor device samples thus obtained was measured. FIG. 8 shows the results. In FIG. 8, curves a, b, and c are respectively
The acceleration energy in the first ion implantation step is 40 k
It represents the incidence rate of sidewall edge defects at eV, 30 keV and 20 keV. In addition, A, B, and C have the As ⁺ acceleration energies in the second ion implantation step of 40 keV, 30 keV , and 30 keV , respectively, in Comparative Example-2.
It represents the incidence of sidewall edge defects at 20 keV.

As is apparent from FIG. 8, when the ion acceleration energy in the first ion implantation step is equal to the ion acceleration energy in the second ion implantation step, that is, when the ion acceleration energy is formed in the second ion implantation step. When the depth of the amorphized region is approximately the same as the depth of the amorphized region formed in the first ion implantation step,
Crystal defects in the manufactured semiconductor device are minimized.
Further, by performing the second ion implantation step,
Crystal defects in a semiconductor device can be significantly reduced. Ion acceleration energy in the second ion implantation step
Ghee is, ion acceleration energy in the first ion implantation step
Energy , that is, when the depth of the amorphized region formed in the second ion implantation step is deeper than the depth of the amorphized region formed in the first ion implantation step, Crystal defects tend to increase. From the above results, the ion acceleration energy in the second ion implantation step is preferably 50 to 130 times the ion acceleration energy in the first ion implantation step.
%, More preferably 50 to 100%, can effectively suppress crystal defects.

Comparative Example 3 A semiconductor device was manufactured using the semiconductor element shown in FIG. 2 under the following conditions. First ion implantation step is performed through the thermal oxide film 32. Ion species used As ⁺ dose amount 5 × 10 ¹⁵ / cm ² Acceleration energy 20 keV First annealing step: FA method 800 ° C. × 30 minutes Note that the second ion implantation step and the second annealing step were not performed. The sidewall edge defect occurrence rate of the semiconductor device sample thus obtained was measured and found to be 42%.

Comparative Example 4 A semiconductor device was manufactured using the semiconductor element shown in FIG. 2 under the following conditions. First ion implantation step is performed through the thermal oxide film 32. Ion species used As ⁺ dose amount 5 × 10 ¹⁵ / cm ² Acceleration energy 20 keV Second annealing step: RTA method 1050 ° C. × 10 seconds The first annealing step and the second ion implantation step were not performed. When the incidence rate of the side wall edge defect of the semiconductor device sample thus obtained was measured, it was 16%.

Example 5 and Comparative Example described above
2. The occurrence rates of the sidewall edge defects obtained in Comparative Example-3 and Comparative Example-4 are summarized as follows.

Embodiment 6 In Embodiment 6, an N ⁺ diffusion layer is formed in a silicon substrate by ion-implanting high concentration As ⁺ into a silicon substrate. This is because it is most advantageous to use As ⁺ as an ion species in order to form a shallow junction. An N ⁺ diffusion layer is formed on the silicon substrate by As ⁺ ion implantation.

By applying the method described below to a semiconductor device having an element isolation region formed by the LOCOS method, it is needless to say that occurrence of a sidewall end defect can be prevented. Now, an example in which the method for manufacturing a semiconductor device of the present invention is applied to a semiconductor element having a trench element isolation region formed by a shallow trench structure.

A semiconductor device whose schematic partial cross-sectional view is shown in FIG. 9 was manufactured. This semiconductor device has the same structure as the semiconductor device shown in FIG.
The element isolation region 12 has a shallow trench structure.

Using the semiconductor element shown in FIG. 9, a semiconductor device was manufactured under the following conditions. First ion implantation step is performed through the thermal oxide film 32. Ion species used As ⁺ acceleration energy 20 keV dose 5 × 10 ¹⁵ / cm ² First annealing step: FA method 800 ° C × 30 minutes Second ion implantation step: ion species used As ⁺ acceleration energy 10 keV dose 3 × 10 ¹⁵ / cm ² Second annealing step: RTA method 1050 ° C × 10 seconds

The source / drain region 40 adjacent to the trench element isolation region 12 of the semiconductor device obtained through the above steps was observed by TEM. As a result, no crystal defects were found in the source / drain regions. This is because, by performing the second ion implantation, a crystal defect region near the surface of the source / drain region 40 is destroyed. This is probably because sexual recovery was performed.

(Comparative Example-5) A first ion implantation step is performed based on a semiconductor device having a device isolation region 12 having a shallow trench structure, as shown in FIG. A semiconductor device having undergone the first annealing step and the second annealing step, that is, not subjected to the second annealing step, was manufactured. The manufacturing conditions were the same as in Example-6. The source / drain regions adjacent to the trench element isolation regions 12 of the semiconductor device thus manufactured were observed by TEM. As a result, as in the case shown in FIG. 11, many fine crystal defects having a length of about 20 nm were found in the source / drain regions.

(Embodiment-7) In Embodiment-7, a semiconductor device having an element isolation region 12 having a shallow trench structure will be described as an example similarly to Embodiment-6, but unlike Embodiment-6. In the second ion implantation step, P ⁺ ions are implanted.

Using the semiconductor element shown in FIG. 9, a semiconductor device was manufactured under the following conditions. First ion implantation step is performed through the thermal oxide film 32. Ion species used As ⁺ acceleration energy 20 keV dose 5 × 10 ¹⁵ / cm ² First annealing step: FA method 800 ° C. × 30 minutes Second ion implantation step: ion species used P ⁺ acceleration energy 10 keV dose 3 × 10 ¹⁵ / cm ² Second annealing step: RTA method 1050 ° C × 10 seconds

The source / drain regions adjacent to the trench element isolation regions 12 of the semiconductor device obtained through these steps were observed by TEM. As a result, no crystal defects were found in the source / drain regions.

The state shown in FIG. 10B, ie, the first state
In the state where the ion implantation step and the first annealing step are completed, the silicon substrate region 6 under the contact hole is formed.
4 includes a crystal defect 70. Next, by performing a second ion implantation step and a second annealing step, the silicon substrate region 6 below the contact hole portion is formed.
4 can suppress the occurrence of crystal defects 70.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. Conditions in each of the ion implantation step and the annealing step can be appropriately selected so as to effectively suppress generation of crystal defects in the semiconductor device. The structure of the semiconductor element is an exemplification, and a semiconductor device can be manufactured based on the manufacturing method of the present invention from a semiconductor element having various structures.

[0074]

According to the present invention, it is possible to effectively suppress the generation of crystal defects in a semiconductor device without reducing the amount of impurities to be introduced into a silicon substrate and without increasing the diffusion length. it can. Therefore, the junction leak current can be reduced without increasing the sheet resistance of the diffusion region of the semiconductor device, and for example, the data retention capability of the semiconductor memory can be improved.

Further, if electrically neutral ions are used in the second ion implantation step, the resist treatment in the second ion implantation step becomes unnecessary, and the ion implantation may be performed once over the entire surface of the wafer. In addition to the simplification of the process, there is an advantage that the degree of freedom of implantation energy (acceleration voltage) and dose is large.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor device, showing an outline of each step of a manufacturing method according to a first preferred embodiment of the present invention.

FIG. 2 shows an LOC suitable for a method of manufacturing a semiconductor device according to the present invention.
FIG. 3 is a partial cross-sectional view of a semiconductor device having an element isolation region by an OS method.

FIG. 3 shows a depth of an amorphized region of a silicon substrate generated by ion implantation and a depth of a sidewall edge defect generated in an annealing step in the method of manufacturing a semiconductor device according to the first aspect of the present invention. FIG.

FIG. 4 is a partial cross-sectional view of a semiconductor device illustrating the principle of a manufacturing method according to a second preferred embodiment of the present invention.

FIG. 5 is a diagram showing the relationship between the ion implantation dose and the incidence of sidewall edge defects in the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing the relationship between the ion implantation energy and the incidence of sidewall edge defects in the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a schematic plan view of the semiconductor device for explaining the incidence of sidewall edge defects.

FIG. 8 is a diagram showing the relationship between the ion implantation energy and the incidence of sidewall edge defects in the manufacturing method according to the second preferred embodiment.

FIG. 9 is a partial cross-sectional view of a semiconductor element having a shallow trench structure element isolation region suitable for the method of manufacturing a semiconductor device of the present invention.

FIG. 10 is a diagram illustrating crystal defects of a conventional semiconductor device.

FIG. 11 is a diagram showing crystal defects in a source / drain region adjacent to an element isolation region having a conventional shallow trench structure.

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/26-21/268 H01L 21/322-21/326 H01L 21/334-21/336 H01L 29/78

Claims (2)

(57) [Claims] 1. A first ion implantation step of implanting impurities into a silicon substrate, and a second annealing step of annealing at a temperature of 600 to 800 ° C.
(C) a second ion implantation step of ion-implanting impurities into the silicon substrate region ion-implanted in the first ion implantation step; (d) 900 to 1100 ° C., 1 to 60 seconds annealing <br/> over Ri second annealing step of performing Le from adult, is formed on a silicon substrate by a second ion implantation step
The depth of the region to be amorphized depends on the first ion implantation.
Of the amorphized region formed by the
Shallower than the depth and due to the second ion implantation step.
Area formed on the silicon substrate
The depth of the region depends on the size of the connection formed by the first annealing step.
The second ion is deeper than the depth of the crystal defect region.
A method for manufacturing a semiconductor device, comprising selecting ion implantation conditions in an implantation step . 2. A second ion implantation step, a method of manufacturing a semiconductor device according to claim 1, wherein the electrically implanting ions of neutral.