JP3325780B2 - Shift register circuit and image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register circuit and an image display using the same.

[0002]

2. Description of the Related Art Various types of matrix-type display devices are available. In recent years, active matrix-type display devices using active elements as switching elements included in each pixel have been developed. The spread to is expanding. An active matrix display device usually has a drive circuit for driving a pixel group in a display panel. As the driving circuit, for example, a shift register circuit is given.

First, FIG. 8 shows a configuration of a general shift register. As shown in the figure, this shift register includes a clock signal CK and an inverted clock signal / C applied to latch circuits LT1 to LTN (here, N stages).
By supplying K, the start signal ST is sequentially transferred to obtain output signals OUT1 to OUTN.

Next, in these shift registers,
Latch circuits LTk, LT (k + 1) for two adjacent stages
FIG. 9 shows a specific configuration example (where k is an odd number of 1 ≦ k <N). In FIG. 9, the preceding latch circuit LTk includes an inverter 91 and clocked inverters 92 and 93, and the subsequent latch circuit LT (k + 1) includes an inverter 94 and clocked inverters 95 and 96. The clocked inverters 92, 93, 95, and 96 function as normal inverters when an input of a control terminal is in an active state, and output high impedance when inactive.

Each of the latch circuits LTk and LT (k + 1) makes the inverters 91 and 94 and one of the clocked inverters 92 and 95 a circulating state, thereby forming a flip-flop circuit. Also, the input start signal ST
Are transferred to the next stage through clocked inverters 93 and 96 and inverters 91 and 94, respectively, and output signals OUTk and O are output from the outputs of these inverters 91 and 94, respectively.
UT (k + 1) is obtained. Then, the clock signal CK is supplied to the control terminal of the other clocked inverter 93 in the preceding latch circuit LTk and the control terminal of one clocked inverter 95 in the subsequent latch circuit LT (k + 1). C
K is the control terminal of one clocked inverter 92 in the preceding latch circuit LTk and the latter latch circuit LTk.
It is connected to the control terminal of the other clocked inverter 96 at (k + 1).

A latch circuit L in the above shift register
In Tk and LT (k + 1), when the clock signal becomes active, the preceding latch circuit LTk captures the start signal ST via the clocked inverter 93, and the subsequent latch circuit LT (k + 1) cuts off the input and receives the input immediately before. The start signal ST is held by the flip-flop circuit of the inverter 94 and the clocked inverter 95. When the clock signal / CK becomes active in the next half cycle, the preceding latch circuit LTk cuts off the input and holds the start signal ST input immediately before by the flip-flop circuit of the inverter 91 and the clocked inverter 92. And the subsequent latch circuit LT (k
+1) captures the start signal ST output from the latch circuit LTk via the clocked inverter 96. Therefore, these latch circuits LTk, LT (k
+1) performs an operation of sequentially latching the start signal ST of the preceding stage in accordance with the rise and fall of the clock signal and transferring it to the next stage.

Next, FIG. 10 shows a schematic configuration diagram of an active matrix type liquid crystal display device. As shown in FIG.
The active matrix type liquid crystal display device has a liquid crystal panel A
RY, a data signal line drive circuit SD, and a scanning signal line drive circuit GD. The liquid crystal panel ARY is one in which two transparent substrates made of glass or the like are arranged to face each other via a liquid crystal. On one of the transparent substrates, m data signal lines SL1 to SLm and n scanning signal lines GL are provided.
1 to GLn are formed in a grid pattern vertically and horizontally, and the data signal line SLi (i is an integer of 1 ≦ i ≦ m) and the scanning signal line GLj (j is an integer of 1 ≦ j ≦ n) are formed. Pixels PIXi, j are formed at each intersection. The data signal line drive circuit SD is a drive circuit that samples the data signal DAT with the data clock signal CKS and the start signal SPS, and distributes and sends the data signals to the data signal lines SL1 to SLm. The scanning signal line driving circuit sequentially scans the scanning signal lines GL1 to GLn one by one in accordance with the scanning clock signal CKG and the start signal SPG, and scans the data signals DAT sent to the data signal lines SL1 to SLm.
Of pixels PIX1, j to PIXm, j of one row in which
Is a circuit for selecting. The signal GPS is input to make the pulse width of the pulse input to the scanning signal line variable.

Here, the data signal line driving circuit will be described. There are a dot-sequential driving method and a line-sequential driving method in which the data signal line driving circuit sends the data signal DAT to each data signal line SLi. The point-sequential driving method is a method in which the data signal DAT is sent out to the data signal line SLi every time it is sampled. The line-sequential driving method is a method in which the data signal DA is sequentially sampled over one horizontal period.
T is held once, and the data signals DAT for one row are simultaneously transmitted to the data signal lines SL1 to SLm. A shift register is used as the data signal line driving circuit in any of the methods. FIG. 11 shows a data signal line driving circuit using a dot sequential driving method with a simple circuit configuration.

As shown in FIG. 11, the data signal line driving circuit includes a shift register including m stages of latch circuits LT1 to LTm, and a start signal SPS is sequentially supplied to each stage in synchronization with a data clock signal CKS. Circuit LTi
(1 ≦ i ≦ m). The start signal SPS is
This is a pulse signal that outputs one pulse every one horizontal period. The latch signals of the start signal SPS output in parallel from the latch circuits LTi of the respective stages are input to the control terminals of the sampling switches ASW1 to ASWm via the buffer circuits BUF1 to BUFm, respectively. Each buffer circuit BUFi (1 ≦ i ≦ m) is a circuit that amplifies the start signal SPS held by the latch circuit, inverts the signal as necessary, and outputs the inverted signal. Each sampling switch ASWi (1 ≦ i ≦ m) Is an analog switch for turning on / off the circuit according to the input of the control terminal.

The data signal DAT is sent to the data signal lines SL1 to SLm via the sampling switches ASW1 to ASWm, respectively. Therefore, this data signal line drive circuit is provided for each horizontal period.
The pulses of the start signal SPS are sequentially transferred by the latch circuits LTi at each stage of the shift register, so that each sampling switch ASWi is sequentially turned on to sample the data signal DAT and send it out to each data signal line SLi.

Next, the liquid crystal panel ARY will be described. A pixel PIXi, j formed at each intersection of the data signal line SLi and the scanning signal line GLj in the liquid crystal panel ARY is shown in FIG.
As shown in FIG. 2, the switching element SW includes a pixel capacitance including a liquid crystal capacitance Cl and an auxiliary capacitance Cs. The switch element SW is a MOS-structured thin film transistor (TFT) formed on one transparent substrate, and has a gate connected to the scanning signal line GLj. Liquid crystal capacitance C
1 is a capacitance via a liquid crystal between the pixel electrode formed in the pixel PIXi, j on one transparent substrate and the common electrode on the other transparent substrate, and the auxiliary capacitance Cs is Is a capacitor element provided on one of the transparent substrates as necessary to supplement the electric charge accumulated in the transparent substrate. The pixel electrode of the liquid crystal capacitor Cl and one electrode of the auxiliary capacitor Cs are connected to the data signal line SLi via the source and the drain of the switch element SW. For this reason, when the scanning signal line GLj is activated by the scanning of the scanning signal line driving circuit GD, the pixels PIX1, j to PIX in the corresponding row are activated.
m and j are turned on, and the data signal DAT sent from the data signal line drive circuit SD to the data signal lines SL1 to SLM is applied to each pixel PIX.
The data is written to the liquid crystal capacitance Cl and the auxiliary capacitance Cs of 1, j to PIXm, j. Therefore, this liquid crystal display device is configured such that each pixel PIX of the liquid crystal panel ARY responds to data signal DAT.
Since the applied voltage of the liquid crystal capacitance Cl at i and j changes, the transmittance and the reflectance of the pixel PIXi and j are controlled, and an image is displayed by the pixels of n rows and m columns.

In recent years, the use of a matrix-type image display device as a display-integrated video camera or digital still camera has been expanding. In particular, in a video camera with a built-in display, it is necessary to switch between normal display for shooting a normal subject and mirror image display for shooting of the photographer himself, and it is possible to transfer the start signal bidirectionally to respond to this Drive circuits (a data signal line drive circuit capable of transmitting the data signal DAT to the data signal lines SL1 to SLm in the reverse direction, and a scan signal line capable of scanning the scan signal lines GL1 to GLn in the reverse direction). Drive circuit) is required.

In order to satisfy the above requirements, a data signal line driving circuit and a scanning signal line driving circuit using a shift register capable of transferring a start signal bidirectionally have been developed.

FIG. 13 shows a shift register capable of transferring a start signal in both directions (a bidirectional shift register, here, K stages). FIG. 13 shows two adjacent latch circuits LTk, LT (k + 1) ( k is an odd number of 1 ≦ k <K)
FIG. 14 shows a specific configuration example.

As shown in FIG. 13, a scan signal LR is input to each latch circuit of the shift register, and a start signal can be transferred bidirectionally.

As shown in FIG. 14, the preceding latch circuit L
Tk is four clocked inverters 101 to 103, 1
07, and the subsequent latch circuit LT (k + 1) also has four clocked inverters 104 to 106 and 108 similarly.
Consists of As an input signal, a scan signal L for determining a transfer direction of a start signal is supplied to a normal shift register circuit.
R and its inverted signal scan signal bar / LR are added.

The clock signal CK is supplied to the control terminal of the clocked inverter 103 in the preceding latch circuit LTk and the control terminal of the clocked inverter 105 in the subsequent latch circuit LT (k + 1). The control terminal of the clocked inverter 102 in the preceding latch circuit LTk and the clocked inverter 106 in the subsequent latch circuit LT (k + 1)
Is connected to the control terminal. And the scan signal LR
Is the clocked inverter 101 of the preceding latch circuit LTk.
The scan signal / LR is connected to the clocked inverter 104 of the rear-stage latch circuit LT (k + 1) and the control terminal of the clocked inverter 108 of the rear-stage latch circuit LT (k + 1). Connected.

In the shift register, the start signal ST is input to the latch circuit LTk, and the latch circuit LTk
To LT (k + 1) from the scan signal LR
Is activated, the clocked inverter 101 of the first-stage latch circuit LTk and the second-stage latch circuit LT (k +
The clocked inverter 104 of 1) functions as a normal inverter, and the clocked inverter 107 of the front-stage latch circuit LTk and the clocked inverter 108 of the rear-stage latch circuit LT (k + 1) have high impedance, similar to the above-described normal shift register. The operation of OU
An output signal can be obtained in the order of Tk and OUT (k + 1).

Next, the latch circuits LT (k + 1) to LT (k + 1)
In the case of transfer to k, the clock signal inverter 107 of the latch circuit LTk and the clocked inverter 108 of the latch circuit LT (k + 1) function as a normal inverter by activating the scan signal / LR.
The clocked inverter 101 of the latch circuit LTk and the clocked inverter 104 of the latch circuit LT (k + 1) become high-impedance, and perform an operation opposite to that described above to obtain an output signal in the order of OUT (k + 1) and OUTk. Wear.

Then, by replacing the shift register of the data signal line drive circuit SD or the scan signal line drive circuit GD in FIG. 10 with the bidirectional shift register, if the data signal line drive circuit is a bidirectional data register, Scanning of the signal lines is realized, and left-right inverted display is possible. With a scanning signal line driving circuit, bidirectional scanning of the scanning signal lines is realized, and vertical inverted display is possible.

[0021]

However, both of the above-mentioned shift registers have one horizontal period (data signal line driving circuit).
Also, since only one pulse is transferred per vertical period (scanning signal line driving circuit), the power consumption (power consumption as viewed from the power supply terminal) associated with the transfer of the start signal ST does not increase so much. However, the clock signals CK and / CK are input to the control terminals of the clocked inverters 102 and 103 and the clocked inverters 105 and 106 of the latch circuits LTk (k is an integer of 1 ≦ k ≦ K) of each stage, Period or 1
The signal level changes repeatedly during the vertical period.
In addition, the number of stages K of the shift register used in the display device is extremely large. In the case of the VGA standard, 640 stages are required for the data signal line driving circuit and 480 stages are required for the scanning signal line driving circuit. Further, according to the XGA standard, the data signal line drive circuit requires 1024 stages, and the scan signal line drive circuit requires 768 stages.

For this reason, the conventional shift register has a problem that a large amount of current flows to charge the parasitic capacitance in the signal line of the clock signal CK, the gate capacitance of the clocked inverter, and the like, and the current consumption becomes extremely large. was there.

In order to solve the above problem, the shift register is divided into a plurality of circuit blocks, and a clock signal is supplied only to the circuit block to which the pulse portion of the start signal is transferred, and power consumption by the clock signal is reduced. A technique for suppressing the increase in the density is disclosed in JP-B-63-50717. This is achieved by synchronizing with the clock signal divided by the frequency dividing circuit, and transferring the start signal by the selection shift register having the number of stages corresponding to the number of circuit blocks obtained by dividing the shift register, thereby supplying the clock signal. Are sequentially selected, but none of the above techniques is applied to a bidirectional shift register.

[0024]

SUMMARY OF THE INVENTION The present invention provides a circuit block in which a plurality of latch circuits for outputting a signal corresponding to an input signal based on a clock signal are connected in series, and a clock signal is supplied to the latch circuit of each circuit block. And a clock signal control circuit for controlling the operation of the latch circuit.
The rising edge and falling edge of the
The start signal is latched and transferred to the next stage.
The output signal is sequentially applied for one period of the clock signal.
The shift register circuit according to active state, the shift is possible to transfer the start signal bidirectionally
In the register circuit, the clock signal control circuit
The set terminal has one of the corresponding circuit blocks.
The output level of each latch circuit in the previous circuit block
That is, the outputs of the last stage and before the second stage are connected, and
The reset terminals of the lock signal control circuit
Each circuit block after the corresponding circuit block
Of the outputs of the latch circuit, the outputs of the second and subsequent stages are connected.
In addition, each of the clock signal control circuits
Based on a scan signal that determines the transfer direction of the signal
After the input of the set terminal becomes active,
Clock signal is supplied until the reset pin becomes active.
Whether the reset terminal input is active
The period until the input of the set terminal becomes active,
It is characterized by controlling whether to supply a clock signal , and thereby the above object is achieved.

According to the present invention, an input signal is generated based on a clock signal.
Multiple latch circuits that output signals in accordance with
Circuit blocks and the latch times of each circuit block
A clock signal control circuit that supplies a clock signal to the
Wherein each of the latch circuits has a rising edge of the clock signal.
The start signal of the previous stage is sequentially latched by the falling edge
To the next stage, and sequentially output signals from each latch circuit.
Activate one cycle of the clock signal
A shift register circuit, wherein the start signal is
Shift register circuit that can transfer data
And the set terminal of each clock signal control circuit includes:
The circuit block immediately before the corresponding circuit block
Of the output of each latch circuit at the last stage
Connected to the output of each of the clock signal control circuits.
The reset terminals of the corresponding circuit blocks
Of the output of each latch circuit in the circuit block immediately after
Of these, the outputs of the second and subsequent stages are connected, and
Lock signal control circuit determines transfer direction of start signal
When the scan signal to be activated is active, the set terminal
After the input becomes active, the reset terminal
A clock signal is supplied until the active state.
When the can signal is inactive, the reset terminal
After the input is activated, the input of the set terminal
Supply a clock signal until active.
The purpose of the above is to
Achieved.

Further, the output signal of the circuit block of the preceding circuit block corresponding to the prior Symbol clock signal control circuit, the output of the latch circuit of the second stage from the last stage, the output signal from the subsequent circuit blocks, 2 Preferably, it is the output of the latch circuit of the stage .

Further, it is preferable that an additional circuit block for controlling the stop of the supply of the clock signal to the adjacent circuit block is provided at both ends of the shift register.

The input signal of the shift register circuit is
It is preferable that the input be made between the additional circuit block and the circuit block.

It is preferable that, of the additional circuit blocks, the additional circuit block on the input side of the start signal is stopped in response to the input of the start signal.

Preferably, the additional circuit block is formed by connecting two or more stages of latch circuits in series.

Preferably, the clock signal control circuit includes a logic circuit for supplying a clock signal to a latch circuit in the block, and the logic circuit receives an initialization signal.

Further, it is preferable that a polycrystalline silicon thin film is used for a transistor element constituting the latch circuit.

According to the present invention, there are provided a plurality of pixels arranged in a matrix, a plurality of data signal lines arranged corresponding to each column of the pixels, and a plurality of data signal lines synchronized with a predetermined timing signal. A data signal line driving circuit for sequentially outputting video signal data, a scanning signal line arranged corresponding to each row of the pixels, and sequentially outputting scanning signals to the plurality of scanning signal lines in synchronization with a predetermined timing signal An active matrix comprising a liquid crystal panel having a scanning signal line driving circuit and supplying a video signal for image display from each data signal line to each pixel in synchronization with a scanning signal supplied from each scanning signal line; In the image display device, the data signal line driving circuit or the scanning signal line driving circuit includes a circuit for sequentially outputting a sampling signal for capturing video data corresponding to each data signal line. Wherein it is characterized in that using the shift register, whereby the above-mentioned object can be achieved Te.

At least one of the data signal line driving circuit and the scanning signal line driving circuit has a circuit element constituting the driving circuit formed on a substrate constituting the liquid crystal panel by the same process as an element constituting a pixel. It is preferable that the element is manufactured.

Hereinafter, the operation will be described.

According to the present invention, a circuit block in which a plurality of latch circuits for outputting a signal corresponding to an input signal based on a clock signal are connected in series, and a clock signal control for supplying a clock signal to the latch circuit of each circuit block A shift register circuit that sequentially transfers a start signal in synchronization with the clock signal, wherein the shift register circuit is capable of transferring the start signal bidirectionally. Therefore, when the present invention is applied to, for example, a display-integrated video camera, it is possible to switch between normal display and mirror image display, while reducing the power consumption consumed by the shift register unit. In addition, when the present invention is applied to a projection, it can be installed on a normal floor or installed on a ceiling.

A clock signal supplied from the clock signal control circuit is controlled by an output signal of a circuit block preceding the circuit block corresponding to the clock signal control circuit and an output signal of a subsequent circuit block. Therefore, there is no need to connect a large-scale circuit for limiting the supply of the clock signal CK to the outside, and the clock signal can be controlled by a simple circuit, so that the circuit scale is reduced.

The output signal of the circuit block preceding the circuit block corresponding to the clock signal control circuit is the output of the latch circuit of the second stage before the last stage, and the output signal of the circuit block of the subsequent stage is the second stage. Since it is characterized by the output of the subsequent latch circuit, the output of the last stage of the circuit block corresponding to the clock signal control circuit can be set to L level (inactive state) and terminated.

An additional circuit block for controlling the stop of the supply of the clock signal to the adjacent circuit block is provided at both ends of the shift register, so that the final output of the final circuit block is set to L level (inactive state). ). That is, the transfer state of the last-stage circuit block can be completely terminated.

Since the start signal of the shift register circuit is inputted between the additional circuit block and the circuit block, when the start signal is transferred from the additional circuit block to the first circuit block, There is no problem that the start signal is not transferred normally due to the delay of the internal clock signal with respect to the clock signal.

The additional circuit block on the input side of the start signal among the additional circuit blocks is characterized by being stopped in response to the input of the start signal, so that the power consumption can be further reduced.

The additional circuit block is characterized in that two or more stages of latch circuits are connected in series, so that the final output of the final circuit block can be terminated at L level (inactive state).

The clock signal control circuit has a logic circuit for supplying a clock signal to a latch circuit in the block, and the logic circuit receives an initialization signal. In this case, the unstable internal state is refreshed, and the outputs of the internal latch circuits are all set to the normal L level (inactive state), thereby preventing the problem that the start signal is not transferred normally.

Since the transistor element constituting the latch circuit is characterized by using a polycrystalline silicon thin film, other peripheral circuits can be easily formed on the same substrate, for example.

According to the present invention, a plurality of pixels arranged in a matrix, a plurality of data signal lines arranged corresponding to each column of the pixels, and the plurality of data signal lines are synchronized with a predetermined timing signal. A data signal line driving circuit for sequentially outputting video signal data, a scanning signal line arranged corresponding to each row of the pixels, and sequentially scanning the plurality of scanning signal lines in synchronization with a predetermined timing signal. A liquid crystal panel having a scanning signal line driving circuit for outputting, and a video signal for image display being supplied to each pixel from each data signal line in synchronization with a scanning signal supplied from each scanning signal line. In the active matrix type image display device, the shift register is used for the data signal line driving circuit or the scanning signal line driving circuit. Reducing, at the same time in the case of applying the present invention for example to a display-integrated video camera the normal display, it is possible to switch the mirror display. In addition, when the present invention is applied to a projection, it can be installed on a normal floor or installed on a ceiling.

At least one of the data signal line driving circuit and the scanning signal line driving circuit has a circuit element constituting the driving circuit formed on the substrate constituting the liquid crystal panel by the same process as an element constituting a pixel. Since the liquid crystal panel is characterized in that it is an element, the frame portion of the liquid crystal panel can be reduced, and the mounting cost can be reduced.

[0047]

Embodiments of the present invention will be described below. Embodiment 1 FIG. 1 shows a configuration diagram of a shift register circuit according to Embodiment 1 of the present invention. In the present embodiment, a case will be described in which a shift register circuit (shown in FIG. 14) capable of transferring a 1-bit bidirectional start signal is divided into n circuit blocks, each having m stages of latch circuits in the stage direction. I do. However, the number of divisions of the shift register circuit of the present invention and the number of latch circuits in each circuit block are arbitrary, and the number of stages may be different for each circuit block. Further, the present invention can be similarly applied to a multi-bit shift register circuit.

FIG. 1 shows a shift register circuit according to Embodiment 1 of the present invention, which includes n circuit blocks (latch circuit groups) BLK1 to BLKn, additional circuit blocks (additional latch circuit groups) BLKx and BLKy, and these circuit block groups. It is constituted by clock signal control circuits CTRL1 to CTRLn provided corresponding to BLK1 to BLKn and analog switches ASW1 to ASW6.

N circuit blocks BLK1 to BLKn
, The input and output are sequentially connected in series, and the start signal ST is analog switches ASW1, ASW2, ASW4, AS
Additional circuit blocks BLKx, CTRL1,
BLKy and CTRLn. The clock signal CK of the shift register circuit is supplied to the additional circuit blocks BLKx and BLKy and the clock signal control circuit CTRL1.
To CTRLn, the clock control circuit generates internal clock signals CK1 to CKn and clock signals / CK1 to / CKn, which are inverted signals of the internal clock signals, and supplies them to the respective circuit blocks BLK1 to BLKn. .

Each clock signal control circuit CTRL1-CT
RLn has a set terminal S and a reset terminal R,
A set terminal S of the clock signal control circuit CTRL1 has a start signal ST via an analog switch ASW2,
Circuit block BLK via analog switch ASW3
x output OUTx is connected. CTRL2-CT
To the set terminal S of RLn, the output of the last stage to the stage before the last stage in the parallel output of the circuit block immediately before the corresponding circuit block is connected. In FIG. 1, the output of the second stage from the last stage is the clock signal control circuit C
Connected to set terminals S of TRL2 to CTRLn.
The outputs of the second and subsequent stages in the parallel output of the circuit block immediately after the corresponding circuit block are connected to the reset terminal R. In FIG. 1, 2
The output of the stage is a clock signal control circuit CTRL1 to CTRL
It is connected to the reset terminal R of L (n-1).

The reset terminal R of the clock signal control circuit CTRLn is connected to the start signal ST via the analog switch ASW5 and the output OUTy of the circuit block BLKy via the analog switch ASW6. The scan signal LR that determines the transfer direction of the start signal ST and the inverted signal / LR are supplied to the circuit block B.
LK1 to BLKn, clock signal control circuit CTRL1
CTRLn and the additional circuit blocks BLKx and BLKy.

Each of the circuit blocks BLK1 to BLKn has a bidirectional start signal S connected in series in m stages.
It comprises latch circuits LT1 to LTm capable of transferring T. Then, the internal clock signals CK1 to CKn and the internal clock signals / CK1 to / CKn output from the clock control circuits CTRL1 to CTRLn are supplied to the latch circuits LT1 to LTm in the corresponding circuit blocks, respectively.
These output signals OUT1, 1 to OUT1, m are output to the outside. Further, the subsequent circuit blocks BLK2 to BLKB
The same applies to the outputs OUT2, 1 to OUTn, m of LKn, and OUT1, 1 to OUTn, m are sent to the outside as parallel outputs of the shift register circuit. The scan signals LR and / LR are connected to all the latch circuits.

The additional circuit blocks BLKx and BLKy are
The start signal ST is connected to the latch circuit LT1 of the circuit block BLKx via the analog switch ASW1 and the latch circuit LT2 of the circuit block BLKy via the analog switch ASW4. .

FIG. 2 shows a clock signal control circuit CTRLi.
(I is an integer of 1 ≦ i ≦ n). The clock signal control circuit includes NOR gates 21 and 22, clocked inverters 23 and 24, and one NAND gate 25 and an inverter 26. As shown in FIG. 1, the input and output of the NOR gates 21 and 22 are connected to each other to form an RS flip-flop circuit.
Is connected to a reset terminal R. The output Q of the circuit is connected to a clocked inverter 24 having a control terminal connected to a scan signal / LR, and the output / Q is connected to a clocked inverter 2 having a control terminal connected to a scan signal LR.
3 is connected. Then, these two outputs are used as the selection signal SBi, which is input to one terminal of the NAND gate 25, and the clock signal CK is input to the other input terminal.
This output is used as the internal clock signal / CKi (1 ≦ i ≦ m)
And the inverted signal of the signal / CKi via the inverter 26 is defined as an internal clock signal CKi (1 ≦ i ≦ m).

When the scan signal LR is active, the clocked inverter 23 functions as a normal inverter, and the clocked inverter 24 becomes high impedance. Therefore, once the set terminal S becomes active, the output / Q becomes inactive, and the selection signal SBi becomes active via the clocked inverter 23.
Next, even when the set terminal S becomes inactive, the active state of the selection signal SBi is maintained. Further, once the input of the reset terminal R becomes active, the selection signal SBi
Becomes inactive, and then the inactive state of the selection signal SBi is maintained even if the input of the reset terminal R returns to inactive.

When the scan signal LR is inactive, the clocked inverter 23 has a high impedance, and the clocked inverter 24 functions as a normal inverter. Therefore, once the reset terminal R becomes active, the output Q becomes inactive, and the selection signal SBi becomes active via the clocked inverter 24. Even if the set terminal S becomes inactive, the active state of the selection signal SBi is maintained. Also, once the input of the set terminal S becomes active, the selection signal SBi
Becomes inactive, and the inactive state of the selection signal SBi is maintained even after the input of the set terminal S returns to inactive.

The selection signal SBi is the scan signal LR
Is active during the period from when the input of the set terminal S becomes active to when the reset terminal R becomes active, the internal clock signal CK
i, an internal clock signal / CKi which is an inverted signal of the signal
Is output.

When the scan signal LR is inactive, it is in an active state from the time when the input of the reset terminal R becomes active to the time when the set terminal S becomes active, and the internal clock signal CKi and the inverted signal of the signal are obtained. Is output as the internal clock signal / CKi.

Next, the operation will be described. FIG. 3 is a time chart illustrating the operation of the shift register circuit of the first embodiment. In the present embodiment, each circuit block BLK
It is assumed that i is composed of 16 stages (m = 16) of latch circuits LT1 to LT16. Further, one cycle of the clock signal is defined as a period T, and the description of the internal clock signals / CK1 to / CKn is omitted.

First, the case where the scan signal LR is active will be described. When the scan signal LR is active, the analog switches ASW1, ASW in FIG.
2. ASW6 is conducting, analog switch ASW3,
ASW4 and ASW5 become non-conductive, and in the latch circuit shown in FIG.
1 and 104 function as normal inverters, and the clocked inverters 107 and 108 have high impedance.

When the start signal ST rises to the H level, the set terminal S of the clock control circuit CTRL1 goes to the H level (active), and the internal clock signal CK1 goes to the circuit block BLK1 with a short delay when the selection signal SB1 goes to the H level. Start to be supplied.

When the internal clock signal CK1 rises, the additional circuit block BLKx (the latch circuit 2)
), The start signal ST is supplied to the circuit block BLK1.
, And the output OUT1,1 of the first-stage latch circuit LT1 in the circuit block goes high (active) at time t1. The internal clock signal C
When K1 falls at time t2, the second-stage latch circuit L
Outputs OUT1 and OUT2 of T2 rise to H level. These output signals OUT1,1 and OUT1,2 return to the L level after each period T, and thereafter the output signals OUT1, OUT1 each time the internal clock signal rises and falls.
3 to OUT1 and 16 sequentially become H level for each period T.

Next, at time t3, the output signals OUT1, OUT1,
When 15 rises to the H level, the set terminal S of the clock signal control circuit CTRL2 goes to the H level, and the selection signal SB2 goes to the H level with a slight delay, so that the internal clock signal CK2 starts to be supplied to the circuit block BLK2.
Then, 2 of internal clock signal CK2 at time t4
At the first rising edge (when the scan signal LR is in the inactive state, a margin is required for the period T for a reason to be described later), the first-stage latch circuit L of the circuit block BLK2
The output signal OUT2,1 of T1 becomes H level. Also,
The output signals OUT2 and OUT2 of the second-stage latch circuit LT2 are H
At the time t5 when the level becomes the clock signal control circuit CTRL
1 is input to the reset terminal R of the H.1, and the selection signal S
When B1 goes low, the internal clock signal CK1 stops. The internal clock signal CK1 is supplied to the circuit block BLK1 for an extra clock pulse after the output signals OUT1 and OUT16 of the last-stage latch circuit LT16 of the circuit block BLK1 rise, so that the latch circuit LTm captures the L level. , And hold the output signals OUT1 and OUT16 as normal L levels.

The reason why the internal clock CKi needs a margin for one pulse will be described with reference to FIGS. FIG. 15 is a time chart of two stages of latch circuits (FIG. 9). First, in FIG. 15, when the inverted clock signal / CKi becomes active at time t1, the clocked inverter 96 in the latch circuit LT (k + 1) is activated.
Functions as a normal inverter, the clocked inverter 95 becomes high impedance, and the pre-stage latch circuit L
The H level of the output OUTk of Tk is taken in and OUT (k +
1) outputs the H level. Next, the clock signal CKi
Is activated at time T2, the latch circuit LT (k +
The clocked inverter 95 of 1) functions as an inverter, and the clocked inverter 96 becomes high impedance, so that OUT (k + 1) holds the H level.
Finally, at time t3 when the inverted clock signal / CKi becomes active again, the L level of the output OUTk of the preceding-stage latch circuit LTk is taken in, and OUT (k + 1) outputs the L level. Therefore, in order for the output OUT (k + 1) to fall after rising, at least the time from time t1 to t3, that is, a margin for one pulse of the clock signal is required.

Thus, the internal clock signal is supplied to the circuit block BLK1 only during the period when the selection signal SB1 is at the H level (active), and the transfer operation is started and completed. The same operation is performed on the subsequent blocks, so that the clock signals CK are sequentially changed to the circuit blocks BLK2 to CKn as the internal clock signals CK2 to CKn.
BLKn, and the final circuit block BL at time t6.
Kn output signal OUT of last latch circuit LT16
n and 16 become H level.

Then, at time t7, a reset signal O from an additional circuit block BLKy consisting of two stages of latch circuits becomes
When UTy goes to H level and the H level is input to the reset terminal R of the final clock signal control circuit CTRLn, the supply of the internal clock signal CKn is stopped. The additional circuit blocks BLKx and BLKy are added in order to completely end the transfer operation of the last circuit block.

Next, the case where the scan signal is inactive will be described. When the scan signal is inactive, the analog switches ASW3, ASW4, AS
W5 is conducting, analog switches ASW1, ASW
2. The ASW 6 is turned off, and in the latch circuit shown in FIG.
8 functions as a normal inverter, and the clocked inverters 101 and 104 have high impedance.

The start signal ST is supplied to the additional circuit block BL
Ky and the reset signal R are input to the reset terminal R of the clock signal control circuit CTRLn, the supply of the internal clock signal CKn starts, and the start signal S via the additional circuit block BLKy.
T is input to the latch circuit LTm of the circuit block BLKn, and the latch circuit Lm is synchronized with the internal clock signal CKn.
Tm, LT (m-1) to LT1 are transferred in this order. The supply of the internal clock signal CK1 to the circuit block BLK1, which is the final circuit block, is performed by the additional circuit block BL.
It stops when the output OUTx from Kx is input to the set terminal S of the clock signal control circuit.

Therefore, contrary to the case where the scan signal is active, outputs can be obtained in the order from OUTn, m to OUTY1,1.

As described above, the shift register circuit of the present invention supplies the clock signal CK only to the circuit block BLKi that transfers the pulse portion where the start signal ST goes to the H level. Therefore, since this clock signal CK is supplied only to approximately 1 / n of the latch circuits of the entire shift register circuit, the parasitic capacitance in the signal line and the clocked inverters 102, 103, 105, 1
06 (FIG. 14) can be reduced.

Further, the start and end timing pulses of the supply of the clock signal CK are transmitted to the preceding and following circuit blocks BL.
K1 to BLKn and additional circuit blocks BLKx, BLKy
Clock signal control circuits CTRL1 to CTRLC having a simple circuit configuration because they are obtained from the outputs of the latch circuits L1 and LT2.
The supply of the clock signal can be controlled only by providing the TRLn, and the circuit scale does not become unnecessarily large. Further, since it is not necessary to connect a large-scale circuit for limiting the supply of the clock signal CK to the outside, it is possible to improve the reliability and reduce the cost in terms of mounting. The shift register circuit is also effective when formed using a single-crystal silicon transistor, but the effect is particularly remarkable when formed using a polycrystalline silicon thin-film transistor. This is because the element characteristics of the polycrystalline silicon thin film transistor are inferior to those of the single crystal silicon transistor, so that it is necessary to increase the element size, which leads to an increase in the circuit capacity and the inferior element characteristics. This is because power consumption by the clock signal increases because the driving voltage increases.

(Embodiment 2) A second embodiment of the present invention will be described with reference to FIG. This corresponds to the input position of the start signal ST of the shift register circuit described in the first embodiment,
This is a modification of the method of supplying a clock signal to the additional circuit blocks BLKx and BLKy, and the basic operation is the same as that of the first embodiment.

In the figure, a start signal ST is supplied to an additional circuit block BLKx via an analog switch ASW1.
Between the analog block AS and the circuit block BLK1
W2 to the set terminal S of the clock signal control circuit CTRL1, between the additional circuit block BLKy and the circuit block BLKn via the analog switch ASW4, and the clock signal control circuit CTRL via the analog switch ASW5.
n is input to each of the n reset terminals R. Further, the output O from the latch circuit LT1 of the additional circuit block BLKx is output.
UTx is a clock signal control circuit CTRL via ASW3.
The output OUTy from the latch circuit LT2 of the additional circuit block BLKy is input to the reset terminal R of the clock signal control circuit CTRLn via the ASW6. Then, the additional clock signal control circuit CTRL
x and CTRLy, and the clock signal CK
The additional clock signal control circuit CTRLx is provided with the scan signal bar / LR and the additional clock signal control circuit CTRL.
The scan signal LR is input to y.

FIG. 5 shows the configuration of the additional clock signal control circuit. This additional clock signal control circuit comprises NAND gates 51 and 53 and inverters 52 and 54,
The clock signal CK is input to one of the two inputs of the D gates 51 and 53. In the case of the additional clock signal control circuit CTRLx at the other input,
When the scan signal / LR is the additional clock signal control circuit CTRLy, the scan signal LR is input and the internal clock signals CKx, / CKx, and CKy, / C
Ky is generated. Then, the internal clock signal CKx, /
CKx is applied to the additional circuit block BLKx, and the internal clock signals CKy and / CKy are applied to the additional circuit block BLKy.
Respectively.

Next, the operation will be described with reference to FIG. Here, the additional circuit blocks BLKx and BLKy will be described. For other basic operations, refer to the first embodiment.
Is the same as

However, the start signal ST and the parallel output signals OUT1, 1 to OUTn, m of the shift register circuit are provided.
Does not pass through the two-stage latch circuits in the additional circuit blocks BLKx and BLKy, so the output timing is advanced by T.

First, the case where the scan signal LR is in the active state will be described. When the scan signal LR is in the active state, the analog switches ASW1 and AS
W2 and ASW6 are conducting, and the remaining analog switches are non-conducting. Since the scan signal LR is active, the additional clock signal control circuit CTRLy supplies the internal clock signals CKy and / CKy and the additional circuit block BLKy performs a normal operation, but the additional clock signal control circuit CTRLx performs the internal clock signals CKx and / CK. CK
x is not supplied, the additional circuit block BLKx is stopped, and the same operation as in the first embodiment is performed.

Next, the case where the scan signal LR is in the inactive state will be described. When the scan signal LR is in the inactive state, the analog switches ASW1, ASW
2. The ASW 6 is non-conductive, and the remaining analog switches are conductive. Contrary to the case described above, the additional circuit block BLKx performs a normal operation, but the additional circuit block BLKy is in a stopped state. That is, in the first embodiment, both the additional circuit blocks BLKx and BLKy operate, but only one of the additional circuit blocks operates, and power consumption can be reduced. Therefore, not only the same effects as in the first embodiment are obtained, but also the power consumption can be further reduced.

Further, according to the configuration of the first embodiment, for example, when the scan signal LR is active, the start signal ST
Is transferred by the clock signal C in the additional circuit block BLKx.
At K, the data is transferred in synchronization with the internal clock signal CK1 in the subsequent circuit block BLK1. This clock signal C
Comparing K with the internal clock signal CK1, the load of the internal clock signal CK1 is large and the number of transistors passing through is large, so that the delay of the internal clock CK1 is large. Therefore, when the start signal ST is transferred from the additional circuit block BLKx to the circuit block BLK1 in the configuration of the first embodiment, the start signal ST may not be transferred normally due to a delay of the clock signal. This does not happen.

(Embodiment 3) Another configuration of the clock signal control circuit in Embodiments 1 and 2 will be described with reference to FIG. The clock signal control circuit CTRLi of the present embodiment shown in FIG. 6 is different from FIG. 2 in that a NAND gate 67 is added, an initialization signal INIT is input, and scan signals LR and / LR input to a control terminal of a clocked inverter. Are replaced.

Since the latch circuit constituting the shift register circuit used in the present invention is configured to apply a positive feedback, the output of the latch circuit may become active depending on the internal state when the power is turned on. In the first and second embodiments, the clock signal control circuit is opened and closed by using the output signal of a specific stage (latch circuit) in the shift register circuit. When the output of the circuit is active, the supply of the clock signal to the previous circuit block is cut off. As a result, signal scanning is not performed in the shift register circuit of the circuit block.

In order to avoid the above problem, it is necessary to inactivate the outputs of all the latch circuits at least when the power is turned on. In this configuration, the clock signal can be supplied to all the latch circuits regardless of the state of the set terminal S and the reset terminal R by inputting the initialization signal INIT when the power is turned on. By scanning the start signal in this state, the outputs of all the latch circuits become inactive after one scanning period. As a result, in the subsequent scanning period, even if the operations described in the first and second embodiments are performed, the above-described problem can be prevented.

(Embodiment 4) An active matrix image display device according to a fourth embodiment of the present invention will be described.

The image display device according to the present embodiment is the same as that of the first or second embodiment described above in at least one of the data signal line driving circuit SDa and the scanning signal line driving circuit GDa in the active matrix type liquid crystal display device shown in FIG. This uses a shift register circuit.

As for the operation, the shift register circuit is divided into circuit blocks and selectively operated, so that the effect of reducing power consumption is obtained and at the same time the scan signal L is obtained.
By changing the state of R, left-right inversion and up-down inversion can be performed. Therefore, when the present invention is applied to a display-integrated video camera, normal display and mirror image display can be switched.When the present invention is applied to a projection, the display can be installed as a normal floor-standing device and suspended from the ceiling. Can be installed.

In addition, these driving circuits may be formed by using ICs (integrated circuits) using single crystal silicon and externally connected to the liquid crystal panel ARY. The liquid crystal panel ARY may be formed over the same substrate. In this case, the effect is remarkable as described in the first embodiment.

[0087]

As described above, according to the present invention, a clock signal is sequentially supplied only to a circuit block in the shift register circuit which requires a transfer operation, so that this clock signal is supplied to the entire shift register circuit. compared,
The power consumed by the parasitic capacitance of the signal line and the gate capacitance of the latch circuit can be significantly reduced. In addition, since the supply of the clock signal to each circuit block can be controlled by the output signals of the preceding and following circuit blocks, the scale of the shift register circuit does not increase. Furthermore, since the present invention is also applicable to bidirectional transfer operations, when the present invention is applied to a display-integrated video camera, normal display and mirror image display can be switched, and the present invention is applied to projection. In this case, it can be installed on a normal floor, or installed on a ceiling. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a shift register circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a clock signal control circuit according to the present invention.

FIG. 3 is a time chart illustrating an operation of the shift register circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a shift register circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of an additional clock signal control circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a clock signal control circuit according to a third embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of an active matrix image display device according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional shift register circuit.

FIG. 9 is a block diagram showing a configuration of a latch circuit forming a conventional shift register circuit.

FIG. 10 is a block diagram illustrating a configuration of a conventional active matrix liquid crystal display device.

FIG. 11 is a block diagram illustrating a configuration of a data signal line driving circuit of a conventional image display device.

FIG. 12 is a diagram showing a configuration of a pixel of a conventional active matrix type liquid crystal display device.

FIG. 13 is a block diagram illustrating a configuration of a bidirectional shift register circuit.

FIG. 14 is a block diagram illustrating a configuration of a latch circuit included in the bidirectional shift register circuit.

FIG. 15 is a time chart of two stages of latch circuits.

[Explanation of symbols]

 SD Data signal line drive circuit GD Scan signal line drive circuit SPS Start signal of data signal line drive circuit SPG Start signal of scan signal line drive circuit CKS Clock signal of data signal line drive circuit CKG Clock signal of scan signal line drive circuit SL Data Signal line GL Scan signal line CTRL Clock signal control circuit BLK Circuit block ST Start signal ASW Analog switch CK Clock signal LT Latch circuit OUT Output signal LR Scan signal SBi Select signal S Set terminal R Reset terminal CKi Internal clock signal

────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI G11C 19/00 G11C 19/00 C J (56) References JP-A-5-72992 (JP, A) JP-A-7-248741 (JP, A) JP-A-8-16087 (JP, A) JP-A-59-69793 (JP, A) JP-A-8-329696 (JP, A) JP-A-8-30239 (JP, A) ( 58) Surveyed field (Int.Cl. ⁷ , DB name) G09G 3/00-3/38 G11C 19/00-19/28 G02F 1/133 505-580

Claims (11)

(57) [Claims] 1. A circuit block comprising a plurality of serially connected latch circuits for outputting a signal corresponding to an input signal based on a clock signal, and a clock signal control circuit for supplying a clock signal to a latch circuit of each circuit block. And said
Each latch circuit makes the rise and fall of the clock signal
Latch the start signal of the previous stage in sequence
Transfer and output signals of each latch circuit
The shift register circuit according to the active state by the period of one cycle of the item, in the shift register circuit capable of transferring the start signal bidirectionally, the set terminal of the clock signal control circuit, it Yes
To the circuit block immediately before the corresponding circuit block.
Of the output of each latch circuit before the second stage from the last stage
Are connected, and the resetting of each of the clock signal control circuits is performed.
One of the circuit blocks corresponding to each
Of the outputs of each latch circuit in the subsequent circuit block,
The outputs of the second and subsequent stages are connected, and each of the clock signal control circuits controls the transfer method of the start signal.
The set terminal based on a scan signal for determining a direction
After the input becomes active, the reset terminal
Supply clock signal or reset until active.
After the set terminal input becomes active,
Clock signal until the child input becomes active
A shift register circuit for controlling whether to supply the shift register. 2. A signal according to an input signal based on a clock signal.
Circuit block with multiple latch circuits that output signals
Clock and the latch circuit of each circuit block.
A clock signal control circuit for supplying a clock signal,
Each latch circuit makes the rise and fall of the clock signal
Latch the start signal of the previous stage in sequence
Transfer and output signals of each latch circuit
Shift register that activates each period of the signal
A starter circuit for transferring the start signal bidirectionally.
In the shift register circuit, the set terminals of the respective clock signal control circuits may be respectively provided.
To the circuit block immediately before the corresponding circuit block.
Of the output of each latch circuit before the second stage from the last stage
Are connected, and the resetting of each of the clock signal control circuits is performed.
One of the circuit blocks corresponding to each
Of the outputs of each latch circuit in the subsequent circuit block,
The outputs of the second and subsequent stages are connected, and each of the clock signal control circuits controls the transfer method of the start signal.
When the scan signal for determining the direction is active,
After the reset terminal input becomes active,
Clock signal is supplied until the terminal becomes active
When the scan signal is inactive,
After the input of the set terminal becomes active,
Until the input becomes active, the clock signal is
And a shift register circuit. 3. A circuit corresponding to the clock signal control circuit.
The output signal of the circuit block preceding the block is
This is the output of the second-stage latch circuit.
Output signal is the output of the second-stage latch circuit
3. The shift register according to claim 1, wherein:
circuit. 4. An adjacent circuit block is provided at both ends of a shift register.
Additional circuit that controls the stop of clock signal supply to the lock
3. The device according to claim 1, further comprising a block.
3. The shift register circuit according to 3. 5. A start signal for a shift register circuit,
Input between the additional circuit block and the circuit block
5. The shift register circuit according to claim 4, wherein: 6. A start signal of said additional circuit block.
The additional circuit block on the input side
The shift register according to claim 4, wherein the shift register is stopped.
Star circuit. 7. The additional circuit block includes two or more stages.
5. The switch according to claim 4, wherein the switches are connected in series.
Shift register circuit. 8. The circuit according to claim 8, wherein said clock signal control circuit comprises a circuit block.
Logic circuit that supplies a clock signal to the latch circuit in the
Path, and an initialization signal is input to the logic circuit.
The shift register circuit according to claim 4, wherein: 9. A transistor element constituting said latch circuit.
The element uses a polycrystalline silicon thin film
Item 9. The shift register circuit according to any one of Items 1 to 8. 10. A plurality of pixels arranged in a matrix,
A plurality of data signals arranged corresponding to each column of the pixel;
A predetermined timing signal to the plurality of data signal lines.
Data signal line drive to output video signal data sequentially
A circuit, a scanning signal line arranged corresponding to each row of the pixel,
The plurality of scanning signal lines are synchronized with a predetermined timing signal.
A scanning signal line driving circuit that outputs a sequential scanning signal;
Each data is synchronized with the scanning signal supplied from the scanning signal line.
A video signal for image display is supplied to each pixel from the signal line.
Matrix image table with liquid crystal panel
Display device, the data signal line driving circuit or the scanning signal line driving circuit
The shift register according to any one of claims 1 to 9.
An image display device using a star circuit. 11. The data signal line driving circuit and scanning signal
Circuit that constitutes at least one of the line driver circuits.
The circuit element forms pixels on a substrate constituting the liquid crystal panel.
The device must be formed by the same process as the device to be formed.
The image display device according to claim 10, wherein: