JP3325072B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to semiconductor devices and process technology, and more particularly, to semiconductor memories.

[0002]

2. Description of the Related Art Planar transistors are often used to manufacture integrated circuit memory devices, such as static random access memories (SRAMs).
The planar transistor has a diffusion source electrode and a drain electrode separated by a channel region. Over the channel region lies a gate electrode separated from the channel region by a gate oxide film. Although planar transistors are used and useful in many integrated circuit memory applications, they are area or area intensive and consume a large amount of substrate area per transistor. Moreover, as integrated circuit dimensions are reduced to the sub-micron range, planar transistors have various disadvantages. At smaller geometries and thinner gate oxide thicknesses, well-documented problems such as hot carrier injection, leakage current, isolation, short channel effects, and channel length variations are predominant in planar transistors. Problem.

To overcome some of the above mentioned disadvantages of planar transistors, thin film transistors (TFTs), elevated source and drain transistors, lightly doped drain (LDD) transistors and other improvements have been developed. Although these improvements reduce some of the disadvantages described above, the improvements have some undesirable properties. The main undesired characteristic is that the improved transistor is in most cases as area-intensive as the planar transistor, or even more area-intensive than the planar transistor, or, in the case of a TFT, a planar transistor. Similarly, it does not operate. For example, a small memory cell area can be obtained by using a TFT.
The fact is that FT is highly resistant and therefore not suitable for all applications.

[0004]

Various approaches have been used to reduce some of the above mentioned adverse effects while at the same time reducing circuit surface area and increasing transistor packing density. Surrounding gate transistors (SGTs) have been developed, and spacer gates and planar diffusions have been used to form the transistors. The SGT has reduced some of the disadvantages affecting the planar transistor and reduced surface area with a vertically arranged spacer gate. SGT distribution topography problems and geometries cause source, gate and drain contacts that are usually difficult to achieve and difficult to manufacture consistently using sub-micron technology. ing. In addition, the doping of the source, drain, and channel regions by implantation can be difficult due to geometry and requires special processing.

[0005] Traditional planar transistors and TF
T technology is currently available in 64Mbit SRAM or 256Mbit
No progress has been made at speeds that allow the formation of large numbers of memory cells, such as bit SRAMs.

[0006]

SUMMARY OF THE INVENTION The above-mentioned disadvantages are overcome by the present invention and other advantages are obtained. The invention comprises a memory device. The memory device includes a substrate having one surface. A first vertical structure is formed to at least partially lie on a surface of the substrate. The first vertical structure has a first vertical transistor underlying a second semiconductor device. A second vertical structure is formed at least partially overlying a surface of the substrate and is formed laterally adjacent to the first vertical structure. The second vertical structure has a second vertical transistor underlying the second semiconductor device. An electrical interconnect is provided between the first and second vertical transistors and the first and second vertical transistors.
And a second semiconductor device to form the memory device.

[0007] The invention will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings.

[0008]

FIG. 1 shows a structure suitable for forming a transistor 10. FIG. Transistor 10 has a base layer, which is a substrate 12 having one surface and having a first conductivity type. If the transistor 10 represents a first transistor formed overlying a second transistor (not shown), the base layer for the first transistor may be conductive of the underlying second transistor. Head layer or head electrode. Substrate 12 can be made from silicon, gallium arsenide, silicon on sapphire, epitaxially formed, germanium, germanium silicon, polycrystalline silicon, diamond, silicon on insulator (SOI), and / or similar substrate materials. Preferably, substrate 12 is formed from silicon. Diffusion 14 is formed in substrate 12.
Various methods can be used to form the diffusion 14. These methods are described below. A first dielectric layer 16 is formed overlying the substrate 12 and initially overlying the diffusion 14. A control electrode conductive layer 18 is formed on the dielectric layer 16. In a preferred form, conductive layer 18 is polycrystalline silicon, but conductive layer 18 is a metal,
Salicide or silicide, germanium silicon,
Polycide or others may be used. Second dielectric layer 20 is formed overlying conductive layer 18.

[0009] The dielectric layers 16 and 20, and all other dielectrics described herein, can vary in physical and chemical composition based on the function they perform. The dielectric layer described herein may be wet or dry silicon dioxide (Si).
O ₂ ), nitride, silicon nitride, oxide based on tetraethylorthosilicate (TEOS), borophosphate silicate glass (BPSG), phosphate silicate glass (PSG), borosilicate glass (BSG), oxide Nitride-oxide (ONO), 5
Tantalum oxide, plasma enhanced silicon nitride _(P-S i N
_x ), titanium oxide, and / or the like. Certain dielectrics are noted when a particular dielectric is preferred or required.

Referring to FIG. 1, a masking layer of photoresist (not shown) is deposited over dielectric layer 20. The masking layer (not shown) is patterned and etched in a conventional manner to form a mask opening exposing a portion of the dielectric layer 20. A portion of the dielectric layer 20 is selectively etched into the conductive layer 18 to form an opening in the dielectric layer 20. A part of the conductive layer 18 is selectively etched into the dielectric layer 16 and the opening is deepened by etching into the conductive layer 18. A portion of the dielectric layer 16 is selectively etched into the substrate 12 to further deepen the opening by etching into the dielectric layer 16. Etching of dielectric layer 16 exposes diffusion 14. Etching of dielectric layers 16 and 20 and control electrode conductive layer 18 results in openings that are self-aligned to the mask openings. The opening may in some cases be referred to as a "device opening".
ng) ". In another form, a non-selective etching process can be used to form the device openings.

In FIG. 1, the diffusion 14 is formed by one of at least two methods. In one form, diffusion 14 comprises a photoresist mask, an oxide mask,
It can be selectively implanted or diffused into the substrate by using one of a nitride mask or the like. Similarly, diffusion 14 can be implanted through an oxide or similar material to ensure a shallow, dopant-dispersed junction. This implantation or diffusion is performed before the formation of the conductive layer 18. In a second method, the diffusion 14 can be implanted or diffused after forming the device opening.
The second approach is to use the resulting diffusion 14
Are preferred due to the fact that they are self-aligned to the device or mask openings. Spread 14
May be either N-type or P-type and may include a plurality of dopant atoms (eg, phosphorus and arsenic). The device openings can be of any shape or size, but are preferably circular or square contacts of the smallest lithographic size (on the order of 0.5 microns or less).

FIG. 2 shows the step of forming the sidewall dielectric layer 22. Sidewall dielectric layer 22 is formed on the sidewalls of conductive layer 18 resulting from the formation of the opening. Dielectric by the fact that functions as a gate oxide film, a S _i O ₂ layer dielectric layer 22, which is most cases growth. Growth of dielectric layer 22 results in thin dielectric layer 24 growing on the exposed surface of diffusion 14.

The formation of dielectric layer 24 is an undesirable side effect. Accordingly, FIG. 3 illustrates a dielectric removal step for a portion of the dielectric layer 24. A cylindrical dielectric spacer 26 or similar formation is formed over dielectric layer 24 and adjacent dielectric layer 22. Preferably, spacer 26
Is an oxide that can be selectively etched into nitride or SiO ₂ , is cylindrical in shape, and is formed in and adjacent to the sidewall of the device opening. Spacer 26 forms an internal opening within the device opening. Spacers 26 are used to protect dielectric layer 22 from subsequent oxide etching. Next, an oxide etch is performed selectively on the spacer 26 and the substrate 12. The oxide etch removes portions of the dielectric layer 24 within the cylindrical dielectric spacer 26. The portion of the dielectric layer 24 below the spacer and surrounding the periphery of the opening remains unetched. Spacer 26 is then removed by traditional nitride or removable spacer technology.

In FIG. 4, first and second current electrodes, also referred to as drain and source, respectively, and a channel region are formed. In a preferred form, grown conductive regions are used to form said first and second current electrodes and channel regions. Preferably, the grown conductive region is formed by epitaxial growth of a base layer of the material.

Transistor 10 is placed in one piece of equipment suitable for epitaxial growth. Heating transistor 10 and exposing diffusion 14 or exposed portions of substrate 12 to dichlorosilane
Alternatively, growth is initiated by exposure to a compound such as a silicon source gas.

First, a first current or drain electrode 28 is formed in the device opening. The electrode 28 is formed of a second conductivity type opposite to the first conductivity type. In order to dope the drain electrode 28 with dopant atoms of the second conductivity type, ion implantation is possible, but in-situ doping is preferred. In situ doping means that the drain electrode 28 is doped by a dopant gas source during growth. If the second conductivity type is P-type, a boron-containing gas or similar dopant gas will
8 used to dope. If the second conductivity type is N-type, a phosphorus-containing, arsenic-containing, or similar dopant gas is used to dope electrode 28. The drain electrode 28 is grown by in-situ doping until the drain electrode 28 is adjacent or nearly adjacent to the bottom of the sidewall dielectric layer 22 as shown in FIG. Is done.
Lightly doped drain (LDD) region or graded drain
The doping profile can be formed by changing the concentration of in-situ doping.

Epitaxial growth is performed in the same manner to form a channel region 30. Channel region 30 is preferably formed by in-situ doping as described herein.
It is formed of the first conductivity type. Due to the fact that the dielectric layer 22 is a gate oxide and the conductive layer 18 acts as a gate, doping in the channel region 30 can be used to adjust the threshold voltage. The channel region is grown by in-situ doping until the electrode is adjacent or nearly adjacent to the top of the sidewall electrode 22, as shown in FIG.

Epitaxial growth continues in a similar manner to form a second current electrode, also referred to as a source electrode, of a second conductivity type. The second current electrode has two sub-regions. These two sub-regions are lightly doped.
doped electrode 32 and heavily doped
y doped) electrode 34. Electrodes 32 and 34
Is formed by changing the concentration of in-situ doping during growth. First, the doping gas of the second conductivity type is set to a predetermined concentration. After a predetermined time, and thus a predetermined epitaxial growth thickness, a lightly doped electrode 32 is formed and the dopant concentration is increased to a second predetermined level. While maintaining the second predetermined level, epitaxial growth is continued to form heavily doped electrode.

It is convenient to have a transistor with a half lightly doped drain (LDD) structure as shown in FIG. Generally, the LDD region causes an increase in series resistance. If an LDD region can be formed only at the source electrode where it is most needed, the advantages of the LDD configuration can be maintained while reducing series resistance. It should be noted that the source and drain regions are interchangeable in the structure of FIG. If the function of source and drain is switched (ie,
If the source is formed below the channel region 30 and the drain is formed above the channel region 30), an LDD structure can be formed for the lower electrode. It is also clear that a full LDD transistor can be formed by forming the LDD region for both the source and the drain. It is important to note that the LDD regions are optional and the doping for both the source and drain regions can be constant.

Also, epitaxial growth requires a clean surface, so a cleaning cycle is performed before starting growth, such as a traditional RCA oxidation clean, Ishizaka-Shiraki clean, or equivalent cleaning cycle. Further, a thin film transistor (TFT) can be formed by the above-described epitaxial method. If the substrate 12 is polycrystalline silicon instead of monocrystalline silicon, the polycrystalline silicon electrode and channel regions are grown epitaxially. This growth is achieved by a vertical TF having the same structure as the transistor 10 of FIG.
Form T. Vertical TFTs are useful for saving area in memory cell design.

It is important to note that the formation of the opening in FIG. 1 can be used to form a multi-gate transistor having a plurality of gate electrodes. A plurality of gate electrodes, or where N is an integer, the N gates are formed by one of two methods. A first method includes forming a gate conductive layer, lithographically masking the gate conductive layer, and etching to form N physically separate distinguishable gates. In this method, photolithographic alignment with the device aperture is important and therefore this method is not preferred. A preferred method is to form the gate conductive layer as a single region or layer and utilize the formation of device openings to separate the single gate conductive layer into N conductive gate regions. This method ensures that all gates are self-aligned to the device opening. FIG. 5 shows, in one form, a top perspective view of the gate conductive layer 18 and the device opening 21 used to etch the layer 18 into N self-aligned gates, where N Is 4.

In FIG. 4, the dielectric layer 24 remaining around the device opening is an epitaxial seeding region for subsequent epitaxial growth.
eding area). Therefore, FIG.
FIG. 4 shows another method that can be used in place of the steps of FIGS. 2-3 and achieves a larger epitaxial seeding area. When the dielectric layers 16 and 20 and the conductive layer 18 are etched to form the opening, the etching of the dielectric layer 20, the subsequent etching of the conductive layer 18, and the subsequent etching of the dielectric layer 16 are usually performed. Used to expose substrate 12 and to self-align various features of transistor 10. If an overetch or isotropic etch occurs during the etching of conductive layer 18, conductive layer 18 is etched laterally and has a “cave” having sides defined by dielectric layers 16 and 20. ". With the conductive layer 18 recessed from the side wall of the opening, a dielectric layer 22 'can be formed as shown in FIG. The formation of dielectric layer 22 'forms a surface dielectric layer (not shown) overlying diffusion 14 which can be removed. The difference is that spacers are no longer needed. Reactive ion etch (R
IE) may be performed to completely remove the surface dielectric layer from the surface of the diffusion 14 without affecting the recessed dielectric layer 22 '.

If the dielectric layer 22 'is formed such that a portion of the "cave" still remains, an optional dielectric spacer 22 "may extend laterally into the opening as shown in FIG. And the dielectric layer 22 "is preferably formed from a TOES-based oxide. The spacers are then RIE etched to form a polysilicon grown SiO ₂ layer adjacent to the conductive layer 18 and a TOES adjacent to the polysilicon grown SiO ₂ layer.
The dielectric layer 22 "is formed as a composite dielectric having an oxide layer based on the composite oxide layer. This composite oxide formation provides micro-holes in the dielectric layer 22 'to create an improved gate dielectric layer. Used to misalign micropores (ie, defects).

In addition, during the RIE etch, a plasma damage can result in the dielectric layer 22 '. Due to the fact that the dielectric layer 22 'functions as a gate oxide, the dielectric layer 22' must be of good quality. Therefore, to avoid or reduce plasma damage during the RIE etch,
The dielectric layer 22 'is nitrided by conventional _{N 2, N 2 O, NH} 3 or equivalent. Nitride oxide materials are more resistant to plasma damage than other oxide materials. Nitride oxide is convenient but optional for transistor 10.

Both N-channel and P-channel transistors can be formed. If the first conductivity type is N-type and the second conductivity type is P-type, a P-channel vertical transistor is formed. If the first conductivity type is P-type and the second conductivity type is N-type, an N-channel vertical transistor is formed.

In most cases, the transistor 10 of FIG.
Will have the conductive layer 18 completely surrounding the channel region 30. Fully encircling conductive layer 18 allows for maximum current carrying capability, more consistent aspect ratio (transistor width / transistor length ratio), and reliable photolithographic alignment. In other cases, high packing density can be achieved by partially surrounding channel region 30 with conductive layer 18. This high packing density is achieved by avoiding space requirements between conductors for most polysilicon and metal design rules.

Transistor 10 can be used to form vertically stacked vertical transistors. These vertically stacked vertical transistors can then be used to form very small static random access memory (SRAM) cells. All transistors used to fabricate micro SRAM cells have sidewall dielectric formation, LDD regions, doping profiles, diffusion,
It can have all the flexibility described above for transistor 10 with respect to oxides and the like. Other vertical transistors exist and can be used in the embodiments proposed herein.

The transistor 10 is different from the other transistors 10
A memory cell having a surface area of about 1 micron stacked vertically on the head of the memory cell can be realized. For example,
If a lithographic feature size or feature size of 0.25 microns is used and the minimum spacing between lines is on the order of 0.25 microns, a 1 micron square cell can be realized. If a line width of 0.4 microns is used and the minimum spacing between lines is on the order of 0.4 microns, a roughly 2.5 square micron cell can be achieved. Contact or device openings are typically sub-micron in size. If 0.
If a line width of 5 microns is used and the minimum spacing between lines is on the order of 0.5 microns, a roughly 4 square micron cell can be achieved. 7 to 14, a plurality of M vertical transistors, where M is an integer equal to 2, are stacked on each other. Each stacked transistor can independently be an N-channel or P-channel device. P-channel means that the transistor has p-type doped source and drain regions. N-channel means that the transistor has N-type doped source and drain regions. Each stacked transistor has 1 to N conductive gates, where N can be different between each of the M stacked transistors.

In the stack of M transistors, the second current electrode, or top electrode, of the bottom transistor is connected to the first current electrode, or bottom electrode, of the overlying transistor. With this connection mechanism, the P-type region will in some cases come into contact with the N-type region and
Create an N-junction. Salicide, metal, to avoid diode voltage drop across the PN junction
Silicide or other material is used to electrically short the PN junction.

In FIGS. 7-14, elements similar to those of FIGS. 1-5 are numbered the same for simplicity and will not be described in detail. Elements of FIGS. 7-14 that are similar to elements of FIGS. 1-5 should be capable of all of the changes and modifications described herein with respect to FIGS. FIG. 7 is substantially equivalent to FIGS. 1 and 2 and the formation of the dielectric layers 16, 20 and 27, the conductive layers 18, 19
2 and 25, the formation of a device opening exposing the substrate 12, the formation of the sidewall dielectric 22 and the dielectric layer 24, and the formation of the diffusion 14.

It is important to describe the layers and regions of FIG. 7 that are different from FIGS. Conductive layers 18 and 1
9 is formed from a single conductive layer in a manner similar to that shown in FIG. Conductive layer 25 is formed overlying dielectric layer 20 and functions as an output conductor. Further, dielectric layer 27 is formed so as to overlie conductive layer 25. Conductive layers 18 and 19 form a first conductive gate electrode and a second conductive gate electrode, respectively. Therefore,
The transistor formed in the device opening and adjacent to the conductive layers 18 and 19 is of a double gate type. It is important to note that conductive layers 18 and 19 can be formed collectively as a single gate in FIG.

Referring to FIG. 8, the previously described sidewall dielectric method utilizing spacers 26 for protection is illustrated. The recessed sidewall approach proposed herein in FIG. 6 is a viable replacement for the spacer approach of FIG. 8 and vice versa. In FIG. 8, a part of the dielectric layer 25 has been removed.

In FIG. 9, the conductive region has the same channel region and electrode region as in FIG. 4, and is formed in the device opening. FIG. 9 shows a half LDD structure. The method of forming electrodes and channel regions by epitaxial growth is described in detail with reference to FIG. As previously mentioned, the conductive regions forming the electrodes and the channel region can optionally be formed with a full LDD structure or a structure without an LDD region. The conductive regions and layers 18 and 19 form a first transistor.

In FIG. 10, a part of the dielectric layer 27 is removed to expose a part of the conductive layer 25. A short epitaxial growth step or deposition and etching procedure is used to form an electrical contact between conductive layer 25 and heavily doped electrode. Preferably, a short (bri
ef) The epitaxial growth step links the conductive layer 25 to the highly doped region 34 via the epitaxial link layer 36. Sidewall contacts, other forms of epitaxial growth, deposition and etching procedures, etc. can be used to form a link layer similar to layer 36.

Referring to FIG. 11, dielectric layers 38 and 42
Then, a conductive layer 40 is formed to enable the formation of the second transistor. The second transistor overlies the first transistor, which is gated by conductive layers 18 and 19. The second transistor uses a highly doped electrode 34 as a base layer. The base layer provides an epitaxial quality material for the formation of the overlying second transistor. Dielectric layers 38 and 42 and conductive layer 40 are formed in a manner similar to that described in FIG.

In FIG. 12, a second device opening, or second opening, is formed by dielectric layers 38 and 42 and conductive layer 4
0. Sidewall dielectric 44 is formed in a manner similar to that described with respect to FIGS. The second transistor is single gated by conductor 40. The conductor 40 completely surrounds the periphery of the second opening, or partially surrounds the periphery of the second opening. The dielectric layer 46 is shown in FIG.
Is formed overlying the highly doped electrode 34 during formation of the sidewall dielectric layer 44.

FIG. 13 shows a side wall spacer and dielectric removing step similar to FIG. The dielectric layer 46 not under the spacer is removed. In FIG. 14, a second conductive region is formed, which has a first current electrode 50, a channel region 52 and sub-regions referred to as a lightly doped drain region 54 and a highly doped drain region 56. A second current electrode.

A plurality of structures similar to the structure shown in FIG. 14 can be connected as taught below to form a micro SRAM cell.

FIGS. 15-20 illustrate another method for forming a vertically integrated vertical transistor structure according to the present invention. 7 to 14 show a technique in which stacked transistors are formed one transistor at a time and without self-alignment. 15 to 20 show a method in which a plurality of transistors are formed in a stack and the transistors are self-aligned with each other. The vertical CMOS logic gate described herein can use either the self-aligned method or the non-self-aligned method. The vertical SRAM cell described here can use either a self-aligned method or a non-self-aligned method.

In FIG. 15, the substrate 12 and the diffusion 14
Is shown again. The same regions and layers as those in FIGS. 1 to 14 are given the same numbers in FIGS. 15 to 20. Conductive layers 60, 64 and 68 and dielectric layers 58,
62, 66 and 70 are formed so as to lie on the substrate 12 as shown. Dielectric layers 58, 62, 66
And 70 are shown as flat. Although planarization is shown, it is not required for functionally stacked devices. Planarization improves terrain and topography in overlying conductive layers, such as metal layers.
reduce the problem. If no planarization method is used, the "volcano-s
happed) stacked logic device is created.

In FIG. 16, device openings or openings are formed. The opening has side walls and the conductive layer 6
0, 64 and 68 and the dielectric layers 58, 62, 66
And 70 are formed by etching a part thereof. During the etching of the conductive layers 60, 64 and 68,
The conductive layers 60, 64 and 68 are over-etched to laterally recess the sidewalls of the openings adjacent to the conductive layers 60, 64 and 68 as shown in FIG. This indentation causes the laterally indented sidewall dielectric layer 72 to be formed simultaneously with the formation of the dielectric layer 74. Due to the fact that the dielectric layer 72 is recessed, the dielectric layer 74 is etched without affecting the dielectric layer 72 as described herein.

Diffusion 14 is, in one form, shown in FIG.
5, is formed on the substrate 12 before or during the formation of the conductive layers 60, 64 and 68 and the dielectric layers 58, 62, 66 and 70. In a preferred form, the diffusion 14 is formed self-aligned to the opening as shown in FIG. In FIG.
All transistors stacked on top of each other are self-aligned with each other. Thus, FIG. 16 illustrates a completely self-aligned process that can be used to form an SRAM cell.

In FIG. 17, one of the first and second transistors is formed on the other head. FIG. 17 illustrates the use of a full LDD transistor. The first transistor comprises a lightly doped region 76 and a heavily doped region 74.
And a first current electrode having The first transistor has a channel region 78. The first transistor has a second current electrode having a lightly doped region 80 and a heavily doped region 82. The second transistor has a first current electrode having a lightly doped region 86 and a heavily doped region 84. The second transistor has a channel region 88. The second transistor has a second current electrode having a lightly doped region 90 and a heavily doped region 92. The dielectric layer 94 protects the highly doped region 92 from subsequent etching processes and damage. The heavily and lightly doped regions together form a single current electrode.

In an SRAM device, a diode voltage drop at a PN junction (typically 0.1 V to 0.9 V)
Should be avoided. Diode voltage drop is avoided by electrically shorting the PN junction with salicide, metal or similar material. FIG. 18 illustrates salicidation (sa) of a PN junction when a completely self-aligned process is used, such as the process shown in FIG.
Figure 4 shows a method that can be used for
An etching hole 96 is formed, exposing the conductive layer 64. An etching step is used to remove a portion of conductive layer 64 as shown in FIG. A short dielectric etch is used to remove sidewall dielectric 72 exposed by etching conductive layer 64. A masking layer 95, preferably a photoresist, is used to protect the dielectric layer 94. Removal of the exposed sidewall dielectric 72 exposes portions of the heavily doped regions 82 and 84.

In FIG. 19, the matching (conform
mal) CVD titanium or similar material is deposited and a salicide anneal is performed to form a salicidation region 97
Is formed. Effective short circuit is now highly doped region 8
Bridged between the PN junction formed by 2 and 84.

In FIG. 20, conductive regions 99 and 9
8 are formed to create an electrical contact to inverter gate 13. Region 98 forms the output contact of inverter gate 13 and region 99 forms the power connection. To make electrical contact, dielectric layer 94 is removed.

It is important to note that this salicide formation step in FIGS. 18-19 is difficult because it is performed in a process having a self-aligned stacked transistor. The process of FIGS. 7-14 is more suitable for the salicide formation step due to the fact that one transistor is formed at a time. A salicide region can be formed over the heavily doped region of the first transistor before the heavily doped region of the second transistor is formed by traditional deposition, etching and annealing cycles, thereby obtaining Electrically short the PN junction. The only disadvantage with this approach is that the resulting salicide region, if formed over a large surface region of the highly doped region, will prevent epitaxial growth of the conductive region. Deciding to use one method over the other is a design choice and depends on the application of the device, the equipment available, and the capabilities of the equipment.

If a plurality of structures similar to the structure shown by FIG. 20 are electrically connected and doped in a suitable manner, one SRAM cell or multiple SRA
An M cell can be manufactured as follows.

In FIG. 21, the structure of FIG. 20 is shown in a head perspective view. Only the conductive layers 60, 64 and 68 are shown with an opening shown as opening 73 in FIG.

FIG. 22 shows a circuit diagram of a conventional SRAM cell. FIG. 22 shows N-type latch transistors 100 and 1
02, N-type pass transistors 104 and 106 and resistive devices 108 and 110 are shown. Interconnect 118
Replaces transistors 104 and 100 with transistor 10
2 gate. Interconnect 120 connects transistors 102 and 106 to the gate of transistor 100. The resistance devices 108 and 110 may be resistance elements, diodes, thin film transistors (TFTs), P-type transistors, and the like. If resistor devices 108 and 110 are transistor devices, interconnect 118 connects to the gate of resistor device 110 and interconnect 120 connects to the gate of resistor device 108. The power supply (Vdd) and ground connections are shown in FIG. Bit lines 114 and 116 and word line 112 are shown. FIG. 22 also shows transistor nodes 101 and 103.

FIG. 23 shows a top perspective view of a layout that can be used to form an SRAM cell according to the present invention. The vertical transistor stack 124 includes two transistors and is dimensionally one lithographic line width (fea).
cure). The vertical transistor stack 124 is formed using the technique shown in FIGS.
FIG. 14 or FIG.
Is the same as The two stacked transistors are similar to transistors 102 and 106 of FIG. Transistor 102 is formed below transistor 106 in this embodiment. The vertical transistor stack 122 includes two transistors and is one lithographic linewidth in size. Vertical transistor stack 12
2 is formed using the technique shown in FIGS. 1-21 and includes two stacked vertical transistors (same as FIG. 14 or FIG. 20). FIG. 22 shows two stacked transistors.
Of the transistors 100 and 104 of FIG. The transistor 100 is a transistor 104 in this embodiment.
Formed underneath.

In FIG. 23, interconnect 118 connects transistor node 101 (see FIG. 22) lying between transistors 100 and 104 in vertical transistor stack 122 to the gate of transistor 102 located in vertical transistor stack 124. . FIG.
In, the interconnect 118 is preferably formed from polysilicon or a similar conductor or semiconductor. Interconnect 120 connects transistor node 103 (see FIG. 22) between transistors 102 and 106 in vertical transistor stack 124 to the gate of transistor 100 located in vertical transistor stack 122. In FIG. 23, interconnect 120 is preferably formed from polysilicon or a similar conductor or semiconductor. Interconnects 118 and 120 are connected between vertical transistor stacks 122 and 124 via vertical stacks 126 and 128, respectively. The interconnects 118 and 120 are similar to the connecting conductive layer 25 of the first transistor stack formed according to FIG. 14 to the conductive layer 18 of the second transistor stack formed according to FIG. Interconnects 118 and 120 are shown in later cross-sectional views (FIGS. 24-26).

The word line 112 is shown in FIG.
The word lines 112 are, for example, each similar to the conductive layer 60 of FIG. Diffusion (not shown) is shown on line 24 in FIG.
Conducts ground potential along -24 and connects to the bottom of each of vertical transistor stacks 122 and 124. This diffusion (not shown) may be a straight diagonal diffusion or a zigzag geometry. Further, the diffusions shown herein may be salicided or silicided. A buried silicide or salicide layer can be formed in the diffusion using an ion implantation step of implanting a refractory metal material, such as cobalt. Other silicide / salicide metals and materials also exist. Silicide and / or salicide form a larger conductive diffusion.

The vertical stack 126 corresponds to the resistance device 1 shown in FIG.
08 including a resistive or TFT device. The vertical stack 126 includes a resistor or TFT device similar to the resistor device 110 of FIG. These TFTs or resistor devices are connected to power conductors (not shown in FIG. 23) at the top of the vertical stacks 126 and 128. These connections are shown in more detail in FIGS.

FIG. 24 shows FIG. 23 along line 24-24.
FIG. FIG. 24 shows the vertical transistor stacks 122 and 124 of FIG. In FIG. 24,
Vertical transistor stack 122 holds transistor 100 of FIG. 22 and transistor 104 of FIG. 22 as shown. The vertical transistor stack is similar to the structure of FIG. 14 or FIG. 20 and therefore like elements of FIG. 24 are numbered the same as in FIG. The diffusion 14 transmits a ground (Vss) signal.

The vertical transistor stack 124 is structurally similar to the vertical transistor stack 12 of FIGS.
2 and therefore are not specifically numbered. Vertical transistor stack 124 is used to form transistors 102 and 106 of FIG. The conductive layer 40 of FIG. 24 forms the word line 112 shown in FIG. Interconnects 118 and 12 of FIG.
0 is shown as the first and second polycrystalline silicon layers in FIG. Interconnect 120 connects transistors 102 and 106 to the gate of transistor 100 via a connection in vertical stack 128. Interconnect 118 connects transistors 100 and 104 to the gate of transistor 102 via a connection in vertical stack 126.

The vertical transistor stacks 124 and 1
22 can be formed simultaneously. All four transistors 100, 102, 104 and 106 are N-type and therefore do not require the silicide electrical short circuit area shown in FIG.

FIG. 25 is a sectional view of FIG.
FIG. Vertical transistor stack 1 of FIG.
22, and the vertical stack 128 of FIG. 23 is shown. The transistor stack 122 of FIG. 25 is the same vertical transistor stack shown in FIG. The only difference is the vertical transistor stack 12 of FIG.
2 is in a different direction (line 2 instead of lines 24-24)
5-25) is a sectional view.

In FIG. 25, a vertical stack 128 is shown. Interconnect 120 connects the gate of transistor 100 to transistors 102 and 106 (output node 103 in FIG. 22). A portion of the vertical stack 128 is used to vertically tie the two conductive layers together to form an interconnect 120 as shown in FIG. The head of the vertical stack 128 is used to form a resistance device 134 similar to the resistance device 110 of FIG. Preferably, the resistive device is a polycrystalline silicon resistive element or a resistive element formed from a resistive material. The resistive element may be doped, compensated or undoped. A conductive layer 136, preferably a metal material, connects the resistor device 134 to a power supply voltage (Vdd).

The resistive device 134 can be formed by a plug and planarization / etchback process, epitaxial growth, or the like. In another form, the resistor device 134 can be formed as a thin film transistor (TFT) or vertical polycrystalline transistor by the process shown in FIGS.

FIG. 26 shows FIG. 23 along line 26-26.
FIG. Vertical transistor stack 1 of FIG.
22 is shown and the vertical stack 126 of FIG.
It is shown. Vertical transistor stack 1 of FIG.
22 is the same vertical transistor stack 122 shown in FIG. The only difference is that the vertical transistor stack 122 of FIG. 26 is a cross-sectional view from a different direction (lines 26-26 instead of lines 24-24).

In FIG. 26, the vertical stack 126
It is shown. Interconnect 118 connects transistor 102
Are connected to transistors 100 and 104 (output node 101 in FIG. 22). Vertical stack 126
Are used to vertically connect the two conductive layers to form an interconnect 118 as shown in FIG. The head of the vertical stack 126 is the resistance device 1 of FIG.
08 to form a resistance device 138 similar to that of FIG. Preferably, the resistive device is a polycrystalline silicon resistive element or a resistive element formed from a resistive material. The resistive element may be doped, compensated or undoped. A conductive layer 136, preferably a metallic material, connects the resistor device 138 to a power supply voltage (Vdd).

The resistance device 138 includes a plug and a planarization (p
lanization / etchback treatment, epitaxial growth, or the like. In one embodiment, the resistor device 138 is a thin film transistor (TF) by the process shown in FIGS.
T) or as vertical polycrystalline silicon transistors.

Since the SRAM cell has been described above (FIGS. 23 to 26) and the method of forming the stacked transistor has been described (FIGS. 1 to 21), the method of manufacturing the SRAM of FIGS. 23 to 26 will be further described. FIG. 27 to FIG. 33 show a top-down processing flow of a device-critical layer for the SRAM device to perform the above operation. FIG.
Shows a first layout and FIGS. 27 to 33 show a second layout. Some of the dielectric layers, substrate layers, diffusions and other layers are not shown in FIGS. Only the conductive layers are shown in FIGS. 27-33 for clarity, and only one SRAM cell is fully numbered.

In FIG. 27, a substrate 12 is provided. Diffusions (not shown) are formed in substrate 12 to carry ground potential, other potentials, or logic signals as needed. The diffusion (not shown) is optionally salicided or silicided as taught herein. First
The dielectric layer (not shown) is formed corresponding to the dielectric layer 16 in FIG.

Polycrystalline silicon, polycide (polyc)
ide) or similar layer is formed and patterned to form a first conductive layer. The first conductive layer forms portions of interconnects 118 and 120 as shown. The doping of the first conductive layer is performed by in-situ doping, diffusion, ion implantation or the like.

In FIG. 28, a second dielectric layer (not shown) is formed corresponding to dielectric layer 20 in FIG. The planarization of the dielectric layer described herein is optional. Preferably polycrystalline silicon, amorphous silicon, polycide or similar material,
A second conductive layer is formed and patterned on the second dielectric layer (not shown). The second dielectric layer is used to form other portions of interconnects 118 and 120 as shown. Doping of the second conductive layer is performed by in-situ doping, diffusion, ion implantation or the like.

In FIG. 29, a third dielectric layer (not shown) is formed corresponding to the dielectric layer 38 of FIG. The planarization of the third dielectric layer (not shown) is optional. A third conductive layer, preferably of polysilicon, amorphous silicon, polycide, or a similar material, is formed and patterned over a second dielectric layer (not shown). The third dielectric layer is used to form the word lines of the SRAM cell similar to the conductive layer 40 of FIG. The doping of the third conductive layer is performed by in-situ doping, diffusion, ion implantation or the like.

In FIG. 30, contact holes are formed and vertical transistor stacks 122 and 12 are formed.
4 are formed as taught herein. All four transistors (transistors 100, 100) formed in vertical transistor stacks 122 and 124
Reference numerals 102, 104, and 106) denote vertical N-type transistors. For the formation of these four transistors, epitaxial growth is preferred, as disclosed herein. The vertical transistor stacks 122 and 124 can be formed sequentially or simultaneously.

In FIG. 31, contact holes are formed and vertical stacks 126 and 128 are formed as taught herein. Vertical stack 12
6 and 128 complete the electrical connection of interconnects 118 and 120. In addition, the heads of the vertical stacks 126 and 128 are used to form a resistance device similar to the resistance devices 134 and 138 of FIGS. The vertical stacks 126 and 128 can be formed sequentially or simultaneously.

In FIG. 32, the traditional interlevel (i
An inter-level dielectric (not numbered) is formed and a conductive layer 136 is formed to connect the heads of the vertical stacks 126 and 128 to the power supply potential (Vdd). The conductive layer 136 is preferably a metal layer.

In FIG. 33, a second traditional interlevel dielectric (not numbered) is formed and conductive layers 131 and 133 are formed to form the tops of the vertical transistor stacks 122 and 124. Connect.
Conductive layers 131 and 133 form a pair of bit lines for the SRAM cell. Typically, conductive layers 131 and 133 are formed on a single metal layer and carry complementary logic signals.

[0073]

The method and apparatus of the present invention proposed herein for forming an SRAM provides a vertical transistor logic and vertical circuit having reduced surface area, improved short channel operation, and reduced channel length variation. . The leakage current is reduced due to the fact that the current electrode and the channel region are separated from the substrate. The length of the transistor 10 is controlled by the thickness L of the conductive layer 18 as shown in FIG. Thus, the transistors of the present invention are lithographically independent, having gate and channel lengths that are smaller than lithographically possible and controlled within smaller variations. Further, the deposition thickness L,
And the small substrate surface area can be used to adjust the aspect ratio and device characteristics of the P-channel device to match the device characteristics of the N-channel.

Although the device width of the transistor used to form the memory device of the present invention taught herein is greater than a conventional planar transistor of the same surface area, the channel width of a cylindrical or cylindrical transistor is This is because it is the outer periphery of the cylinder. It should be noted that the contact holes taught herein need not be circular and may be triangular, square, elliptical, square or other shapes. Because of the smaller channel length and larger channel width, the current carrying capability of the present transistor logic can be increased without increasing the surface area of the logic circuit. In most cases, the surface area of the SRAM cell substrate will be less than 3 square microns and 1 square micron (sub-one sq.) For the SRAM cell technology disclosed herein.
uremicron).

The memory device of the present invention is lithographically formed in a contact hole having the smallest line width in an integrated circuit. Furthermore, the formation of the SRAM cell of the present invention only requires a few photolithographic steps if the SRAM is formed completely self-aligned as shown in FIGS. Even if each transistor is sequentially formed one at a time, the source electrode of the transistor,
All that is required for the formation of the drain electrode and the channel region is one mask. Many features of the transistors disclosed herein, such as diffusions and gates, can be self-aligned. Asymmetric source and drain electrodes are obtained and LDD and half L
DD transistors are easily formed. Bulk inversion of the channel region can be achieved for sub-micron channel region dimensions. Low logic off current, known crosstalk phenomena, and current leakage into the substrate are minimized due to the fact that many diffusions are placed in series and separated from the substrate.

The SRAM cell of the present invention avoids many polysilicon, silicon and metal junctions because the SRAM cell of the present invention has transistors that are physically closer together than conventional SRAM cell transistors. And high-speed operation can be performed.

In some cases, the SRAM of the present invention may be formed to have the transistor in an opening that is too large to be completely depleted or depleted. Completely depleted transistors and bulk inversion transistors are advantageous and are possible for the transistors disclosed herein if small lithographic shapes are achieved. Full channel area exhaustion or bulk channel inversion is also desirable for large geometry transistors to achieve improved performance. If sidewall contacts are made to the channel region of the transistor of the present invention and the sidewall contacts are connected to a substrate or power supply, depending on the device conductivity, improved depletion or depletion (de)
pletion) can be achieved. The sidewall contact is possible for a transistor gate region with a non-gate sidewall portion or for a logic gate having a partially enclosed channel region. Because of the partially surrounding gate structure disclosed herein, a channel contact can be created and depletion is improved.

Still referring to FIGS. 25 and 26, interconnects 118 and 120 are output nodes for the SRAM cells (ie, similar or coupled to output nodes 101 and 103 in FIG. 22). It is known in the art that a biased capacitance located adjacent to the output node of an SRAM improves the immunity of known and understood soft errors. Accordingly, the diffusion (not shown) is performed in FIG. 25 and FIG.
And below 120. This diffusion (not shown)
Can be connected to the diffusion 14 and thus in a preferred manner to ground or to other traditional potentials. This diffusion (not shown) adds capacitive coupling to interconnects 118 and 120 and improves soft error immunity.

Although the invention has been shown and described with reference to specific embodiments, further modifications and improvements will occur to those skilled in the art. For example, the SRAM memory taught herein may be inverted so that the Vdd power supply voltage is a diffusion region and Vdd
The ss power supply voltage can be formed of metal. P channel and N
Channel transistors are stacked on top of each other
M embodiments can be formed. The polycrystalline vertical TFT can be used as a resistance device. Other vertical transistors exist in the prior art and any vertical transistor can be used to form an SRAM cell similar to the SRAM cells disclosed herein. Various techniques exist for sidewall dielectric formation and various spacer techniques can be used in conjunction with the present invention. Various silicidation methods exist. Many features of the device of the present invention can optionally be self-aligned or non-self-aligned.

In addition, a number of device structures are possible, such as no LDD, half LDD, full LDD, double LDD, and in-situ graded LDD electrode structures. A nitrided gate oxide can be used to reduce RIE (reactive ion etching) damage to the sidewall gate dielectric. A wide variety of process integration mechanisms are possible with a wide range of layouts and process flows. Other vertical layouts also exist. The methods and apparatus disclosed herein can be used to form memory cells for other conventional SRAMs. In some cases, the resistance device proposed here does not need to be large. The vertical transistor in the SRAM cell of the present invention has a current electrode separated from the substrate.
This isolation allows the electrodes to function as capacitors. Thus, the cells of the present invention can operate as a cross between dynamic random access memory (DRAM) and SRAM cells. In addition, other SRAM circuits can be created using the methods and apparatus disclosed herein. For example,
An N-channel transistor can be formed below the P-channel TFT, or an N-channel transistor can be formed below the resistor. Accordingly, it is not intended that the invention be limited to the specific forms shown and that the appended claims will cover all modifications that do not depart from the spirit and scope of the invention. It should be understood.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a transistor used in a semiconductor memory device and a method for forming the same according to the present invention.

FIG. 2 is a cross-sectional view showing a semiconductor memory device according to the present invention and a transistor used in a method for forming the same.

FIG. 3 is a cross-sectional view showing a transistor used in a semiconductor memory device and a method for forming the same according to the present invention.

FIG. 4 is a cross-sectional view showing a transistor used in a semiconductor memory device and a method of forming the same according to the present invention.

FIG. 5 is a top perspective view showing a vertical transistor having a plurality of gates for use in a semiconductor memory device according to the present invention.

FIG. 6 is a cross-sectional view illustrating another method of forming a sidewall dielectric for a transistor used in a semiconductor memory device according to the present invention.

FIG. 7 is a cross-sectional view showing a pair of vertically stacked transistors according to the present invention and a method for forming the same.

FIG. 8 is a cross-sectional view showing a pair of vertically stacked vertical transistors according to the present invention and a method for forming the same.

FIG. 9 is a cross-sectional view illustrating a pair of vertically stacked transistors and a method for forming the same according to the present invention.

FIG. 10 is a cross-sectional view illustrating a pair of vertically stacked transistors according to the present invention and a method for forming the same.

FIG. 11 is a cross-sectional view showing a pair of vertically stacked transistors according to the present invention and a method for forming the same.

FIG. 12 is a cross-sectional view showing a pair of vertically stacked transistors according to the present invention and a method for forming the same.

FIG. 13 is a cross-sectional view showing a pair of vertically stacked transistors according to the present invention and a method for forming the same.

FIG. 14 is a cross-sectional view showing a pair of vertically stacked transistors according to the present invention and a method for forming the same.

FIG. 15 is a cross-sectional view illustrating another pair of vertically stacked transistors according to the present invention and a method for forming the same.

FIG. 16 is a cross-sectional view showing another pair of vertical transistors stacked in the vertical direction and a method of forming the same according to the present invention.

FIG. 17 is a cross-sectional view showing another pair of vertically stacked transistors according to the present invention and a method for forming the same.

FIG. 18 is a cross-sectional view showing another pair of vertically stacked transistors according to the present invention and a method for forming the same.

FIG. 19 is a cross-sectional view illustrating another pair of vertically stacked transistors according to the present invention and a method for forming the same.

FIG. 20 is a cross-sectional view showing another pair of vertically stacked vertical transistors according to the present invention and a method for forming the same.

FIG. 21 is a top perspective view of one embodiment of the pair of vertically stacked vertical transistors of FIG. 20;

FIG. 22 is a circuit diagram showing a conventional static random access memory (SRAM).

FIG. 23 is a head perspective view of a static random access memory (SRAM) according to the present invention.

FIG. 24 is a cross-sectional view of the static random access memory of FIG. 23, taken along line 24-24.

FIG. 25 is a cross-sectional view of the static random access memory of FIG. 23, taken along line 25-25.

FIG. 26 is a cross-sectional view of the static random access memory of FIG. 23, taken along line 26-26.

FIG. 27 is a perspective view of the head showing a method of making another static random access memory (SRAM) according to the present invention.

FIG. 28 is a perspective view of a head showing a method of making another static random access memory (SRAM) according to the present invention.

FIG. 29 is a perspective view of a head showing a method of making another static random access memory (SRAM) according to the present invention.

FIG. 30 is a perspective view of a head showing a method of making another static random access memory (SRAM) according to the present invention.

FIG. 31 is a perspective view of the head showing a method of making another static random access memory (SRAM) according to the present invention.

FIG. 32 is a perspective view of the head showing a method of making another static random access memory (SRAM) according to the present invention.

FIG. 33 is a perspective view of the head showing a method of making another static random access memory (SRAM) according to the present invention.

[Explanation of symbols]

 12 Substrate 14 Diffusion 28 First current electrode 30 Channel region 32 Second current electrode 40 Gate electrode 50 First current electrode 52 Channel region 54 Second current electrode 100, 102, 104, 106 Transistors 118, 120 Electrical Interconnect 122 First vertical transistor stack 124 Second vertical transistor stack 126,128 Vertical stack 134,138 Resistor device

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor John T. Fitch 11160 # 623, Jollyville Road, Austin, 78759, Texas, USA James Di Heiden, 78737, Austin, Texas, USA Rio Bravo Lane 6802 (72) Inventor Keith E. Whitec 3204 # 214, Manchaka Road, Austin 78704, Texas, United States of America Reference: JP-A-64-89560 (JP, A) -265558 (JP, A) US Patent 4,554,570 (US, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8244 H01L 27/11 JICST file (JOIS)

Claims (2)

(57) [Claims] 1. A semiconductor memory device, comprising:First A transistor (100), wherein the first transistor
Transistor is a first current electrode (28), said first current electrode
on top ofTo positionA second current electrode (32);
Between the second current electrodeIn the first channel region (30)
Wherein the first channel region has a first channel width
And the firstFew adjacent to the channel region
At least one gate electrode (120),Having,Second A transistor (104), wherein the second transistor
Transistor is a first current electrode (50), said first current electrode
on top ofTo positionA second current electrode (54), the first and
Between the second current electrodesIn the second channel region (52)
The second channel region has a second channel width
One, and at least adjacent to the second channel region
And one gate electrode (40).
A channel region is defined by the second channel width and the first channel.
The first channel so that the width of the first channel is substantially the same
Located above the area, With Here, a second current electrode of the first transistor and a
The first current electrode of the second transistor is the semiconductor
Electrically coupled to the first node of the memory device and
The second node of the semiconductor memory device is connected to the first transistor.
At least one of the gate electrodes of the transistor or
The at least one gate voltage of the second transistor;
Electrically connected to one of the poles, Semiconductor memory device. 2. Further,Third A transistor (102), the third transistor
The transistor is a first current electrode, on the first current electrodeRank
PutA second current electrode, said first and second current electrodes
BetweenA third channel region, the third channel region
The zone having a third channel width;
At least one gate electrode adjacent to the channel region
(118),Having,Fourth A transistor (106), wherein the fourth transistor
The transistor is a first current electrode, on the first current electrodeRank
PutA second current electrode, said first and second current electrodes
BetweenA fourth channel region, wherein the fourth channel region is
The zone having a fourth channel width;
At least one gate electrode adjacent to the channel region
(40), wherein the fourth channel region is the fourth channel region.
And the first channel width are approximately the same size
Which is located above the third channel region so that
of, With Here, a second current electrode of the third transistor and a
The first current electrode of the fourth transistor corresponds to the semiconductor
Electrically coupled to the second node of the memory device;
The first node of the semiconductor memory device is connected to the third node
The at least one gate electrode of the transistor
Or said at least one of said fourth transistors
Electrically connected to one of the gate electrodes, The semiconductor memory device according to claim 1.