JP3316723B2 - Compensation method for receiving apparatus, receiving apparatus, and transmitting / receiving apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus and a transmitting / receiving apparatus for demodulating data from mutually orthogonal I and Q signals used in a radio communication system, and a method of compensating the receiving apparatus.

[0002]

2. Description of the Related Art FIG. 41 shows Philips published in 1986.
From page 219 of Journal of Reserch vol.41, No.3, 2
Page 31 (Reference 1), from page 462 of IEICE Transactions C-1, vol. J76-C-1, No. 11, published in 1993
469 pages (Reference 2) or held in 1991
This is a configuration example of a homodyne configuration receiving apparatus described in Proceeding pages 457 to 462 (Reference 3) of Vehicle technol. Conf. Sponsored by IEEE.

In FIG. 1, reference numeral 1 denotes a low noise amplifier (LNA) which receives a received wave of frequency frf from an antenna (not shown) and amplifies the received wave, and 2 denotes a band for extracting a signal of a predetermined band from the output of the low noise amplifier 1. Pass filter (BPF),
Reference numeral 6 denotes a quadrature mixer that mixes an output signal of the band-pass filter 2 and a local oscillation signal having a frequency fp and outputs baseband I and Q signals. The I signal and the Q signal are orthogonal to each other.

A quadrature mixer 6 is a 0-degree divider 4 for dividing the output of the band-pass filter 2 into two, a 90-degree phase shifter 5 for delaying the phase of a local oscillation signal supplied from the outside by 90 degrees, and a 0-degree phase shifter. Mixer (MIX) 3 for mixing the output signal of distributor 4 and the output signal of 90-degree phase shifter 5 to output an I signal
a, a mixer (MI) that mixes the output signal of the 0-degree distributor 4 with a local oscillation signal supplied from the outside and outputs a Q signal
X) 3b.

[0005] The reference numeral 8 designates a local mixer for generating a local oscillation signal.
Is supplied to the local oscillator (LO). The oscillation frequency of the local oscillator 8 changes based on channel setting data supplied from a control circuit (not shown). Reference numerals 9a and 9b denote low-pass filters (LPF) for extracting low-frequency signals from the I signal and the Q signal, respectively, and reference numerals 10a and 10b denote baseband amplifiers (AMP) for amplifying the outputs of the low-pass filters 9a and 9b, respectively. 11b is an A / D converter for converting the output of the baseband amplifiers 10a and 10b from analog to digital, 12 is an A / D converter 11a,
11b is a demodulation operation circuit that performs demodulation processing based on the data of the I signal and the data of the Q signal output by 11b.

Next, the operation will be described. The conventional homodyne receiving apparatus shown in FIG.
, A complex envelope detection of the received wave frf into an I signal and a Q signal. The orthogonal mixer 6 is composed of two local oscillation waves distributed by the mixers 3a and 3b with a phase difference of 90 degrees therebetween.
The fp and the received wave frf distributed in the same phase are respectively subjected to analog multiplication and frequency mixing.

Here, the local oscillation frequency fp and the reception wave frequency
If frf is substantially the same, low-pass filters 9a, 9
b, the I output and the Q output of the quadrature mixer 6 are respectively filtered, and the frequency component of the difference between fp and frf near the baseband frequency is extracted, whereby the modulated signal component of the received wave (RF) is obtained. These I and Q outputs are amplified by the baseband amplifiers 10a and 10b to increase the level, and then quantized by the A / D converters 11a and 11b, respectively. The demodulation operation circuit 12 reproduces data modulated into a received wave based on the data of the I signal and the data of the Q signal.

[0008] As described above, the receiver having the homodyne configuration has
It comprises an I receiving circuit and a Q receiving circuit.

A receiving device having such a homodyne configuration has
There are the following features as compared with the heterodyne configuration receiving apparatus. (1) Since the intermediate frequency circuit is unnecessary, the size is small and the cost is low. (2) Since the image frequency of the mixer does not exist, the band-pass filter 2 becomes small.

For these reasons, the homodyne receiving apparatus is used for AM radio, FM radio, pager (mainly FSK modulation), and the like. Reference 1 cited above shows a case applied to AM radio and FM radio, Reference 2 shows a case applied to pager, and Reference 3 shows a case applied to digital mobile communication. I have.

[0011]

The conventional homodyne receiver has a simple structure, but has various problems, and its application is very limited.
Hereinafter, the problem will be described with reference to FIGS. 42 and 43. In FIG. 43, a solid line indicates ideal characteristics, and a dotted line indicates deteriorated characteristics.

(A) In the mixers 3a and 3b or the baseband amplifiers 10a and 10b, the DC offset Δi,
Δq occurs (FIG. 42). These DC offset Δ
The center of the IQ spatial diagram is shifted by i and Δq (FIG. 43 (a) shows a case where the center is offset in the direction of the fourth quadrant). (b) Mixer 3a, 3b or baseband amplifier 10
Gain imbalance occurs in a and 10b, and the gain Gi of the I channel and the gain Gq of the Q channel are not completely balanced (FIG. 42). This imbalance causes the IQ spatial diagram to shrink and expand in the direction of the I axis or the Q axis (FIG. 43).
(B) shows a spatial diagram when the gain of the Q channel is low). (c) A phase error Δφ occurs in the 0-degree distributor 4 or the 90-degree phase shifter 5 (FIG. 42). The spatial diagram becomes an ellipse due to this phase error Δφ (FIG. 43 (c) shows that the axis passing through the second and fourth quadrants is the major axis of the ellipse, and the axis passing through the first and third quadrants is the short axis of the ellipse. Axis.)

Due to the vector errors of (a) to (c),
The spatial diagram of the output of the homodyne receiver is transformed from a perfect circle, which is an ideal characteristic, to an ellipse whose center is offset (FIG. 43 (d) is a combination of the transformations of FIGS. 43 (a) to (c)). Is shown).

In this case, the orthogonal mixers 3a, 3b
The input wave represented by the following equation, where the carrier angular frequency is ωc, the coordinates of the I axis and the coordinates of the Q axis are d1 (t) and d2 (t), respectively.
Suppose Vin (t) is added. Vin (t) = d1 (t) · cos (ωct) −d2 (t) · sin (ωct) (1)

At this time, Δi and Δq are respectively set on the I axis and Q
DC offset error with respect to axis, ΔG is gain error, Δφ
Is a phase error, the voltage Vi (t) of the I output and the Q output filtered by the low-pass filters 9a and 9b, the voltage Vq
(t) is given by the following equation. However, a frequency difference and a phase difference between the carrier and the local oscillation wave are not taken into consideration. Vi (t) = d1 (t) + Δi Vq (t) = ΔG · ｛−d1 (t) · sin (Δφ) + d2 (t) · cos (Δφ)｝ + Δq (2)

Due to these errors, the amplitude after demodulation may become small depending on the coordinates of the transmission code. Then, transmission quality deteriorates. For example, in the case of digital transmission,
It deteriorates as shown in FIG. In the figure, the vertical axis indicates a bit error rate (hereinafter, BER), and the horizontal axis indicates (signal power per bit / noise power per Hz). The solid line represents the BE of a perfect quadrature mixer without error.
The dotted line indicates the BER characteristic of the imperfect quadrature mixer having an error.

According to FIG. ₁ , the power ratio at which the BER becomes y is x _{1 for} a perfect orthogonal mixer and x ₂ for an incomplete orthogonal mixer (x ₁ <x ₂ ). That is, for the same power ratio, the BER of the imperfect quadrature mixer is greater than the BER of the perfect quadrature mixer. Therefore, when the quadrature mixer is incomplete, if the power level is relatively small, errors frequently occur, which is a practical problem. This means that, for example, in land mobile communication, the service area of the receiving device is reduced.

Incidentally, such a problem is shown in FIG.
It also exists in principle in a heterodyne receiver using the quadrature mixer 6 of the intermediate frequency. In the figure,
Reference numeral 58 denotes a downconverter for converting a received wave into an intermediate frequency signal. The down-converter 58 includes a mixer 13 for mixing the received signal and the local oscillation signal, a local oscillator 16 for generating a local oscillation signal for converting to an intermediate frequency signal, an amplifier (AMP) 14 for amplifying an output of the mixer 13, an amplifier It comprises a bandpass filter (BPF) 15 for extracting a signal of a predetermined band from the output signal of 14. The intermediate frequency signal output from the down converter 58 is input to the quadrature mixer 6.

However, the above problems are more serious in the homodyne configuration than in the heterodyne configuration for the following reasons. (d) In a homodyne configuration, the quadrature mixer operates at high frequencies. The 0-degree distributor 4 and the 90-degree phase shifter 5 operating at a high frequency are difficult to obtain predetermined accuracy in terms of distribution amplitude and phase. Therefore, a gain error and a phase error increase. In addition, DC offset is the WJ Tech-note vol.5, published in 1978, NO1
As described in “Mixers as phase detector” (Reference 4), due to the unbalance of each semiconductor element of the balanced mixer constituting the mixer 3, the unbalance becomes larger at a high frequency, so that the DC offset Becomes larger.

(E) In the heterodyne configuration shown in FIG.
The RF stage has a low gain from the viewpoint of suppressing distortion in the mixer. Therefore, the amplifier 14 is set to a high gain, and the level setting is performed so that the modulation signal output from the quadrature mixer 6 has a sufficiently high level as compared with the DC offset.
On the other hand, in the homodyne configuration, the RF stage similarly has a low gain, but there is no equivalent to the amplifier 14 in the intermediate frequency band, and the level of the modulation signal output from the quadrature mixer 6 is lower than that in the heterodyne configuration. Low. Therefore, the amplitude of the DC offset becomes relatively large.

As described above, in the homodyne configuration, D
The problem of C offset is particularly acute. So, conventionally,
In Document 2 and the like, as shown in FIG. 46, the DC offset of the quadrature mixer 6 is suppressed by providing high-pass filters (HPF) 60a, 60a at the IQ outputs (outputs of the LPFs 9a, 9b) of the quadrature mixer 6, respectively. are doing. Alternatively, as shown in FIG. 47, the DC offset of the baseband amplifiers 10a and 10b is also suppressed by providing high-pass filters 60c and 60d at the outputs of the baseband amplifiers 10a and 10b, respectively.

However, when these high-pass filters 60 are used, there arises a problem that the transmission code is distorted due to a transient response. FIG. 48B shows a transient response characteristic of the high-pass filter 60 when the impulse signal of FIG. 48A is input. As shown in FIG. 48B, since the low-frequency component of the impulse that does not pass through the high-pass filter 60 leaks, interference with the adjacent code of the transmission code occurs depending on the time constant.

FIG. 49 (b) shows the response characteristics when the code signal having the DC offset shown in FIG. 49 (a) is passed through the high-pass filter 60. As can be seen from FIG. 49B, the DC offset can be suppressed, but the DC component of the code is also suppressed, so that the transmission code is distorted. In order to avoid this problem, it is necessary to set the cutoff frequency of the high-pass filter 60 to a frequency sufficiently lower than the transmission speed of the transmission code.

However, depending on the transmission method, an unmodulated carrier (CW) may be transmitted and received at the beginning of a code for a long time for the purpose of carrier reproduction (FIG. 50).
(A)). For example, there is a case where consecutive identical codes are transmitted in QPSK. At this time, since the input of the high-pass filter 60 has a constant voltage for a long time, the signal is significantly attenuated in the high-pass filter 60 and the CW portion is cut off as shown by the dotted line in FIG. There is.

On the other hand, if the cutoff frequency of the high-pass filter 60 is set low, another problem occurs. The DC offset generated in the output of the quadrature mixer 6 varies depending on the level and frequency of the local oscillator 8 (FIG. 51A). for that reason,
When the local oscillation frequency fp changes, the DC offset amount superimposed on the code changes, so that the output code of the high-pass filter 60 is disturbed as shown in FIG.
ER deteriorates. As described above, the high-pass filter 60
If the cutoff frequency of the DC offset is set low, there is a problem that the fluctuation of the DC offset cannot be removed for a long time.

As a solution to the above problem, for example, IEICE Transactions B-II, vol, J75-BI
I, No. 1, pp1-9 (1992.1) (Reference 5)
And US Pat. No. 5,294,203 (Reference 6), the error of the orthogonal coordinate IQ of the received signal is detected by the error detecting means 103 during the receiving operation, and then the coordinate of the IQ received signal is corrected by the error compensating means 104. (See Fig. 5)
2).

However, this method has the following problems. (1) Since this is an online process in which the error detection process and the compensation process are performed at the same time as the reception process, the amount of demodulation calculation and the power consumption increase. (2) In order to expand the service area, error compensation is most needed especially in a line condition where the CN is low, but under this condition the received signal used to detect the error contains a lot of noise. As a result, the accuracy of error detection is generally low. Therefore, the desired effect cannot be obtained.

The problem has been described with respect to the homodyne receiving apparatus shown in FIG. 41 and the heterodyne receiving apparatus shown in FIG. 45. However, the homodyne transmitting apparatus shown in FIG. 53 and the transmitting apparatus shown in FIG. The same problem occurs to some extent in the heterodyne transmission device as long as the quadrature mixer is used (although the DC offset corresponds to the leakage of the carrier component in the transmission quadrature mixer 38, the BER is degraded). In that respect).

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. A receiving apparatus, a transmitting / receiving apparatus, and a receiving apparatus capable of reducing the influence of an error relating to the rectangular coordinate IQ of a received signal and reducing the BER. It is an object to provide a method of compensating the device.

[0030]

According to a first aspect of the present invention, there is provided a method for compensating a receiving apparatus, comprising the steps of: detecting a received signal and outputting an I signal and a Q signal orthogonal to each other; enter the test signal as a signal, received with the determined gain error which is an error between the I and Q signals of the test signal, a calibration step of storing the error data of the upper Symbol gain error in the memory, a communication signal the received signal
Is converted from analog to digital, error data is read out from the memory, and an I signal or a Q signal of the communication signal is compensated based on the error data. The method for compensating a receiving device according to claim 2, wherein the receiving device includes a detector that detects a received signal and outputs an I signal and a Q signal that are orthogonal to each other.
Enter the test signal as the received signal, together determine the phase error which is an error between the I and Q signals of the test signal, a calibration step of storing the error data of the upper Symbol phase error memory, a communication signal And reading the error data from the memory when the communication signal is received, and compensating the I signal or the Q signal of the communication signal based on the error data.

According to a third aspect of the present invention, there is provided a method for compensating for a receiving apparatus, wherein the calibration step includes the steps of: inputting a test signal as the received signal;
With obtaining an error between the, and the first calibration step of storing the error data of the error in the memory, reads the error data from the memory, the I signal or Q signal of the test signal based on the error data and second calibration step of compensating, on the basis of this I and Q signals
Together determine the serial error, which is constituted from a third calibration step of updating the error data by storing error data for the error in the memory. Claim
The method of compensating the receiving device according to claim 4, wherein the calibration step includes:
Further, errors occurring in the I signal and the Q signal of the test signal and
The DC offset error is calculated as
It stores the error data of the offset error in the memory.
is there. Compensation method of a receiving apparatus according to claim 5, the calibration
Step inputs the test signal as said received signal, where
It occurs in the I and Q signals of the above test signal based on the constant value.
Error between the I signal and the Q signal.
And save the error data in memory.
1 calibration step and reading error data from memory
Out of the test signal based on the error data.
A second compensating at least one of the I signal and the Q signal.
Compensation by the calibration step and the second calibration step.
Error occurring in the I and Q signals obtained above, or I
The error between the signal and the Q signal is determined, and
By storing the difference data in the memory, the error
And a third calibration step for updating the data.
It is.

In a sixth aspect of the present invention, the test signal input in the calibration step is a pilot signal included in an external communication signal.

According to a seventh aspect of the present invention, in the method for compensating for a receiving apparatus, the test signal input in the calibration step may be transmitted from an external device.
This is an unmodulated signal transmitted prior to data.

[0034] In the compensation method of the receiving apparatus according to claim 8 , in the calibration step, the test signal is a sine wave,
The DC offset error Δi of the I signal and the DC offset error Δq of the Q signal are obtained by extracting the low frequency components of the signal and the Q signal, and the I signal and the Q signal of the communication signal are obtained in the compensation step. And the DC offset error Δi of the Q signal are subtracted from each other to compensate for the offset.

According to a ninth aspect of the present invention, a test signal is input as a reception signal to a reception apparatus having a detector that detects a reception signal and outputs an I signal and a Q signal orthogonal to each other. Determining a difference between the I signal and the Q signal of the test signal, storing the error data in a memory, reading error data from the memory when a communication signal is received, A compensating step of compensating the I signal and the Q signal of the communication signal based on the above. In the calibration step, the test signal is a sine wave, and one of the I signal and the Q signal for the sine wave input is provided. When the amplitude is V1 (t) and the other amplitude is V2 (t), the low frequency component is extracted after squaring the I signal and the Q signal, respectively. Squared value of the amplitude (V1 (t))
2, (V2 (t)) 2, and further, a gain error ΔG is calculated by the following equation (a), and ΔG = Ｖ (V2 (t)) 2 / (V1 (t)) 2 (0.5 (a) In the compensation step, the gain is obtained by multiplying the signal corresponding to the amplitude V1 (t) by the gain error ΔG, or by dividing the signal corresponding to the amplitude V2 (t) by the gain error ΔG. To compensate.

The compensation method of the receiving apparatus according to claim 10 is
A test signal is input as a received signal to a receiving apparatus provided with a detector that detects a received signal and outputs an I signal and a Q signal orthogonal to each other, and outputs the I signal and Q of the test signal.
A calibration step of obtaining errors in the signal and storing the data of these errors in a memory; reading out the error data from the memory when a communication signal is received; and an I signal and a Q of the communication signal based on the error data. And a compensating step for compensating the signal. In the calibrating step, the test signal is a sine wave, the amplitude of one of the I signal and the Q signal with respect to the sine wave input is V1 (t), and the other is the amplitude. Is V2 (t), the low-frequency component is extracted after squaring the I signal and the Q signal, thereby obtaining the square value of the amplitude (V1 (t)).
² , (V2 (t)) ² , and further, a gain error ΔG is calculated by the following equation (a), and ΔG = ｛(V2 (t)) ² / (V1 (t)) ² ｝ ^0.5 (a) After multiplying the I signal and the Q signal, a low frequency component is extracted, and the extracted value is expressed as (V3 (t)) 2
Then, the phase error Δφ is obtained by the following equation (b), and Δφ = sin-1 ｛(V3 (t)) 2 / (ΔG ・ (V1 (t)) 2)｝ (b) In the above compensation step, The phase is compensated by the following equation (c). {V2 (t) + V1 (t) * sin (Δφ)} / cos (Δφ) (c)

The receiving apparatus according to claim 11, a detector which detects the communication signal received and outputs the I and Q signals are orthogonal to each other, the output I signal by the detector
And Q signals are converted from analog to digital, respectively.
An A / D converter, and a memory in which error data of a gain error between the I signal and the Q signal generated in the detector determined based on a test signal is stored in advance;
Compensating means for reading the error data from the memory, compensating the I signal or the Q signal output from the A / D converter based on the error data, and a compensated I signal output by the compensating means; And a demodulation circuit for demodulating data based on the Q signal. Claim
12 is a detector that detects a received communication signal and outputs an I signal and a Q signal that are orthogonal to each other, and an error of a phase error between the I signal and the Q signal generated in the detector. A memory in which data is stored in advance, a readout of the error data from the memory, a compensation means for compensating the I signal or the Q signal based on the error data, and a compensated I signal output by the compensation means; And a demodulation circuit for demodulating data based on the Q signal.

According to a thirteenth aspect of the present invention, the receiving device includes a temperature sensor for measuring a temperature inside the device, a plurality of error data corresponding to a plurality of temperatures are stored in the memory, and the compensating means includes the I signal reads the error data corresponding to the temperature at which the temperature sensor outputs or
The other is intended to compensate for the Q signal.

A receiver according to a fourteenth aspect includes a local oscillation frequency detector for detecting a frequency of a local oscillation wave of the detector, and a plurality of error data corresponding to a plurality of frequencies are stored in the memory. The compensating means reads error data corresponding to the frequency output from the local oscillation frequency detector and reads the I signal or the Q signal.
It compensates the signal.

According to a fifteenth aspect of the present invention, the DC offset error Δi of the I signal and the DC offset error Δq of the Q signal are stored in the memory, and the DC offset error from the I signal is stored in the compensating means. It is provided with an i-channel subtractor for subtracting Δi and a q-channel subtractor for subtracting the DC offset error Δq from the Q signal. The receiving device according to claim 16 is provided inside the device.
It has a temperature sensor to measure the temperature and
Error data corresponding to each of multiple temperatures
Is stored, and the compensation means outputs the signal from the temperature sensor.
The error data corresponding to the temperature
And at least one of the above Q signals.
You. The receiving device according to claim 17 is characterized in that:
Equipped with a local oscillation frequency detector that detects the frequency of the vibration
In addition, the above memory supports multiple frequencies
Are stored, and the compensation means is
Error corresponding to the frequency output from the local oscillation frequency detector
The difference data is read and the I signal and the Q signal are skipped.
At least one is compensated.

[0041] The receiving apparatus according to claim 18, a detector which detects the communication signal received and outputs the I and Q signals are orthogonal to each other, the output I signal by the detector
And Q signals are converted from analog to digital, respectively.
An A / D converter, a memory in which error data generated in the detector obtained based on a test signal is stored in advance, and error data is read out from the memory, and the I signal and the Q signal are read based on the error data. And a compensating means for compensating the I and Q signals output from the A / D converter based on the compensated I signal and Q signal output by the compensating means.
And a demodulation circuit for demodulating the data.
A gain error ΔG between the I signal and the Q signal is stored, and the compensating means includes a multiplier for multiplying the I signal or the Q signal by a coefficient corresponding to the gain error ΔG. is there.

According to a nineteenth aspect of the present invention, there is provided a receiver for detecting a received communication signal and outputting I and Q signals orthogonal to each other, a memory in which error data generated in the detector is stored in advance, Compensating means for reading error data from the memory and compensating the I signal and the Q signal based on the error data; and a demodulation circuit for demodulating data based on the compensated I and Q signals output by the compensating means. Wherein the phase error Δφ between the I signal and the Q signal is stored in the memory, and the compensating means stores one of the amplitudes of the I signal and the Q signal as V 1 (t), Assuming that the other amplitude is V2 (t), based on the above phase error Δφ, the equation ΔV2 (t)
+ V1 (t) * sin (Δφ)｝ / cos (Δφ).

According to a twentieth aspect of the present invention, when a test wave is input to the detector instead of the communication signal,
An error detection circuit for obtaining the error data based on the I signal and the Q signal from the detector and storing the error data in the memory.

A receiving apparatus according to a twenty-first aspect of the present invention includes a test signal generator that generates a sine wave and supplies it to the detector when the error detection circuit obtains error data.

A receiver according to claim 22 , wherein the error detection circuit extracts a low frequency component of the I signal to output a DC offset error Δi, and outputs a DC offset error Δi; And a q-channel low-pass filter that extracts a component and outputs a DC offset error Δq.

According to a twenty- third aspect of the present invention, there is provided a receiver for detecting a received communication signal and outputting an I signal and a Q signal orthogonal to each other, a memory in which error data generated in the detector is stored in advance, Compensating means for reading error data from the memory and compensating the I signal and the Q signal based on the error data; and a demodulation circuit for demodulating data based on the compensated I and Q signals output by the compensating means. And when a test wave is input to the detector as the communication signal, the I from the detector is
An error detection circuit for obtaining the error data based on the signal and the Q signal and storing the error data in the memory, wherein the error detection circuit has an i-channel square arithmetic circuit for squaring the I signal, and q for squaring the Q signal. A channel square arithmetic circuit,
An i-channel low-pass filter for extracting a low-frequency component of an output signal of the i-channel square arithmetic circuit; a q-channel low-pass filter for extracting a low-frequency component of an output signal of the q-channel square arithmetic circuit; A gain error calculation circuit for calculating a gain error ΔG based on the output of the channel low-pass filter and the output of the q-channel low-pass filter.

According to a twenty-fourth aspect of the present invention, there is provided a receiver for detecting a received communication signal and outputting an I signal and a Q signal orthogonal to each other, a memory in which error data generated in the detector is stored in advance, Compensating means for reading error data from the memory and compensating the I signal and the Q signal based on the error data; and a demodulation circuit for demodulating data based on the compensated I and Q signals output by the compensating means. And when a test wave is input to the detector as the communication signal, the I from the detector is
An error detection circuit for obtaining the error data based on the signal and the Q signal and storing the error data in the memory, wherein the error detection circuit has an i-channel square arithmetic circuit for squaring the I signal, and q for squaring the Q signal. A channel square arithmetic circuit,
An i-channel low-pass filter for extracting a low-frequency component of an output signal of the i-channel square arithmetic circuit; a q-channel low-pass filter for extracting a low-frequency component of an output signal of the q-channel square arithmetic circuit; A gain error calculation circuit that calculates a gain error ΔG based on an output of the channel low-pass filter and an output of the q-channel low-pass filter, a multiplication circuit that multiplies the I signal and the Q signal,
A low-pass filter that extracts a low-frequency component of the output signal of the multiplication circuit; and a phase error calculation circuit that calculates a phase error Δφ based on the output of the low-pass filter and the output of the gain error calculation circuit. It is a thing.

The receiving apparatus according to claim 25 is provided with low-pass filter control means for changing the frequency characteristic of the low-pass filter in response to a change in the communication rate.

According to a twenty-sixth aspect of the present invention, there is provided a receiver for detecting a received communication signal to output an I signal and a Q signal orthogonal to each other, and extracting a high frequency component of the I signal.
A channel high-pass filter, a q-channel high-pass filter for extracting high-frequency components of the Q signal, and demodulation of data based on an output signal of the i-channel high-pass filter and an output signal of the q-channel high-pass filter. A demodulation circuit that performs the above-described operation, and the D signal included in the I signal or the Q signal.
High-pass filter control means for controlling the i-channel high-pass filter and the q-channel high-pass filter so as to increase the cutoff frequency when the C offset varies.

According to a twenty-seventh aspect of the present invention, the i-channel high-pass filter and the q-channel high-pass filter are each constituted by a switched capacitor filter whose cut-off frequency changes in accordance with the frequency of a supplied clock. A reference signal generator for generating a reference signal in the high-pass filter control means, a clock generated by dividing the reference signal, the i-channel high-pass filter and the q-channel high-pass filter, And a frequency division number control unit for lowering the frequency division number of the counter when the DC offset fluctuates.

According to a twenty-eighth aspect of the present invention, there is provided a receiving apparatus comprising: a local oscillator for generating a local oscillation wave; and a detector for detecting a communication signal received based on the local oscillation wave and outputting an I signal and a Q signal orthogonal to each other. An i-channel high-pass filter for extracting the high-frequency component of the I signal, a q-channel high-pass filter for extracting the high-frequency component of the Q signal, an output signal of the i-channel high-pass filter, and the q-channel height. A demodulation circuit that demodulates data based on an output signal of the band-pass filter; and, when an unmodulated signal is received, a difference between the frequency of the local oscillation wave and the frequency of the unmodulated signal is determined by the Cutoff frequency and q
A control circuit for controlling the local oscillator so as to be higher than any of the cutoff frequencies of the channel high-pass filter.

A receiver according to claim 29 , comprising a local oscillator for generating a local oscillation wave, and a detector for detecting a communication signal received based on the local oscillation wave and outputting an I signal and a Q signal orthogonal to each other. , An i-channel high-pass filter for extracting the high-frequency component of the I signal, a q-channel high-pass filter for extracting the high-frequency component of the Q signal, and an output of the i-channel high-pass filter. An i-channel correction filter having an inverse characteristic to the pass characteristic of the above, and an input of the output of the q-channel high-pass filter, and a q-channel correction filter having an inverse characteristic to the pass characteristic of the filter; A demodulation circuit for demodulating data based on the output signal of the filter and the output signal of the q-channel correction filter.

A receiver according to claim 30 is a local oscillator for generating a local oscillation wave, and a detector for detecting a communication signal received based on the local oscillation wave and outputting an I signal and a Q signal orthogonal to each other. An i-channel delay means for delaying the I signal, an i-channel low-pass filter for extracting a low-frequency component of the I signal, and an output of the i-channel delay means and an output of the i-channel low-pass filter. An i-channel subtractor for obtaining a difference, a q-channel delay unit for delaying the Q signal, a q-channel low-pass filter for extracting a low-frequency component of the Q signal, an output of the q-channel delay unit and the q-channel A q-channel subtractor for obtaining a difference from an output of the low-pass filter; and demodulating data based on an output signal of the i-channel subtractor and an output signal of the q-channel subtractor. It is obtained by a demodulation circuit.

According to a thirty-first aspect of the present invention, there is provided a transmitting / receiving apparatus comprising: a transmitting and receiving antenna; a detector for detecting a signal received from the antenna to output an I signal and a Q signal orthogonal to each other; A reception error memory storing error data in advance, reading out the reception error data from the reception error memory, and compensating means for compensating the I signal and the Q signal based on the reception error data, and outputting the compensation means A receiver including a demodulation circuit for demodulating data based on the compensated I signal and Q signal, a transmission error memory for storing transmission error data,
A modulation signal generation circuit for modulating transmission data to output an I signal and a Q signal orthogonal to each other, reading the transmission error data from the transmission error memory, and outputting the I and Q signals output from the modulation signal generation circuit based on the transmission error data Signal and Q
An error compensation circuit for compensating a signal, a modulator for generating a transmission signal based on the compensated I signal and Q signal output from the error compensation circuit, and an amplifier for amplifying an output of the modulator and supplying the output to the antenna A transmission unit comprising: a transmission unit that obtains the transmission error data by comparing coordinates of data transmitted by the demodulation circuit of the reception unit with coordinates of the transmitted transmission data; and the transmission error memory of the transmission unit. And a transmission error calculating circuit for storing the transmission error data, the transmission unit generates the transmission signal from the input transmission data, and the transmission signal from the amplifier, The transmission error calculation circuit supplies data to a detector, wherein the reception unit compensates and demodulates the supplied transmission signal based on reception error data stored in advance. Output, the transmission error calculation circuit, and requests the transmission error data by comparing the coordinates of the coordinates and the transmission data of the data output from the demodulating circuit.

A transmitting / receiving apparatus according to claim 32 , further comprising a frequency converter for converting a frequency of a transmission signal supplied from the amplifier of the transmitting section to the detector of the receiving section to a frequency of the receiving section. Things.

A transmission / reception device according to claim 33 , further comprising a temperature sensor for measuring a temperature inside the device, a plurality of transmission error data corresponding to each of a plurality of temperatures being stored in the transmission error memory, The error compensation circuit reads out transmission error data corresponding to the temperature output from the temperature sensor and compensates the I signal and the Q signal.

A transmission / reception apparatus according to claim 34 , further comprising a local oscillation frequency detector for detecting a frequency of a local oscillation wave of the modulator of the transmission section, wherein the transmission error memory stores a plurality of local oscillation frequencies. A plurality of corresponding transmission error data are stored, and the error compensation circuit reads transmission error data corresponding to the frequency output from the local oscillation frequency detector and compensates the I signal and the Q signal.

[0058]

According to the first aspect of the present invention, the calibration step comprises:
A gain error, which is an error between the I signal and the Q signal, is obtained based on a test signal input instead of the received signal, and error data of the gain error is stored in a memory. Receive the signal and
The data is converted from analog to digital, error data is read from the memory, and the I signal or the Q signal of the communication signal is compensated based on the error data. Claim 2
In the invention of the above, the calibration step is performed between the I signal and the Q signal based on the test signal input instead of the received signal.
The phase error, which is the error of the phase error, is obtained , the error data of the phase error is stored in a memory, and the compensation step reads the error data from the memory when an actual communication signal is received, and performs the communication based on the error data. Compensate the I or Q signal of the signal.

[0059] In the invention of claim 3, in the calibration step, the first calibration step, with obtaining an error between the I and Q signals of the test signal based on a predetermined value, the error of the error store data in memory, the second calibration step, reads the error data from the memory, to compensate the I signal or Q signal of the test signal based on said error data, a third calibration step of, this I An error is obtained based on the signal and the Q signal, and the error data is updated by storing the data of the error in the memory. In the invention of claim 4,
The calibration step further includes an I signal and a Q signal of the test signal.
Find DC offset error as error occurring in signal
At the same time, note the error data of the DC offset error.
To save the file. In the invention of claim 5, the calibration step
The step, the first calibration step, as the received signal
A test signal is input, and based on a predetermined value, the I
Error in the signal and Q signal, or I signal and Q
Find the error between the signal and
In a memory, and the second calibration step
Read the error data from
Based on at least the I and Q signals of the test signal
Compensating for one, and the third calibration step is the second calibration
Occurs in the I and Q signals compensated by the step
Error between the I signal and the Q signal.
And save the error data in the above memory.
Thus, the error data is updated.

According to the sixth aspect of the present invention, a pilot signal included in an external communication signal is input as the test signal in the calibration step.

According to the seventh aspect of the present invention, an unmodulated signal transmitted before data is input from the outside as the test signal in the calibration step.

According to the eighth aspect of the present invention, in the calibrating step, the test signal is a sine wave, and the low frequency components of the I signal and the Q signal are extracted, whereby the D signal of the I signal is extracted.
The C offset error Δi and the DC offset error Δq of the Q signal are obtained, and in the compensation step, the DC offset error Δi of the I signal is obtained from the I signal and the Q signal of the communication signal.
And the DC offset error Δq of the Q signal is subtracted to compensate for the offset.

According to the ninth aspect of the present invention, a test signal is input as a reception signal to a reception apparatus having a detector that detects a reception signal and outputs an I signal and a Q signal orthogonal to each other. A calibration step of obtaining errors occurring in the I signal and the Q signal of the signal and storing the data of these errors in a memory; reading error data from the memory when a communication signal is received; A compensating step for compensating the I and Q signals of the signal. In the calibrating step, the test signal is a sine wave, and the I signal with respect to the sine wave input is
The amplitude of one of the signal and the Q signal is V1
(T), when the other amplitude is V2 (t), the low frequency component is extracted after squaring the I signal and the Q signal, thereby obtaining the square value of the amplitude (V1 (t)) ² ,
(V2 (t)) ² , and further, a gain error ΔG is calculated by the following equation (a), and ΔG = ｛(V2 (t)) ² / (V1
(T)) ² ｝ ^0.5 (a) In the compensation step, the signal corresponding to the amplitude V1 (t) is multiplied by the gain error ΔG, or the signal corresponding to the amplitude V2 (t) is The gain is compensated by dividing by the gain error ΔG.

According to a tenth aspect of the present invention, a test signal is input as a reception signal to a reception device having a detector for detecting a reception signal and outputting an I signal and a Q signal orthogonal to each other, and A calibration step of obtaining errors occurring in the I signal and the Q signal of the signal and storing the data of these errors in a memory; reading error data from the memory when a communication signal is received; A compensating step for compensating the I signal and the Q signal of the signal. In the calibrating step, the test signal is a sine wave, and the amplitude of one of the I signal and the Q signal with respect to the sine wave input is V1.
(T), when the other amplitude is V2 (t), the low frequency component is extracted after squaring the I signal and the Q signal, thereby obtaining the square value of the amplitude (V1 (t)) ² ,
(V2 (t)) ² , and further, a gain error ΔG is calculated by the following equation (a). ΔG = ｛(V2 (t)) ² / (V1 (t)) ² ｝ ^0.5 (a) After multiplying the I signal and the Q signal, a low frequency component is extracted, and the extracted value is expressed as (V3 (t)) ²
Then, the phase error Δφ is obtained by the following equation (b), and Δφ = sin ⁻¹ {(V3 (t)) ² / (ΔG · (V1 (t)) ² )} (b) In the above compensation step, The phase is compensated by the following equation (c). {V2 (t) + V1 (t) * sin (Δφ)} / cos (Δφ) (c)

According to the eleventh aspect of the present invention, the detector detects the communication signal and outputs an I signal and a Q signal orthogonal to each other, and the A / D converter is output by the detector.
Convert I and Q signals from analog to digital, respectively.
In other words, the memory previously stores error data of a gain error between the I signal and the Q signal generated in the detector determined based on a test signal, and the compensating means reads the error data from the memory, to compensate for the I signal or the Q signal based on said error data, a demodulation circuit demodulates data on the basis of the I signal and the Q signal. In the twelfth aspect of the present invention, the detector detects the communication signal and outputs an I signal and a Q signal orthogonal to each other, and the memory stores the error of the phase error between the I signal and the Q signal generated in the detector. data previously stored the compensation means reads the error data from the memory, to compensate for the I signal or the Q signal based on said error data, a demodulation circuit demodulates data on the basis of the I signal and the Q signal .

According to the thirteenth aspect of the present invention, the temperature sensor measures the temperature inside the device, the memory stores a plurality of error data corresponding to the plurality of temperatures, and the compensation means includes the temperature sensor. Error data corresponding to the output temperature is read to compensate for the I signal or the Q signal.

In the fourteenth aspect , the local oscillation frequency detector detects the frequency of the local oscillation wave of the detector, and the memory stores a plurality of error data corresponding to a plurality of frequencies, respectively. Compensation means reads error data corresponding to the frequency output from the local oscillation frequency detector to compensate for the I signal or the Q signal.

According to a fifteenth aspect of the present invention, the memory stores the DC offset error Δi of the I signal and the DC offset error Δq of the Q signal, and the i-channel subtractor of the compensating means calculates the DC offset error Δi from the I signal. The DC offset error Δi is subtracted, and the q-channel subtractor subtracts the DC offset error Δq from the Q signal. Claim 1
In the invention of the sixth aspect, a temperature sensor for measuring the temperature inside the device is provided.
Sensor, and the memory has multiple temperatures
Multiple error data corresponding to each are stored, and
Means for detecting an error corresponding to the temperature output by the temperature sensor;
The data is read and the I signal and the Q signal are
At least one is compensated. In the invention of claim 17,
Local oscillation frequency for detecting the frequency of the local oscillation wave of the detector
A wave number detector is provided, and a plurality of
Multiple error data corresponding to each wave number are stored,
The compensation means outputs the local oscillation frequency detector
The error data corresponding to the frequency is read and the I signal and
And at least one of the Q signals.

In the eighteenth aspect of the present invention, the detector detects the communication signal and outputs an I signal and a Q signal orthogonal to each other, and the A / D converter is output by the detector.
Convert I and Q signals from analog to digital, respectively.
In other words, the memory stores a gain error ΔG between the I signal and the Q signal, which is generated in the detector based on a test signal, and the compensator reads error data from the memory. The multiplier of the compensating means adds the gain error ΔG to the I signal or the Q signal.
Multiplied by a coefficient corresponding to the demodulation circuit the I signal and Q
The data output from the A / D converter is demodulated based on the signal.

According to the nineteenth aspect , the detector detects the communication signal and outputs an I signal and a Q signal orthogonal to each other, and the memory stores the phase error Δφ between the I signal and the Q signal. And the compensating means reads the error data from the memory, and the computing unit of the compensating means sets the amplitude of one of the I signal and the Q signal to V
1 (t), and when the other amplitude is V2 (t), the equation {V2 (t) + V1 (t) * si
calculating a n (Δφ)} / cos ( Δφ), and demodulates data on the basis of the I and Q signals.

In the twentieth aspect , when the test wave is input to the detector instead of the communication signal, the error detection circuit detects the error based on the I signal and the Q signal from the detector. The data is obtained and stored in the memory.

In the invention of claim 21 , when the error detection circuit obtains error data, the test signal generator generates a sine wave and supplies it to the detector.

In the invention of claim 22 , the i-channel low-pass filter extracts the low-frequency component of the I signal and outputs a DC offset error Δi, and the q-channel low-pass filter outputs the low-frequency component of the Q signal. The component is extracted and a DC offset error Δq is output.

According to a twenty- third aspect of the present invention, there is provided a detector for detecting a received communication signal to output I and Q signals orthogonal to each other, a memory in which error data generated in the detector is stored in advance, Compensating means for reading error data from the memory and compensating the I signal and the Q signal based on the error data; a demodulating circuit for demodulating data based on the compensated I signal and the Q signal output by the compensating means; When a test wave is input to the detector as the communication signal, the I signal from the detector is
An error detection circuit that obtains the error data based on the signal and the Q signal and stores the error data in the memory, wherein an i-channel square arithmetic circuit squares the I signal, a q-channel square arithmetic circuit squares the Q signal, An i-channel low-pass filter extracts a low-frequency component of the output signal of the i-channel square arithmetic circuit, and a q-channel low-pass filter extracts a low-frequency component of the output signal of the q-channel square arithmetic circuit. An arithmetic circuit based on the output of the i-channel low-pass filter and the output of the q-channel low-pass filter,
The gain error ΔG is calculated.

According to a twenty-fourth aspect of the present invention, there is provided a detector for detecting a received communication signal and outputting an I signal and a Q signal orthogonal to each other, a memory in which error data generated in the detector is stored in advance, Compensating means for reading error data from the memory and compensating the I signal and the Q signal based on the error data; a demodulating circuit for demodulating data based on the compensated I signal and the Q signal output by the compensating means; When a test wave is input to the detector as the communication signal, the I signal from the detector is
An error detection circuit that obtains the error data based on the signal and the Q signal and stores the error data in the memory, wherein an i-channel square arithmetic circuit squares the I signal, a q-channel square arithmetic circuit squares the Q signal, An i-channel low-pass filter extracts a low-frequency component of the output signal of the i-channel square arithmetic circuit, and a q-channel low-pass filter extracts a low-frequency component of the output signal of the q-channel square arithmetic circuit. An arithmetic circuit based on the output of the i-channel low-pass filter and the output of the q-channel low-pass filter,
A gain error ΔG is calculated, and the multiplication circuit calculates the I signal and the Q signal.
The low-pass filter extracts the low-frequency component of the output signal of the multiplication circuit, and the phase error calculation circuit calculates a phase based on the output of the low-pass filter and the output of the gain error calculation circuit. The error Δφ is calculated.

In the invention according to claim 25 , the low-pass filter control means changes the frequency characteristic of the low-pass filter in response to a change in the communication rate.

In the twenty-sixth aspect , the detector detects the communication signal and outputs an I signal and a Q signal that are orthogonal to each other, and the i-channel high-pass filter extracts the high-frequency component of the I signal. The channel high-pass filter is Q
A high-frequency component of the signal is extracted, and a demodulation circuit demodulates data based on the output signal of the i-channel high-pass filter and the output signal of the q-channel high-pass filter. Alternatively, when the DC offset included in the Q signal fluctuates, the i-channel high-pass filter and the q-channel high-pass filter are controlled so that the cutoff frequency is increased.

In the twenty-seventh aspect of the present invention, the reference signal generator of the high-pass filter control means generates a reference signal, and the counter divides the reference signal to generate a control clock for the switched capacitor filter. At the same time, the frequency is supplied to the i-channel high-pass filter and the q-channel high-pass filter, respectively, and the frequency division number control unit decreases the frequency division number of the counter when the DC offset fluctuates.

According to a twenty-eighth aspect of the present invention, the local oscillator generates a local oscillation wave, the detector detects a communication signal based on the local oscillation wave, and outputs an I signal and a Q signal orthogonal to each other. A high-pass filter extracts a high-frequency component of the I signal, a q-channel high-pass filter extracts a high-frequency component of the Q signal, and a demodulation circuit outputs the output signal of the i-channel high-pass filter and the q-channel. Demodulates data based on the output signal of the high-pass filter,
When the control circuit receives the unmodulated signal, the difference between the frequency of the local oscillation wave and the frequency of the unmodulated signal is i
The local oscillator is controlled so as to be higher than both the cutoff frequency of the channel high-pass filter and the cutoff frequency of the q-channel high-pass filter.

According to a twenty- ninth aspect of the present invention, a local oscillator generates a local oscillation wave, a detector detects a communication signal based on the local oscillation wave, and outputs an I signal and a Q signal orthogonal to each other. A high-pass filter extracts a high-frequency component of the I signal, a q-channel high-pass filter extracts a high-frequency component of the Q signal, and an i-channel correction having an inverse characteristic to a pass characteristic of the i-channel high-pass filter. Filter compensates for distortion and the like, the q-channel correction filter having the inverse characteristic to the pass characteristic of the q-channel high-pass filter compensates for distortion and the like, and the demodulation circuit outputs the i-channel correction filter output signal and Data is demodulated based on the output signal of the q-channel correction filter.

According to a thirty-first aspect of the present invention, a local oscillator generates a local oscillation wave, a detector detects a communication signal based on the local oscillation wave, and outputs an I signal and a Q signal orthogonal to each other. Delay means for delaying the I signal;
An i-channel low-pass filter extracts the low-frequency component of the I signal, an i-channel subtractor finds the difference between the output of the i-channel delay means and the output of the i-channel low-pass filter, Delays the Q signal, q
A channel low-pass filter extracts the low-frequency component of the Q signal, a q-channel subtractor obtains the difference between the output of the q-channel delay means and the output of the q-channel low-pass filter, Data is demodulated based on the output signal of the channel subtractor and the output signal of the q-channel subtractor.

In the invention of claim 31 , the antenna performs transmission and reception, the reception unit performs reception processing, and the transmission unit performs error compensation based on transmission error data in the transmission error memory, and then performs transmission processing. A transmission error calculation circuit obtains transmission error data by comparing the coordinates of the data output by the demodulation circuit of the reception section with the coordinates of the transmitted data, and stores the transmission error data in the transmission error memory of the transmission section. When obtaining the transmission error data, when obtaining the transmission error data, the transmission unit generates the transmission signal from the input transmission data and outputs the transmission signal from the amplifier to the detection of the reception unit. To the vessel,
The receiving section outputs the data obtained by compensating and demodulating the supplied transmission signal based on reception error data stored in advance to the transmission error calculation circuit, and the transmission error calculation circuit outputs the data from the demodulation circuit. The transmission error data is obtained by comparing the coordinates of the transmitted data with the coordinates of the transmission data.

In the invention according to claim 32 , the frequency converter converts the frequency of the transmission signal supplied from the amplifier of the transmission section to the detector of the reception section to the frequency of the reception section.

In the invention according to claim 33 , the temperature sensor measures the temperature inside the device, and the transmission error memory stores a plurality of transmission error data corresponding to a plurality of temperatures, respectively. The error compensation circuit
The transmission error data corresponding to the temperature output from the temperature sensor is read to compensate for the I signal and the Q signal.

In the invention of claim 34 , a local oscillation frequency detector detects the frequency of a local oscillation wave of the modulator of the transmitting section, and the transmission error memory corresponds to each of a plurality of local oscillation frequencies. A plurality of transmission error data are stored, and the error compensation circuit reads transmission error data corresponding to the frequency output from the local oscillation frequency detector and compensates for the I signal and the Q signal.

[0086]

【Example】

Embodiment 1 FIG. Hereinafter, the receiving apparatus according to the first embodiment will be described with reference to the drawings. In FIG. 1, reference numeral 1 denotes a low-noise amplifier (LNA) for receiving a received wave of frequency frf (a predetermined sine wave at the time of extracting a vector error) from an antenna (not shown), and amplifying the received wave. A band-pass filter (BPF) 6 for extracting a signal of the band B. A quadrature mixer 6 for mixing the output signal of the band-pass filter 2 and the local oscillation signal of the frequency fp and outputting a baseband I signal and a Q signal. . The I signal and the Q signal are orthogonal to each other.

The quadrature mixer 6 has a 0-degree divider 4 for dividing the output of the band-pass filter 2 into two, a 90-degree phase shifter 5 for delaying the phase of the local oscillation signal supplied from the outside by 90 degrees, Mixer (MIX) 3 for mixing the output signal of distributor 4 and the output signal of 90-degree phase shifter 5 to output an I signal
a, a mixer (MI) that mixes the output signal of the 0-degree distributor 4 with a local oscillation signal supplied from the outside and outputs a Q signal
X) 3b.

Reference numeral 8 denotes a local oscillator (LO) that generates a local oscillation signal and supplies the signal to the quadrature mixer 6. Local oscillator 8
Oscillation frequency changes based on channel setting data supplied from a control circuit (not shown). Reference numerals 9a and 9b denote low-pass filters (LPFs) for extracting low-frequency signals from the I signal and the Q signal output from the quadrature mixer 6, respectively.
Reference numerals a and 10b denote baseband amplifiers (AMP) that amplify the outputs of the low-pass filters 9a and 9b, 11a,
An analog-to-digital converter 11b converts the outputs of the baseband amplifiers 10a and 10b from analog to digital, respectively.

Reference numeral 101 denotes an error detection / compensation circuit for detecting a vector error occurring in the I data and Q data output from the AD converters 11a and 11b and compensating for the error. The error detection / compensation circuit 101 includes an error detection circuit 103 for detecting a vector error, and an error compensation circuit 104 for performing compensation processing on I data and Q data based on the output of the detected error data (memory 102). Is done. Reference numeral 102 denotes a memory for storing error data detected by the error detection and compensation circuit 101. Reference numeral 12 denotes a demodulation operation circuit that performs a demodulation process based on the compensated I ′ data and Q ′ data output from the error detection and compensation circuit 101.

FIG. 2 shows the detailed configuration of the error detection circuit 103. In the figure, reference numeral 107 denotes a DC offset detection circuit for detecting DC offset errors Δi and Δq of I data and Q data. DC offset detection circuit 107
Are low-pass filter calculating means 116a for detecting DC offset error Δi of I data, and low-pass filter calculating means 1 for detecting DC offset error Δq of Q data.
16b.

Reference numeral 108a denotes a low-pass filter operation means 1
A subtraction circuit 108b for obtaining a difference Vi ′ (t) between the DC offset error Δi output from the A / D converter 16a and the I data output from the A / D converter 11a.
This is a subtraction circuit for calculating a difference Vq ′ (t) between the DC offset error Δq output from the A / D converter 16b and the Q data output from the A / D converter 11b.

Reference numeral 105 denotes a gain error detection circuit which detects a gain error ΔG based on Vi ′ (t) and Vq ′ (t) output from the subtraction circuits 108a and 108b and outputs the same to the memory 102. The gain error detection circuit 105 calculates Vi ′
(T), the square of Vq ′ (t) (Vi ′ (t)) ² , (V
q '(t)) ² for each square operation circuit 110 for obtaining ²
a, 110b, (Vi '(t)) ² , (Vq' (t))
² low frequency components (V1 '(t)) ² , (V2' (t)) ²
Low-pass filter operation means 111 for extracting
a, 111b and low-pass filter operation means 111a,
And an operation circuit A112 for obtaining a gain error ΔG based on the output of each of the signals 111b.

Reference numeral 106 denotes a phase error detection circuit which detects the phase error Δφ based on Vi ′ (t), Vq ′ (t) and the gain error ΔG and outputs the phase error Δφ to the memory 102. The phase error detection circuit 106 calculates a product (Vi ′ (t) · Vq ′ (t)) of Vi ′ (t) and Vq ′ (t) by a multiplication circuit 113.
When a low-pass filtering unit 114 for taking out low frequency components of the (Vi '(t) · Vq ' (t)), the constant a ² for outputting and gain error ΔG and below the low-pass filtering unit 114 Arithmetic circuit B1 for obtaining phase error Δφ based on
15.

Note that, for easy understanding, FIG. 2 shows an A / D converter 11, a memory 102, and an error compensation circuit 10.
4, the demodulation operation circuit 12 is also shown.

FIG. 3 shows a detailed configuration of the error compensation circuit 104. In the figure, reference numeral 120 denotes a DC offset compensation circuit that subtracts a DC offset by adding DC offset errors −Δi and −Δq to I data and Q data output from the A / D converters 11a and 11b, respectively. . The DC offset compensating circuit 120 includes an adding circuit 1201a for adding an I channel and an adding circuit 1201b for adding a Q channel.

Reference numeral 121 denotes a gain error compensation circuit that performs gain error compensation on I data and Q data based on the gain error ΔG. The gain error compensation circuit 121 includes a multiplication circuit 1211a that performs multiplication processing for the I channel and a multiplication circuit 1211b that performs multiplication processing for the Q channel. Note that one of the two multiplication circuits may not be provided as described later.

Reference numeral 122 denotes a phase error compensation circuit for compensating a phase error for I data and Q data based on the phase error Δφ. The phase error compensation circuit 122 includes a multiplication circuit 1221a for compensating a phase error for the I channel and a multiplication circuit 1221b for compensating a phase error for the Q channel.
It is composed of Note that one of the two multiplication circuits may not be provided as described later.

Note that, for easy understanding, FIG. 3 shows an A / D converter 11, a memory 102, and an error detection circuit 10.
3, the demodulation operation circuit 12 is also shown.

Next, the operation will be described. The homodyne receiver according to the conventional configuration shown in FIG. 1 uses a quadrature mixer 6 to convert a received wave frf into an I signal and a Q signal in a normal communication operation.
Complex envelope detection with the signal. The quadrature mixer 6 performs analog mixing of the two local oscillation waves fp distributed with a phase difference of 90 degrees from each other by the mixers 3a and 3b and the reception wave frf distributed with the same phase, and performs frequency mixing.

Here, the local oscillation frequency fp and the reception wave frequency
If frf is substantially the same, low-pass filters 9a, 9
b, the I output and the Q output of the quadrature mixer 6 are respectively filtered, and the frequency component of the difference between fp and frf near the baseband frequency is extracted, whereby the modulated signal component of the received wave (RF) is obtained. These I and Q outputs are amplified by the baseband amplifiers 10a and 10b to increase the level, and then quantized by the A / D converters 11a and 11b, respectively.

Then, the error detection / compensation circuit 101 performs compensation processing for each of the I data and the Q data. Error data necessary for compensation is stored in the memory 102 in advance by a procedure described later. Demodulation operation circuit 12
Reproduces data modulated into a received wave based on the I signal data and the Q signal data.

<Operation of Error Detection Circuit 103> Next, an operation for obtaining error data will be described. Before starting communication (either immediately after the power of the device is turned on for communication or at the time of adjustment work at the time of manufacturing the communication device), as shown in FIG. A sine wave is input to this receiver. The sine wave is frequency-mixed with the local oscillation wave fp in the quadrature mixer 6 and further filtered in the low-pass filters 9a and 9b.
The IQ frequency component (angular frequency Δω) of the difference between the local oscillation frequency fp and the sine wave frequency frf is extracted. These I output and Q power are amplified by the baseband amplifiers 10a and 10b, and the level thereof is increased.
a and 11b.

The error detecting circuit 103 in the error detecting and compensating circuit 101 performs a digital operation described later to extract DC offset errors Δi and Δq, a gain error ΔG, and a phase error Δφ. These error data are stored in the memory 102.

Next, the specific contents of the digital operation of the error detection circuit 103 will be described in more detail with reference to FIG.

When a sine wave is injected, the A / D converter 1
I component and Q component voltages Vi input to 1a and 11b
(T) and Vq (t) are given by the following equations similar to the above-mentioned equation (2). Vi (t) = a · cos (Δω · t) + Δi Vq (t) = ΔG · a · sin (Δφ−Δω · t) + Δq (3) where a is the amplitude.

The signals obtained by converting the voltages Vi (t) and Vq (t) into digital signals are input to the error detection circuit 103. These digital signals are first input to the DC offset detection circuit 107. Low-pass filter operation means 116a, 116b of DC offset detection circuit 107
Smoothes the I channel and the Q channel, respectively, and suppresses the Δω component in the above equation (3). By performing such smoothing, Δi and Δq in equation (3)
Is obtained. The DC offset detection circuit 107 writes these Δi and Δq into the memory 102.

These low-pass filter operation means 116
a and 116b are IIR (Infinit Impulse Response)
It is a digital filter such as a filter or a FIR (Finite Impulse Response) filter. Alternatively, it may be a simple time moving average calculation (0th order term of discrete Fourier transform).

The DC offsets Δi and Δq are input to the subtraction circuits 108a and 108b together with the voltages Vi (t) and Vq (t) converted into digital signals. The voltage Vi is calculated by the subtraction circuits 108a and 108b.
DC offsets Δi, Δq are respectively subtracted from (t), Vq (t). By this operation, voltages Vi ′ (t) and Vq ′ (t) in which the DC offset has been corrected are obtained.
The corrected voltages Vi ′ (t) and Vq ′ (t) are input to the gain error detection circuit 105 and the phase error detection circuit 106.

In the gain error detection circuit 105, first,
By the square operation circuits 110a and 110b, Vi '
(T) and the square calculation of Vq '(t) are performed.
Further, (Vi ′ (t)) ^{2 is} obtained by the low-pass filter operation means 111a and 111b having the same operation content (cutoff frequency) as the low-pass filter operation means 116a and 116b.
, (Vq ′ (t)) ² are suppressed. (V1 (t)) ² , (V2 (t)) ² output by the low-pass filter operation means 111a and 111b, respectively.
Is given by: ^{(V1 (t)) 2 =} a 2/2 (V2 (t)) 2 = (ΔG · a) 2/2 (4)

The arithmetic circuit A105 calculates (V1
From (t)) ² and (V ² (t)) ² , the gain error ΔG and the square of the amplitude a ² are obtained. ΔG = {(V2 (t) ) 2 / (V1 (t)) 2} 0.5 a 2 = 2 * (V1 (t)) 2 (5) The gain error .DELTA.G is written into the memory 102. At the same time, the gain error ΔG is output to the phase error detection circuit 106 together with the square of the amplitude a ² .

In the phase error detection circuit 106, first,
The product of Vi ′ (t) and Vq ′ (t) is obtained by the multiplication circuit 113. This result is input to the low-pass filter calculating means 114 having the same calculation content (cutoff frequency) as the low-pass filter calculating means 111, and the product Vi ′ (t) · Vq ′ is obtained.
The 2 · Δω component included in (t) is suppressed. This output (V3 (t)) ² is given by the following equation. (V3 (t)) ² = 0.5 * ΔG * a ² * sin (Δφ) (6)

The arithmetic circuit B106 calculates (V3
(T)) to obtain the phase error Δφ based ² and the gain error ΔG calculated in gain error detection circuit 105 amplitude and squared a ^2. Δφ = sin ⁻¹ {2 * (V3 (t)) ² / (ΔG · a ² )} = sin ⁻¹ {(V 3 (t)) ² / (ΔG · (V 1 (t) ² )} (7) This phase error Δφ is written to the memory 102.

By inputting a predetermined sine wave in accordance with the above procedure, the error detection circuit 103 causes the vector error Δi
, Δq, ΔG and Δφ are extracted and stored in the memory 1
02.

Note that according to the above-described error extraction operation,
If the calculation of the square root of the equation (5) and the calculation of the inverse trigonometric function of the equation (7) are performed by digital operation, the calculation load increases. Further, even when the reference table is used, the memory capacity is increased. Therefore, under the condition that ΔG is close to 1, that is, the condition where the gain error is relatively small, the approximate expression x
Equation (5) may be approximated by the following equation using ^0.5 = 0.5 * (1 + x). ΔG = 0.5 * {(V2 (t)) ² / (V1 (t)) ² + 1} (8)

Further, under the condition that Δφ is close to 0, that is, the phase error is relatively small, Expression (7) may be approximated by the following expression using the approximate expression sin θ = θ. Δφ = 2 * (V 3 (t)) ² / (ΔG · a ² ) = (V 3 (t)) ² / (ΔG · (V 1 (t) ² ) (9)

In the above description, the phase error Δφ is obtained and stored in the memory 102. However, since sin Δφ is used in the error compensation calculation described below, the sin Δφ may be stored in the memory 102.

<Operation of Error Compensation Circuit 104> According to the above procedure, the memory 102 stores error data in advance. At the time of actual communication, the memory 102
The error compensating circuit 104 compensates for the vector error using the error data Δi, Δq, ΔG and Δφ stored in.

Next, the operation of the error compensation circuit 104 will be described in detail with reference to FIG. Error compensation is performed by correcting the coordinates of a code obtained from an actual received wave using vector errors Δi, Δq, ΔG, and Δφ during actual communication.

First, -Δi and -Δq are added to the A / D converted codes I (t) and Q (t) by the adders 1201a and 1201b of the DC offset compensator 120 to compensate for the offset error. Is done. These results are newly designated as codes I (t) and Q (t). I (t) <− (I (t) −Δi) Q (t) <− (Q (t) −Δq) (10)

The signal coordinates at this time are given by the following equation from equation (2). I (t) = d1 (t) Q (t) = ΔG ｛d1 (t) ・ sin (ｔφ) + d2 (t) ・ cos (＋ φ)｝ (11)

Next, the gain error ΔG is compensated for Q (t) by the multiplication circuits 1211a and 1211b of the gain error compensation circuit 121 according to the following equation. This result is newly designated as a code Q (t). Q (t) <−Q (t) / ΔG (12)

The signal coordinates at this time are as follows from equation (11). I (t) = d1 (t) Q (t) =-d1 (t) .sin (.DELTA..phi.) + D2 (t) .cos (.DELTA..phi.) (13)

It should be noted that instead of the formula (12), I (t) <− I
(t)-It may be ΔG.

Next, the multiplication circuits 1221a and 1221b of the phase error compensation circuit 122 compensate the phase error Δφ with respect to Q (t) according to the following equation. This result is newly designated as a code Q (t). Q (t) <− {Q (t) + I (t) * sin (Δφ)} / cos (Δφ) = {V2 (t) + V1 (t) * sin (Δφ)} / cos (Δφ) (14)

By the above calculation, the coordinates of the IQ signal are given by the following equations. I (t) = d1 (t) Q (t) = d2 (t) (15) In this way, correct signal coordinates without error can be obtained.

It should be noted that in order to ease the division of the equation (12), which has a relatively large computational load, I (t) <− I (t) * ΔG (16) (the multiplication circuit 1211b in FIG. ))

In order to alleviate the trigonometric function operation of the equation (14) with a large operation load, the equation (14) can be replaced by the following equation under the condition that Δφ is close to 0, that is, the phase error is relatively small. Good. Q (t) <− ｛Q (t) + I (t) * Δφ｝ (17)

As described above, according to the receiving apparatus of the first embodiment, the error detection circuit detects the vector error and stores it in the memory, and the error compensating circuit compensates the vector error based on the error data stored in the memory. Circuit and
Good BER characteristics can be obtained by removing vector errors.

<Processing Procedure for Error Detection and Error Compensation> FIG.
The following summarizes the procedure of the above-described error detection and error compensation. In the figure, S1 is an error extraction procedure (performed before demodulation), and S2 is an error compensation procedure (during reception). First, an error extraction procedure S1 is executed, and then, an error compensation procedure S2 is executed.

First, a sine wave for extracting an error is input to the receiver (S11). Next, the error detection circuit 103
Detects a demodulation error (S12). Next, the memory 102
The vector error data is written in (S13). And
When communication is started (S21) and actual reception / demodulation is performed, the error compensation circuit 104 reads vector error data from the memory 102 (S22). Next, error compensation is performed based on these data (S23). Then, a demodulation process is performed (S24).

Further, as in S3 in FIG. 5, error extraction may be performed at the time of product manufacture. That is, error extraction is performed in advance at the time of product adjustment after product assembly is completed. After the manufacture and assembly are completed (S31),
A sine wave for extracting an error is input to the receiver (S
32). Next, the error detection circuit 103 detects a demodulation error (S33). Next, the vector error data is written into the memory 102 (S34). Thereafter, the product is shipped (S35). Then, at the time of actual reception / demodulation after shipment, the vector error data stored in advance is read from the memory 102 to perform error compensation.

According to the procedure shown in FIG. 5, in addition to the effects described above, an error is detected from a high-purity sine wave that does not include line noise at a factory, so that error compensation can be accurately performed. There is also an effect.

As described above, according to the receiving apparatus of the first embodiment, there is provided a memory for storing error data, an error extraction step (calibration step) for obtaining error data, and error compensation by receiving an actual communication signal. Is separately provided, error data can be accurately measured based on a pure sine wave, and accurate compensation can be performed. Since the accuracy of this compensation does not change even when the CN ratio of the received signal is low, the compensation method of the receiving apparatus of the first embodiment is particularly close to the communication limit due to the small received signal strength. It is effective when it is a level. This means that the service area is expanded, which is a great advantage. Further, the error compensation circuit 10
4 and the error detection of the error detection circuit 103 are not performed simultaneously. Therefore, power consumption during demodulation during actual communication does not increase, and there is an effect that power consumption can be reduced.

The frequency difference between the sine wave frequency injected into the receiving apparatus and the local oscillation frequency fp input to the quadrature mixer 6 may be within the pass band of the low-pass filter 9. Does not require much accuracy. Therefore, the vector error can be detected with a simple device.

In the above description, the receiver having the homodyne configuration has been described as an example. However, the first embodiment can be applied to the receiver having the heterodyne configuration using the quadrature mixer 6, and the same effect can be obtained. Play.

Although the above description does not describe a specific hardware configuration of the digital operation, even a hardware using a logic circuit is a process based on software such as a DSP or a CPU. The same effect is often achieved.

Embodiment 2 FIG. In the first embodiment, the DC offset was compensated in the error detection compensation circuit 101. However, by providing a high-pass filter (HPF) 6 at the output of the quadrature mixer 6, the DC offset compensation in the error detection and compensation circuit can be omitted.

Hereinafter, the receiving apparatus according to the second embodiment will be described with reference to the drawings. FIG. 6 is a configuration diagram of the receiving device according to the second embodiment. In the figure, reference numerals 60a and 60b denote high-pass filters (HPF) for extracting high-frequency components of output signals of the low-pass filters 9a and 9b, respectively. Also, 1
Reference numeral 30 denotes an error detection / compensation circuit that detects and compensates for a gain error and a phase error. Error detection and compensation circuit 1 of the first embodiment
01 is different in that the detection and compensation of the DC offset are not performed. 7 and 8 show the detailed configurations of the error detection circuit 103 and the error compensation circuit 104 that constitute the error detection and compensation circuit 130, respectively. The same or corresponding parts as those shown in FIGS. 1 to 3 are denoted by the same reference numerals.

The error detecting circuit shown in FIG. 7 and the error compensating circuit shown in FIG. 8 are provided with DC offsets Δi, Δi from the error detecting circuit 103 in FIG. 2 and the error compensating circuit 104 in FIG.
The configuration related to the processing of q is removed. This is because the DC offset is suppressed by the high-pass filters 60a and 60b. Therefore, the memory 10
2 stores only the gain error ΔG and the phase error Δφ. Other operations are exactly the same as those in the first embodiment, and have the same effects.

Further, the error detection and compensation circuit 130 has a DC
Since it is not necessary to perform the detection and compensation calculation of the offsets Δi and Δq, the configuration is simplified, the calculation is performed at a high speed, and the power consumption is further reduced.

As in the first embodiment, the low-pass filter 1
Numerals 11 and 114 are constituted by digital filters such as IIR filters and FIR filters, or simple time-moving average calculators (zero-order terms of discrete Fourier transform).

As in the first embodiment, the difference between the sine wave frequency injected into the receiving device and the local oscillation frequency fp input to the quadrature mixer 6 may be within the pass band of the low-pass filter 9. No setting accuracy is required. Therefore, the vector error can be detected with a simple device.

As in the first embodiment, the present invention can be applied to a heterodyne-type receiving device using the quadrature mixer 6, and the like.
A similar effect is achieved.

As in the first embodiment, any of hardware such as a logic circuit or software such as a DSP or a CPU may be used.

Embodiment 3 FIG. Third Embodiment A third embodiment relates to a receiving device in which a sine wave source (transmitting device) used for error detection is provided in the receiving devices shown in the first and second embodiments. Hereinafter, the receiving apparatus according to the third embodiment will be described with reference to the drawings. In FIG. 9, a transmission device 134 generates a sine wave used for error detection and inputs the sine wave to the low noise amplifier 1 of the reception device. The same or corresponding parts as in the first embodiment of FIG. 1 are denoted by the same reference numerals.

Next, the operation will be described. The specific operation of the error detection and compensation in the third embodiment is described in the first or second embodiment.
Is the same as In this embodiment, a sine wave source used for error detection is provided in the apparatus. According to the third embodiment,
Exactly the same effects as those of the first or second embodiment can be obtained.

FIG. 10 shows the processing procedure. First, when the power is turned on (S41), the sine wave source 134 in the transceiver generates a sine wave and inputs the sine wave to the low noise amplifier 1 of the receiving device 133 (S42). Then, a demodulation error is detected as in the first embodiment (S43), and error information is written into the memory 102 (S44). Based on these error information, error compensation is performed in the next process (S2).

Therefore, according to the third embodiment, FIG.
According to the procedure shown in FIG. 0, error detection can be performed for each communication before starting communication, so that error detection and error compensation can be performed based on error data measured immediately before, so that the accuracy of compensation is improved. I do. Further, the error detection can be performed at any time, which is convenient. Further, compared with the error detection at the time of manufacturing shown in the first embodiment, there is an advantage that the error does not change over time.

Although the above description has been made with respect to the receiver having the homodyne configuration, a receiver having a heterodyne configuration using the quadrature mixer 6 may be used, and the same effects can be obtained.

Embodiment 4 FIG. In the fourth embodiment, the sine wave used for the error detection of the receiving apparatus shown in the first and second embodiments is
The present invention relates to a communication system supplied from a base station facing a receiving device. The communication system according to the fourth embodiment will be described below with reference to the drawings. In FIG. 11, reference numeral 135 denotes a base station transmitter. The same or corresponding parts as in the first embodiment of FIG. 1 are denoted by the same reference numerals.

Next, the operation will be described. The operation of error detection / compensation is the same as in the first or second embodiment. In this embodiment, a sine wave source used for error detection is
5 is supplied.

In satellite communication or the like, as shown in FIG. 12, for example, communication modulated waves f _{1 to} f ₄ are transmitted from base station transmitting apparatus 13.
5 and an unmodulated sine-wave pilot signal f _pilot as a reference source for antenna beam alignment and reception frequency is often transmitted from the base station. Therefore, in this embodiment, a pilot signal f _pilot transmitted from the base station is used as a sine wave to be injected into the receiving device.

The specific error detection and
The operation of the compensation is exactly the same, and the first and second embodiments
Has the same effect as. Further, the error detection can be performed at any time, which is convenient, the accuracy of compensation is improved, and there is no need to provide a transmission device inside the device, and the configuration is simplified. In addition, compared with the conventional calibration using a modulated reception wave (References 5 and 6), since a narrow band sine wave is used, a good CN can be obtained, and high detection accuracy can be obtained.

FIG. 13 shows the processing procedure. First, when the power is turned on (S51), reception of a signal from the base station is started (S52), and a pilot signal of a communication partner is supplemented (S53). Then, a demodulation error is detected as in the first embodiment (S54), and error information is written to the memory 102 (S55). The next processing (S
Error compensation is performed in 2).

Therefore, according to the fourth embodiment, FIG.
According to the procedure shown in FIG. 3, since error detection can be performed for each communication before communication is started, there is an effect that higher-precision error detection and error compensation can be performed. further,
It is convenient that error detection can be performed at any time.

The above description has been made with respect to the receiver having the homodyne configuration. However, a receiver having a heterodyne configuration using the quadrature mixer 6 may be used, and the same effects can be obtained.

Embodiment 5 FIG. In the fifth embodiment, the sine wave used for the error detection of the receiving device shown in the first and second embodiments is
The present invention relates to a communication system supplied from a base station facing a receiving device. Hereinafter, the communication system of the fifth embodiment will be described with reference to the drawings. In FIG. 14, reference numeral 136 denotes a base station transmitting device. The same or corresponding parts as in the first embodiment of FIG. 1 are denoted by the same reference numerals.

Next, the operation will be described. Error detection / compensation is the same as in the first or second embodiment. In this embodiment, a sine wave source used for error detection is a transmitter of a base station. In digital modulation schemes (PSK, QAM, etc.) that have recently become popular in satellite communications and mobile communications, as shown in FIG.
Before communication modulated wave from the base station (random pattern period T ₂₎ is transmitted, often sinusoidal unmodulated (CW) is transmitted as a reception frequency synchronization (time period T
₁ ). Therefore, using a CW signal transmitted in the period T ₁ from the base station as a sine wave is injected to the receiving device in this embodiment.

In the fifth embodiment, specific error detection and
The operation of the compensation is exactly the same, and the first and second embodiments
Has the same effect as. Further, the error detection can be performed at any time, which is convenient, the accuracy of compensation is improved, and there is no need to provide a transmission device inside the device, and the configuration is simplified. The fifth embodiment is applicable to a communication system having no pilot signal as in the fourth embodiment.

FIG. 16 shows the processing procedure. First, when the power is turned on (S51), reception of a signal from the base station is started (S62), and a non-modulated wave (sine wave) at the head of a transmission code of a communication partner is supplemented (S63). Then, a demodulation error is detected as in the first embodiment (S64), and error information is written to the memory 102 (S65). Based on these error information, error compensation is performed in the next process (S2).

Therefore, according to the fifth embodiment, FIG.
According to the procedure shown in FIG. 6, since error detection can be performed for each communication before starting communication, there is an effect that error detection and error compensation with higher accuracy can be performed. further,
It is convenient that error detection can be performed at any time. In particular, in the time division multiplexing method, since error detection can be performed for each burst, detection and detection with higher accuracy than in the fourth embodiment can be performed.
There is also an effect that compensation can be performed.

The above description has been made with respect to the receiver having the homodyne configuration. However, the receiver having the heterodyne configuration using the quadrature mixer 6 may have the same effect.

Embodiment 6 FIG. In the sixth embodiment, the error detection circuit 103 of the receiving device shown in the first and second embodiments is provided outside the receiving device separately from the receiving device. Hereinafter, the receiving apparatus of the sixth embodiment will be described with reference to the drawings. In FIG. 17, reference numeral 137 denotes a calibration device including the error detection circuit 103, and 138 denotes a receiving device. The same or corresponding parts as in the first embodiment of FIG. 1 are denoted by the same reference numerals.

Next, the operation will be described. The operation of error detection / compensation is the same as in the first or second embodiment. This embodiment is the same as the first and second embodiments including the operation, except that the error detection circuit 103 is provided outside the receiving device 138. When a sine wave for error detection is injected into the receiving device 138, an external error detection circuit 103 detects an error based on data output from the A / D converter 11. Then, the error data is written into the memory 102 inside the receiving device 138. Using the result, error compensation is performed at the time of actual communication.

In this embodiment, the error detection circuit 103 is provided outside the receiving device 138, and an error is detected at the time of manufacturing the receiving device 138, for example. Therefore, there is an effect that the configuration of the device can be simplified and downsized as compared with the first and second embodiments. Further, when a computer using a microprocessor or the like is used as the calibration device 137 having the error detection circuit 103, Basi
A high-level language such as c, Fortran, or C can be used. Therefore, a floating-point operation with an increased number of significant digits, a function such as an inverse trigonometric function or a square root can be used, and there is an effect that the accuracy of error detection can be improved.

It should be noted that, as shown in FIG.
May be provided in the calibration device 137. FIG.
According to the configuration described above, the number of signal lines connecting the receiving device 138 and the calibration device 137 can be reduced.

The above description has been made with respect to the receiver having the homodyne configuration. However, the receiver having the heterodyne configuration using the quadrature mixer 6 may have the same effect.

In the above description, a computer using a microprocessor as the calibration device 137 has been described as an example. However, even if the H / W is a logic circuit, the S / W such as a DSP or CPU may be used.
May be used, and the effect of reducing the size of the receiving device does not change at all.

Embodiment 7 FIG. In the seventh embodiment, the cutoff frequency of the low-pass filter operation means 111, 114, and 116 of the error detection circuit shown in FIG. 2 of the first embodiment and FIG. 7 of the second embodiment can be varied. Hereinafter, this embodiment 7
The configuration of the low-pass filter calculation means applied to the error detection circuit of FIG. In FIG.
Reference numeral 140 denotes an FIR filter, which includes delay elements 142 a to 142 e cascade-connected, an input signal and a delay element 14.
2a to 142e, a predetermined tap coefficient h
_n (n is an integer, 1 to 6)
43a to 143f and adders 144a to 144e for adding the outputs of the multipliers 143a to 143f, respectively. 141 is a tap coefficient h _n rewriting means for rewriting the tap coefficients h _{1 to} h ₆ of the FIR filter 140 input from the outside.

Next, the operation will be described. Example 7
Is the low-pass filter operation means 1 of the error detection circuit 103
FIR filter 14 used for 11, 114, 116
The tap coefficient of 0 can be rewritten by the rewriting means 141. Thereby, the cut-off frequency of the low-pass filter operation means 111, 114, 116 can be changed as needed.

For example, in a mobile communication receiver,
There is a multi-rate system corresponding to a plurality of systems having different communication rates. In this case, the receiving device must be able to support various communication rates. In the receiving apparatus of the seventh embodiment, upon receiving rate information from a control unit (not shown), the rewriting means 141 operates the low-pass filter calculating means 1 so as to obtain optimum filter characteristics for this rate.
Determining the tap coefficient h _n of 11,114,116. Since the same tap coefficient is supplied to these three types of filters, the characteristics of these filters are all the same. In addition,
Since the rate information is notified from a control device such as a CPU before communication, the rate can be easily known in the receiving device.

Thus, for example, even when a single receiving apparatus is used for systems having different transmission speeds, this error detection method can be applied.

The above description has been made with respect to the receiver having the homodyne configuration. However, the receiver having the heterodyne configuration using the quadrature mixer 6 may have the same effect.

Embodiment 8 FIG. In the eighth embodiment, the accuracy of the error detection in the error detection circuit 103 of the receiving apparatus shown in the first and second embodiments is improved by repeating the detection a plurality of times. FIG. 20 is a configuration diagram of the receiving apparatus according to the eighth embodiment. The receiving device of FIG. 20 and the receiving device of FIG.
20, the difference is that the error detection circuit 103 detects an error based on the output I ′ signal and the Q ′ signal of the error compensation circuit 104.

Next, the operation of the receiving apparatus according to the eighth embodiment will be described with reference to FIG. In the figure, S7 is an error detection procedure, and S2 is an error compensation procedure.

The first error detection calculation in S7 is the same as in the first and second embodiments. That is, a sine wave is input to the receiver (S71), and a demodulation error is detected (S7).
4) Write error information in the memory 102 (S75).
At this time, since the memory 102 does not store the error data, the error compensation circuit 104 performs
Alternatively, error compensation is performed based on a predetermined initial value.

On the other hand, in the second and subsequent times, the error information written in the previous error detection calculation is read from the memory 102, and the IQ data is compensated by the error compensation circuit 104. Error detection is performed again based on these IQ data. The error information written in the memory 102 is corrected based on the detection result. That is, a sine wave is input to the receiver (S71), and error information is read from the memory (S7).
2) The IQ data of the receiver is corrected (S73), a demodulation error is detected (S74), and the corrected error information is written to the memory (S75).

The same applies to the third and subsequent times. A value newly obtained from the value stored in the memory 102 is corrected by adding a DC offset or a phase error and multiplying a gain error.

Since the error detection calculation is repeatedly performed as described above, the accuracy of the error detection calculation can be improved. In particular, when various approximation operations performed to reduce the load of digital operations such as the DSP described in the first embodiment are used,
The effect of high precision is remarkably obtained.

The above description has been made with respect to the receiver having the homodyne configuration. However, a receiver having a heterodyne configuration using the quadrature mixer 6 may have the same effect.

In the above description, H / W of digital operation is not described. However, H / W by a logic circuit or processing based on S / W of a DSP or CPU may be used. Has the effect of

Embodiment 9 FIG. In the ninth embodiment, a temperature sensor is provided in the receiving device shown in the first and second embodiments,
The output data of this sensor is used as an address of the memory 102. Various errors of the receiving apparatus are not always constant, but fluctuate due to external factors such as temperature. Therefore,
Even if compensation is performed based on error data stored in the memory, it is difficult to completely eliminate the error depending on external factors at that time. This is particularly problematic when compensating based on errors measured during factory shipment. The ninth embodiment aims to solve such a problem.

The receiving apparatus according to the ninth embodiment will be described below with reference to the drawings. In FIG. 22, reference numeral 151 denotes a temperature sensor for detecting the temperature inside the apparatus. The temperature data output from the temperature sensor 151 is input to the memory 102 as an address. That is, the memory area and data accessed by the memory 102 are switched according to the temperature. The same or corresponding parts as in the first embodiment of FIG. 1 are denoted by the same reference numerals.

Next, the operation will be described. Error detection compensation circuit 1
Operations such as 03 are the same as those in the first embodiment. In the ninth embodiment, the error extraction procedure S1 of FIG.
It is repeated for different temperatures. Memory 10
The error stored in 2 is caused by unbalance of the quadrature mixer 6 and the baseband amplifier 10, and these are values that depend on temperature. Therefore, as shown in FIG. 23, for example, data at temperatures of −10 ° C., 0 ° C.,. FIG. 22 shows that the above-mentioned temperatures correspond to the codes corresponding to the respective temperatures (this is
, 001,... 111, and the DC offset errors are Δ ₀ , Δ ₁ ,..., Δ ₇ , and the gain errors εg ₀ , εg ₁ , respectively.
... εg ₇ , phase errors εφ ₀ , εφ ₁ , εφ ₇
Is shown.

On the other hand, in S2 of FIG. 4 of the first embodiment, when the error information is read from the memory (S22), the address to be read is specified by the temperature data of the temperature sensor 151. Is read. For example, when the temperature is −10 ° C., the memory 10
2 address 000 is specified and the DC offset error Δ
₀ , gain error εg ₀ and phase error εφ ₀ are read.
The same applies to other temperatures 0 ° C.,... 70 ° C.

As described above, according to the ninth embodiment, error data for various device temperatures are stored, and the optimum error data is read out from the compensation amount corresponding to the actual device temperature and compensated. Optimal compensation can be performed according to the temperature. As a result, the deterioration of the error compensation due to the temperature change can be suppressed, and the accuracy can be improved.

In the above description, the case where the temperature versus the error is stored in the memory 102 has been described as an example. As can be seen from FIG. 23, errors are stored at certain constant temperature intervals.
The intermediate temperature may be adjusted to the address of the memory 102 by truncating or rounding off lower bits of the temperature data serving as an address. The intermediate temperature may be obtained by interpolation (linear interpolation, Lagrange interpolation, spline interpolation, etc.) from the temperature versus error data in the memory 102, which has the effect of further improving the accuracy.

Although the above description has been made with respect to the receiver having the homodyne configuration, a receiver having a heterodyne configuration using the quadrature mixer 6 may be used, and the same effect can be obtained.

In the above description, the H / W of digital operation is not described. However, the H / W by a logic circuit or the processing based on S / W of a DSP or CPU may be used. Has the effect of

Embodiment 10 FIG. In the tenth embodiment, in the receiving apparatuses shown in the first and second embodiments, the receiving frequency (local oscillation frequency) is used as the address of the memory 102. Various errors of the receiving apparatus are not always constant, but fluctuate with a change in frequency. Therefore, even if compensation is performed based on the error data stored in the memory, it is difficult to completely remove the error depending on the change in frequency at that time. The tenth embodiment aims to solve such a problem.

The receiving apparatus according to the tenth embodiment will be described below with reference to the drawings. In FIG. 24, reference numeral 152 denotes data conversion means for converting channel setting data for setting a predetermined frequency channel for the local oscillator 8 into an address of the memory 102. The same or corresponding parts as in the first embodiment of FIG. 1 are denoted by the same reference numerals.

Next, the operation will be described. Error detection compensation circuit 1
Operations such as 03 are the same as those in the first embodiment. In the tenth embodiment, an error extraction procedure S1 of FIG.
Is repeatedly performed for various channel frequencies. The error stored in the memory 102 is caused by the imbalance of the quadrature mixer 6 and the baseband amplifier 10, and these are values that depend on the reception frequency. Therefore, when there are 16 reception channels, as shown in FIG.
Error data for each of ₀ , f ₁ ,... F ₁₅ is stored in the memory 102. FIG. 25 shows that the above-mentioned frequencies correspond to the codes corresponding to the respective frequencies (this is the memory 1
0000, 0001,... 1
111, and for each, the DC offset error is Δ ₀ , Δ ₁ ,... Δ ₁₅ , the gain error εg ₀ ,
εg ₁ ,... εg ₁₅ , phase error εφ ₀ , εφ ₁ ,.
- shows that εφ is _15.

On the other hand, in S2 of FIG. 4 of the first embodiment, when the error information is read from the memory (S22), the address to be read is specified by the data from the data conversion means 152 for converting the channel frequency. Is read out. For example, when the frequency is f ₀ , the address 0000 of the memory 102 is designated, the DC offset error Δ ₀ , the gain error εg ₀ ,
The phase error εφ ₀ is read. Other frequencies f ₁ , ...
The same applies to the · f _15.

In the above description, an explanation has been given of the case where the received frequency versus the error is stored in the memory 102. Here, with respect to the intermediate frequency between the addresses, the lower bits of the frequency data are truncated or rounded off, and the memory 102
Address. Alternatively, the memory 102
(Linear interpolation, Lagrangian interpolation, spline interpolation, etc.) may be obtained from the data of the frequency vs. error, which has the effect of further improving the accuracy.

In the above description, the reception frequency is stored in the memory 10
Although the case of using the address of 2 has been described, the temperature of the ninth embodiment may be used as the address simultaneously with the reception frequency.
In this case, for example, the address is divided into two, and the frequency and the temperature correspond to each other. Alternatively, an address obtained by adding the frequency data and the temperature data is used as an address. As a result, the fluctuation of the error with respect to the temperature and the frequency can be suppressed, and there is an effect that the accuracy is further improved.

The above description has been made with respect to the receiver having the homodyne configuration. However, a receiver having a heterodyne configuration using the quadrature mixer 6 may be used, and the same effects can be obtained.

In the above description, H / W of digital operation is not described. However, H / W by a logic circuit or processing based on S / W of a DSP or CPU may be used. Has the effect of

Embodiment 11 FIG. In the eleventh embodiment, for example, in a receiving apparatus including a high-pass filter (HPF) for suppressing a DC offset shown in FIG. 46 or FIG. 47, distortion of a transmission code due to the high-pass filter is suppressed. It is a receiving device that can be used.

The receiving apparatus according to the eleventh embodiment will be described below with reference to the drawings. In FIG. 26, 153a, 1
53b is provided after the low-pass filters 9a and 9b for the respective IQ signals, a high-pass filter (HPF) using a switched capacitor, 154 is a clock (frequency Fsc) for driving a switch capacitor, and 15
Reference numeral 5 denotes a counter for dividing the frequency of the clock 154, and the number of divisions N can be changed by external control data. 160
Is a control circuit that controls the frequency division number of the counter 155 and outputs channel setting data for controlling the oscillation frequency of the local oscillator 8. The same or corresponding parts as in the first embodiment of FIG. 1 are denoted by the same reference numerals.

FIG. 27 shows a configuration example of a high-pass filter (HPF) 153 using a switched capacitor. 156a and 156b are switches for opening and closing the feedback circuit of the operational amplifier 158. When these switches are closed, a feedback circuit is formed and a capacitor (C _c2 ) 157 having one end grounded.
b is connected to this feedback circuit. 156a and 156b are switches for opening and closing the input circuit. When these switches are closed, the input terminal of the operational amplifier 158 through the capacitor C ₀ - is connected to the input terminal, the input terminal, one end is connected to a capacitor which is grounded (C _c1).

The switches 156a to 156d are opened and closed by the divided clock output from the counter 155 (frequency Fsc / N). When the switches 156a to 156d are closed, the charges stored in the capacitors C _C1 and C _C2 are discharged, and become equivalent to resistance. And this resistance value changes with the opening and closing cycle of the switch. Therefore, when the switching cycle of the switch is changed, the characteristics of the filter shown in FIG.
7 (b)) changes. Since the cutoff frequency fc of the high-pass filter 153 is given by the following equation, the cutoff frequency fc can be controlled by the frequency division number N of the counter 155. fc = Fsc · Cc1 / (2π · N · Cc2) (18)

Next, the operation will be described. High-pass filter 1
When a code having a DC offset as shown in FIG. 28A is passed through 53a and 153b, the cut-off frequency fc of the filter is compared with the transmission speed in order to prevent the code from being distorted in a steady state. It is necessary to set a sufficiently low cutoff frequency. For example, the period T _{1 in} FIG.
It is necessary to lower the cut-off frequency fc in and period T _3. In the configuration according to the present embodiment, the frequency division number N of the counter 155 can be increased by external control data, and the cutoff frequency fc given by equation (18) can be reduced.

On the other hand, in the period T ₂ in FIG.
In order to suppress the DC offset fluctuation caused by the frequency change of the local oscillator 8 from being superimposed on the code, the frequency division number N of the counter 155 is reduced, and the high-pass filters 153a and 153
It is necessary to increase the cutoff frequency fc of 3b. The period T ₂ are are determined by system, it is notified in advance from such CPU.

The control circuit 160 controls the frequency division number N of the counter 155 so as to satisfy the above conditions. As a result, as shown in FIG. 28B, when the DC offset is constant (periods T ₁ and T ₃ ), the output waveform is not distorted. Further, when the DC offset fluctuates (period T ₂ ), the fluctuation immediately attenuates. Therefore, adverse effects due to this variation are prevented. In addition,
The fluctuation of the DC offset occurs when the communication condition changes. This switching time (period T ₂ ) is a guard time in a no-communication state, and the communication system has a problem if the influence of the DC offset ends within this period. Absent. The switching time of the frequency and the like is about several tens μs to several ms.

As described above, according to the eleventh embodiment,
Since the cutoff frequency fc of the high-pass filter 153 is optimally changed in accordance with the code transmission situation, it is possible to suppress the deterioration of the BER due to the intersymbol interference in the high-pass filter 153.

The above description has been made with respect to the receiver having the homodyne configuration. However, a receiver having a heterodyne configuration using the quadrature mixer 6 may be used, and the same effect can be obtained.

Embodiment 12 FIG. In the twelfth embodiment, a non-modulated carrier (C
W) is suppressed. Hereinafter, Example 1
2 will be described with reference to FIG. In FIG. 29,
A control circuit 161 controls a frequency synthesizer used as the local oscillator 8. The same or corresponding parts as in the first embodiment of FIG. 1 are denoted by the same reference numerals.

Next, the operation will be described. In the case of receiving an unmodulated carrier (CW), if the frequency frf of the received wave matches the frequency fp of the local oscillator 8, the output of the quadrature mixer 6 becomes DC as shown in FIG. As a result, the output signal is attenuated by the high-pass filter 60 and unmodulated carriers are cut off.

[0209] By the way, in normal communication, the CW is at the head of the code for the purpose of carrier reproduction or the like, so that its occurrence time can be predicted in advance. Therefore, in the present embodiment, in order to pass the CW, the control circuit 161 controls the local oscillator 8 so that the frequency frf of the received wave and the frequency fp of the local oscillator 8 are shifted by more than the cutoff frequency of the high-pass filter 60. Control.

In this case, even if the received wave is CW, the frequency at the output of the quadrature mixer 6 becomes the absolute value of (frf-fp) and passes through the high-pass filter 60. By controlling the frequency of the local oscillator 8 in this way, even a receiving device having the high-pass filter 60 can receive CW.

In the above description, a configuration in which the output frequency fp of the local oscillator 8 is directly controlled by the control circuit 161 has been taken as an example. However, as shown in FIG. VCXO) may be applied and controlled to achieve the same effect.

In the above description, the configuration in which the output frequency fp of the local oscillator 8 is directly controlled has been described. However, the control circuit may not be provided, and the frequency of the local oscillator 8 may be offset from the beginning. Effect.

The above description has been made with respect to the receiver having the homodyne configuration. However, a receiver having a heterodyne configuration using the quadrature mixer 6 may be used, and the same effects can be obtained.

Embodiment 13 FIG. The thirteenth embodiment is intended to suppress the distortion of the code due to the high-pass filter for suppressing the DC offset and the accompanying deterioration of the BER. Hereinafter, the receiving apparatus according to the thirteenth embodiment will be described with reference to the drawings. In FIG. 31, 163a and 163b are high-pass filters 60
This is a digital filter having impulse response characteristics opposite to those of a and 60b. The same or corresponding parts as those of the second embodiment in FIG. 1 are denoted by the same reference numerals.

Next, the operation will be described. The high-pass filters 60a and 60b for suppressing DC offset have an impulse response characteristic shown in the lower part of FIG. This causes interference with adjacent codes. On the other hand, the digital filter 163
a and 163b have the impulse response characteristics shown in the upper part of FIG. Impulse response characteristics of high-pass filters 60a and 60b and digital filters 163a and 163b
The characteristics are mutually opposite characteristics as can be seen from FIG. Therefore, the digital filters for correction 163a,
163b cancels the impulse response of the high-pass filters 60a and 60b. Thereby, the high-pass filter 6
Code distortion due to 0a and 60b and BER degradation associated therewith can be suppressed.

In the above description, the digital filter 16
3 is not described, for example, II
An R, FIR filter or the like may be used, and the same effect is obtained.

The above description has been made with respect to the receiver having the homodyne configuration. However, a receiver having a heterodyne configuration using the quadrature mixer 6 may be used, and the same effects can be obtained.

Embodiment 14 FIG. In the fourteenth embodiment, an alternative to the high-pass filter is provided in order to suppress the distortion of the code due to the high-pass filter for suppressing the DC offset and the accompanying deterioration of the BER.

Hereinafter, the receiving apparatus of this embodiment will be described with reference to the drawings. In FIG. 33, 170a, 170
b is a low-pass filter (LPF) for extracting low-frequency components from the outputs of the baseband amplifiers 10a and 10b, respectively.
It is. Outputs of the low-pass filters 170a and 170b are DC offsets Δi and Δq, respectively. 171
a and 171b are delay lines for respectively delaying the outputs of the baseband amplifiers 10a and 10b by a predetermined time, 172a
Is a low-pass filter 170 from the output of the delay line 171a.
A subtractor 172b for subtracting Δi which is the output of a is a subtractor for subtracting Δq which is the output of the low-pass filter 170b from the output of the delay line 171b. Subtractor 172
a and 172b are output from the A / D converters 11a and 11a, respectively.
11b. The same or corresponding parts as those of the second embodiment in FIG. 1 are denoted by the same reference numerals.

Next, the operation will be described. Baseband amplifiers 10a and 10b, which are modulated signals including a DC offset
Are smoothed by the low-pass filters 170a and 170b. Usually, the modulation signal is random,
If the time constants of the low-pass filters 170a and 170b are set to a sufficiently long time, the modulation signal becomes 0 V, and the DC offsets Δi and Δq can be extracted.

Also, baseband amplifiers 10a and 10b
Is delayed by delay lines 171a and 171b having the same delay time as the low-pass filters 170a and 170b. From these delayed IQ signals, a subtractor 17
The DC offsets Δi and Δq are respectively subtracted by 2a and 172b. This removes the DC offset.

At this time, the low-pass filters 170a, 170
If the time constant of 70b is set to a sufficiently long time, the high-pass filter is not used, so that the BER does not deteriorate due to intersymbol interference.

When the time constant of the low-pass filter 170 is sufficiently longer than the transmission speed and the DC offset does not fluctuate in a short time, the same effect can be obtained without providing the delay line 171. .

In the above description, the AD converters 11a, 11a
Although the configuration for correcting the input potential of 1b has been described as an example, as shown in FIG. 34, the configuration is such that the midpoint potentials (or reference potentials) of the AD converters 11a and 11b are corrected by adders 173a and 173b, respectively. It may have the same effect.

In the above description, the A / D converter 11
The configuration for correcting the input potentials of a and 11b has been described as an example. However, as shown in FIG. 35, a configuration for correcting by digital operation after A / D conversion may be used, and the same effect is achieved.

Although the above description has been made with respect to the receiver having the homodyne configuration, a receiver having a heterodyne configuration using the quadrature mixer 6 may be used, and the same effects can be obtained.

Embodiment 15 FIG. Fifteenth Embodiment A fifteenth embodiment relates to a transmission / reception apparatus which corrects a vector error of a modulated wave of a transmission apparatus by using the completely calibrated high-accuracy reception apparatus of the first or second embodiment.

Hereinafter, the transmitting / receiving apparatus according to the fifteenth embodiment will be described with reference to the drawings. In FIG. 36, reference numeral 200 denotes an arithmetic circuit for calculating an error between a demodulated code obtained from the output of the demodulation arithmetic circuit 12 on the receiving device side and a code modulated on the transmitting device side, and 201 stores the error between transmission and reception. A memory 202 is an error compensating circuit for compensating an error included in a modulation output of the modulation signal generating circuit 57 based on error data of the memory 201, and 203 is an antenna (ANT) not shown
Or a switch for switching the signal flow from the antenna. Here, the conventional example of FIG.
The same or corresponding parts as in the first embodiment are denoted by the same reference numerals.

Next, the operation will be described. FIG. 36 is a configuration example of a transmission / reception device having the same transmission / reception frequency. The transmitting device as well as the receiving device shows an example of a homodyne configuration.

Here, it is assumed that the receiving apparatus has already completed the vector error compensation based on the sine wave for error detection.

In the transmitting / receiving apparatus of FIG. 36, first, a vector error of a modulated wave of the transmitting apparatus is obtained. The modulation signal generation circuit 57 performs vector modulation with the modulation data. This modulation output is input to the error compensating circuit 202. At this stage, since no compensation data is stored in the memory 201,
No compensation is provided. A part of the transmission wave vector-modulated according to the modulation signal output of the signal generation circuit 57 is connected to the switch 20.
3 and is input to the low noise amplifier 1 on the receiving device side.
The transmitted wave is detected by the quadrature mixer 6, the error on the receiving device side is compensated, and the code is reproduced by the demodulation operation circuit 12. Assuming that the compensation at the receiving device has been completely performed, if an error occurs in the generated code, this is due to an error at the transmitting device.

By the way, the data of the coordinates transmitted from the transmitting device side is obtained, and the original modulation coordinates can be known. Therefore, the arithmetic circuit 200 compares the coordinates demodulated by the demodulation arithmetic circuit 12 with the original coordinates of the transmission wave, and obtains an error therebetween. For example, the coordinates of 4 points for QPSK and 16 points for 16QAM are known, and this error detection is easy. After detecting the error, the arithmetic circuit 200 stores the error data of the transmission wave in the memory 201.

Then, at the time of the next transmission, the error compensating circuit 202 corrects the coordinates based on the error data in the memory 201 before transmitting. As a result, a modulation error occurring in the transmission signal can be removed.

As described above, since the coordinates of the transmission wave are corrected using the high-accuracy receiving apparatus, high vector accuracy of the transmission wave can be obtained, and there is an effect that BER deterioration due to a modulation error can be suppressed.

In the above description, the timing of extracting the vector error of the transmitted wave is not described.
(2) At the start of communication, (3) in the case of TDMA, every burst, or (4) at any time of transmission, the same effect can be obtained.

The above description has been made with reference to a transmission / reception apparatus having the same transmission frequency and reception frequency as an example.
As shown in FIG. 7, transmission / reception devices having different transmission / reception frequencies may be used. In FIG. 37, reference numeral 207 denotes a frequency converter that matches the frequency of the transmission signal with the frequency of the reception signal. The frequency converter 207 includes a band-pass filter (B) that extracts a signal of a predetermined band from a transmission signal from the transmission device.
PF) 204b, a local oscillator (LO) 20 for generating a local oscillation wave having the same oscillation frequency as the transmission / reception frequency difference
5. Output of band-pass filter 204b and local oscillator 20
(MIX) 206 that mixes the outputs of
And a band-pass filter 204a for extracting a signal in a predetermined band from the output of the band 06. Frequency converter 207
Is specially provided in place of the original antenna of the transmission / reception device in order to obtain an error.

The configuration of FIG. 38 is the same as that of FIG. 37, except that the transmission signal is corrected by the frequency converter 207 for the transmission / reception frequency difference and then supplied to the receiving device side, and has the same effect. However, the time when the vector error of the transmission wave is extracted according to the above-described procedure is at the time of manufacturing or adjusting a product because the frequency converter 207 is provided outside the transmitting / receiving device for extracting the error.

The above description has been made with respect to a receiver having a homodyne configuration, but a transmitter having a heterodyne configuration using the quadrature mixer 38 may also provide the same effect.

Although the above description does not describe H / W of digital operation, H / W by a logic circuit or processing based on S / W of a DSP or CPU may be used. Has the effect of

Embodiment 16 FIG. In the sixteenth embodiment, the transmission frequency is used as an address of the memory 201 for storing the vector error of the modulated wave of the transmitting and receiving apparatus shown in FIG. Hereinafter, the transmitting / receiving device of the embodiment 16 will be described with reference to the drawings. 38, a data conversion circuit 210 converts channel setting data to the local oscillator 8 into an address of the memory 102. 1 and 36
The same or corresponding parts as in Examples 1 and 15 are denoted by the same reference numerals.

Next, the operation will be described. Although the frequency dependency of the error in the receiving apparatus has been described in the tenth embodiment, the same applies to the transmitting apparatus. The error stored in the memory 201 is caused by the imbalance of the quadrature mixer 38 and the baseband amplifier 55. Among these, the error due to the quadrature mixer 38 is a value that depends on the transmission frequency. Therefore, if an error is stored for each transmission frequency in the memory 201 as in the table of FIG. 25 of the tenth embodiment, the error compensation amount can be changed according to the transmission frequency. As a result, deterioration due to the transmission frequency in error detection and compensation can be suppressed, and higher accuracy can be achieved.

In the above description, the case where the table of the transmission frequency versus the error is stored in the memory 201 has been described. Here, for the intermediate frequency between addresses, the lower bits of the frequency data may be truncated or rounded off to match the address of the memory 201. Alternatively, it may be obtained by interpolation (linear interpolation, Lagrange interpolation, spline interpolation, or the like) from the data of the frequency versus error in the memory 201, which has the effect of further increasing the accuracy.

In the above description, the timing of extracting the vector error of the transmission wave is not described.
(2) At the start of communication, (3) in the case of TDMA, every burst, or (4) at any time of transmission, the same effect can be obtained.

Although the above description has been made with respect to a transmitting / receiving apparatus having the same transmitting / receiving frequency, a transmitting / receiving apparatus having a different transmitting / receiving frequency may be used. An external frequency converter as shown in FIG. The same effect can be obtained by the above.

The above description has been made with respect to the receiver having the homodyne configuration. However, a transmitter having a heterodyne configuration using the quadrature mixer 38 may be used, and the same effects can be obtained.

In the above description, H / W of digital operation is not described. However, H / W by a logic circuit or processing based on S / W of a DSP or CPU may be used. Has the effect of

Embodiment 17 FIG. The seventeenth embodiment is different from the memory 2 for storing the vector error of the modulated wave of the transmitting and receiving apparatus of the fifteenth embodiment.
The address uses the temperature as the address 01. Less than,
A transmission / reception apparatus according to the seventeenth embodiment will be described with reference to the drawings. In FIG. 39, reference numeral 211 denotes a temperature sensor for detecting the internal temperature of the apparatus. Temperature sensor 211 outputs temperature data to memory 201. Here, the same or corresponding parts as those in Embodiments 1 and 15 in FIGS. 1 and 36 are denoted by the same reference numerals.

Next, the operation will be described. Although the temperature dependency of the error in the receiving apparatus has been described in the ninth embodiment, the same applies to the transmitting apparatus. The error stored in the memory 201 is caused by unbalance of the quadrature mixer 38 and the baseband amplifier 55, and these values are temperature-dependent. As shown in the table of FIG. 23 of the ninth embodiment, if the error with respect to the temperature detected by the temperature sensor 211 is stored in the memory 201 for each temperature, the error compensation amount can be changed according to the temperature. As a result, it is possible to suppress deterioration of the error detection / compensation due to the temperature, and it is possible to achieve high accuracy.

In the above description, the temperature vs. error is stored in the memory 201. Here, with respect to the temperature between addresses, the lower bits of the temperature data may be truncated or rounded off to match the address of the memory 201. Alternatively, it may be obtained by interpolation (linear interpolation, Lagrange interpolation, spline interpolation, or the like) from the data of temperature versus error in the memory 201, which has the effect of further increasing the accuracy.

In the above description, the timing of extracting the vector error of the transmission wave is not described.
(2) At the start of communication, (3) in the case of TDMA, every burst, or (4) at any time of transmission, the same effect can be obtained.

Although the above explanation was made with respect to a transmitting / receiving apparatus having the same transmitting / receiving frequency, a transmitting / receiving apparatus having a different transmitting / receiving frequency may be used. A similar effect can be obtained by providing an external frequency converter and extracting an error. Can be

The above description has been made with respect to the transmitting / receiving apparatus having the homodyne configuration. However, a transmitting apparatus having a heterodyne configuration using the quadrature mixer 38 may be used, and the same effects can be obtained.

In the above description, the H / W of digital operation is not described, but the H / W by a logic circuit or the processing based on S / W of a DSP or CPU may be used. Has the effect of

Embodiment 18 FIG. In the eighteenth embodiment, the completely calibrated high-accuracy receiving apparatus of the first or second embodiment is used as a base station, and the vector error of the modulated wave of the transmitting apparatus of the slave station is corrected. Hereinafter, the communication system of the eighteenth embodiment will be described with reference to the drawings. In FIG. 40, 220
Denotes a base station transmitting device, and 221 denotes a slave station receiving device. The receiving device provided in parallel with the base station transmitting device 220 and the transmitting device provided in parallel with the slave station receiving device 221 exemplify a homodyne configuration. Here, the same or corresponding parts as those in Embodiments 1 and 2 in FIGS. 1 and 7 are denoted by the same reference numerals.

Next, the operation will be described. It is assumed that the receiving apparatus of the base station has already completed the vector error compensation based on the input sine wave. The slave station transmits a vector-modulated transmission wave according to the modulation signal output of the modulation signal generation circuit 57.

The transmission wave from the slave station is detected by the quadrature mixer 6 of the receiving device of the base station, and the error is compensated. The code is reproduced in the demodulation operation circuit 12. Here, the arithmetic circuit 20
With 0, an error from the original coordinates of the transmission wave is obtained. For example, since the coordinates of 4 points for QPSK and 16 points for 16QAM are known, this error detection is easy. The transmission device 220 of the base station transmits the error data of the transmission wave to the slave station. This transmission wave is reproduced by the slave station receiver 221. The error data of the transmission wave of the slave station is stored in the memory 201. At the time of transmission from the slave station, the coordinates are corrected by the error compensation circuit 202 and transmission is performed.

As described above, according to the eighteenth embodiment, since the coordinates of the transmission wave of the slave station are corrected using the receiving device of the base station with high accuracy, high vector accuracy of the transmission wave can be obtained. There is an effect that BER deterioration due to a modulation error can be suppressed. Further, since error detection is performed by the base station, there is an effect that power consumption, cost, and size of the slave station can be reduced.

In the above description, the timing of extracting the vector error of the transmitted wave is not described.
(2) At the start of communication, (3) in the case of TDMA, every burst, or (4) at any time of transmission, the same effect can be obtained.

The above description has been made with respect to the receiver having the homodyne configuration. However, the transmitter having the heterodyne configuration using the quadrature mixer 38 may also have the same effect.

Although the above description does not describe H / W of digital operation, H / W by a logic circuit or processing based on S / W of a DSP or CPU may be used. Has the effect of

[0261]

As described above, according to the first aspect of the present invention, a receiving apparatus provided with a detector for detecting a received signal and outputting an I signal and a Q signal orthogonal to each other is used as the received signal. the test signal inputted, with determining the gain error is the error between the I and Q signals of the test signal, a calibration step of storing the error data of the gain error in the memory, received the receiving communication signals Analog signal
And reading out the error data from the memory , and compensating the I signal or the Q signal of the communication signal based on the error data. The error data is obtained based on the test wave. The accuracy of the data is improved, and the influence of the received signal on the rectangular coordinates IQ can be reduced. As a result, BER (Bit Error Rat
e) can be improved. Further, according to the invention of claim 2, to the receiving device provided with a detector which detects the received signal and outputs the I and Q signals are orthogonal to each other, enter the test signal as the received signal, the test together determine the phase error which is an error between the I and Q signals of the signal, a calibration step of storing the error data of the upper Symbol phase error memory, read out error data from the memory when receiving the communication signal And a compensation step of compensating the I signal or the Q signal of the communication signal based on the error data. Since the error data is obtained based on the test wave, the accuracy of the error data is improved and the The effect can be reduced. Thereby, BER (Bit Error
Rate) can be improved.

According to the third aspect of the present invention, the calibration step includes the steps of: inputting a test signal as the reception signal; and performing a calibration between the I signal and the Q signal of the test signal based on a predetermined value.
With determination of the error, a first calibration step of storing the error data of the error in the memory, reads the error data from said memory, first to compensate for the I signal or Q signal of the test signal based on the error data and second calibration step, with obtaining the error on the basis of the I and Q signals, the error data of the error is constituted by a third calibration step of updating the error data by storing in the memory, the error Since the data is obtained repeatedly, the accuracy of the error data is further improved. Further, according to the invention of claim 4, the calibration step
Further, errors occurring in the I signal and the Q signal of the test signal
Determine the DC offset error as the difference
Saving DC offset error data in memory
Thus, the DC offset can be compensated. Further, according to claim 5
According to the description, the calibration step is performed as the received signal.
A test signal is input, and based on a predetermined value, the I
Error in the signal and Q signal, or I signal and Q
Find the error between the signal and
A first calibration step of storing in a memory,
Read the error data from
Based on at least the I and Q signals of the test signal
And second calibration step of compensating for one, the second calibration
Occurs in the I and Q signals compensated by the step
Error between the I signal and the Q signal.
And save the error data in the above memory.
A third calibration step for updating the error data.
So that the error data is obtained repeatedly.
Therefore, the accuracy of the error data is further improved.

According to the invention of claim 6 , since the test signal input in the calibration step is a pilot signal included in an external communication signal, error detection can be performed at any time.

According to the seventh aspect of the present invention, the test signal input in the calibration step is a non-modulated signal transmitted from the outside prior to data, so that error detection can be performed more frequently. Can be.

According to the eighth aspect of the present invention, in the calibration step, the test signal is a sine wave, and the low frequency components of the I signal and the Q signal are extracted, so that the DC offset error Δi of the I signal is obtained. And the DC offset error Δq of the Q signal, and in the compensation step, the DC offset error Δi of the I signal and the DC offset error Δq of the Q signal are subtracted from the I signal and the Q signal of the communication signal, respectively. Since compensation is performed, DC offset can be compensated.

According to the ninth aspect of the present invention, a test signal is input as a reception signal to a reception apparatus provided with a detector for detecting a reception signal and outputting an I signal and a Q signal orthogonal to each other. A calibration step of obtaining errors occurring in the I signal and the Q signal of the test signal and storing the data of these errors in a memory; reading error data from the memory when a communication signal is received; A compensating step for compensating the I signal and the Q signal of the communication signal based on the communication signal.
The test signal is a sine wave, and the amplitude of one of the I signal and the Q signal with respect to the sine wave input is V1.
(T), when the other amplitude is V2 (t), the I signal and the Q signal are each squared, and then the low-frequency component is extracted to obtain the squared value of the amplitude (V1 (t)) 2,
(V2 (t)) 2, and further, a gain error ΔG is calculated by the following equation (a). ΔG = ｛(V2 (t)) 2 / (V1 (t)) 2｝ 0.5 (a) Then, the gain is compensated by multiplying the signal corresponding to the amplitude V1 (t) by the gain error ΔG or by dividing the signal corresponding to the amplitude V2 (t) by the gain error ΔG. Therefore, the gain error can be compensated.

According to the tenth aspect of the present invention, a test signal is input as a reception signal to a reception apparatus provided with a detector that detects a reception signal and outputs an I signal and a Q signal orthogonal to each other. A calibration step of obtaining errors occurring in the I signal and the Q signal of the test signal and storing the data of these errors in a memory; reading error data from the memory when a communication signal is received; A compensating step of compensating the I signal and the Q signal of the communication signal based on the input signal. In the calibrating step, the test signal is a sine wave, and an amplitude of one of the I signal and the Q signal with respect to the sine wave input is provided. To V1
(T), when the other amplitude is V2 (t), the low frequency component is extracted after squaring the I signal and the Q signal, thereby obtaining the square value of the amplitude (V1 (t)) ² ,
(V2 (t)) ² , and further, a gain error ΔG is calculated by the following equation (a). ΔG = ｛(V2 (t)) ² / (V1 (t)) ² ｝ ^0.5 (a) After multiplying the I signal and the Q signal, a low frequency component is extracted, and the extracted value is expressed as (V3 (t)) 2
Then, the phase error Δφ is obtained by the following equation (b), and Δφ = sin-1 ｛(V3 (t)) 2 / (ΔG ・ (V1 (t)) 2)｝ (b) In the above compensation step, Compensating the phase by the following equation (c): {V2 (t) + V1 (t) * sin (Δφ)} / cos (Δφ) (c) Therefore, the phase error can be compensated.

[0268] According to the invention of claim 11, a detector which detects the communication signal and outputs the I and Q signals are orthogonal to each other, the I signal output by the detector and
A- which converts each Q signal from analog to digital
A D converter, a memory in which error data of a gain error between the I signal and the Q signal generated in the detector determined based on a test signal are stored in advance, and reading the error data from the memory; and compensating means for compensating the I signal or the Q signal output from the a-D converter on the basis of the error data, since a demodulation circuit for demodulating the data on the basis of the I and Q signals in advance The error can be compensated by the stored error data, and the configuration is simplified. Claims
According to the twelfth aspect, a detector that detects a communication signal and outputs an I signal and a Q signal that are orthogonal to each other, and error data of a phase error between the I signal and the Q signal generated in the detector. A memory stored in advance, a compensator for reading the error data from the memory, and compensating the I signal or the Q signal based on the error data; and a compensated I signal and a Q signal output by the compensator. And a demodulation circuit for demodulating the data based on the data, the error can be compensated by the error data stored in advance, and the configuration is simplified.

According to the thirteenth aspect of the present invention, there is provided a temperature sensor for measuring a temperature inside the apparatus, a plurality of error data corresponding to a plurality of temperatures are stored in the memory, and the compensating means is provided. Since the error data corresponding to the temperature output from the temperature sensor is read out and the I signal or the Q signal is compensated for, the error can be appropriately compensated even if the error fluctuates due to the temperature.

According to the fourteenth aspect of the present invention, a local oscillation frequency detector for detecting a frequency of a local oscillation wave of the detector is provided, and a plurality of error data corresponding to a plurality of frequencies are stored in the memory. Is stored, and the compensating means reads error data corresponding to the frequency output from the local oscillation frequency detector to compensate for the I signal or the Q signal. Even in such cases, compensation can be made appropriately.

According to the fifteenth aspect of the present invention, the DC offset error Δi of the I signal and the DC offset error Δq of the Q signal are stored in the memory. An i-channel subtractor for subtracting an offset error Δi;
Since a q-channel subtractor for subtracting the offset error Δq is provided, DC offset can be compensated. Claims
According to the sixteenth aspect, the temperature sensor for measuring the temperature inside the device is provided.
Sensor, and the memory has multiple temperatures
Multiple error data corresponding to each are stored, and
Means for detecting an error corresponding to the temperature output by the temperature sensor;
The data is read and the I signal and the Q signal are
The error fluctuated with temperature because at least one was compensated.
Even in such cases, compensation can be made appropriately. Also, the invention of claim 17
According to the above, the frequency of the local oscillation wave of the detector is detected.
A local oscillation frequency detector;
In addition, multiple error data corresponding to each of multiple frequencies
Is stored, and the compensation means detects the local oscillation frequency.
Error data corresponding to the frequency output by the
At least one of the I signal and the Q signal is compensated.
Therefore, even if the error varies with frequency,
Can compensate.

[0272] According to the invention of claim 18, a detector which detects the communication signal received and outputs the I and Q signals are orthogonal to each other, output by the detector I
Convert signal and Q signal from analog to digital respectively
And a memory in which error data generated in the detector obtained based on the test signal is stored in advance, and the error data is read out from the memory, and the A / D converter reads the error data based on the error data. Output
And compensating means for compensating for the I signal and the Q signal,
A demodulation circuit for demodulating data based on the compensated I signal and Q signal output by the compensation means, wherein a gain error ΔG between the I signal and the Q signal is stored in the memory; Since the means is provided with a multiplier for multiplying the I signal or the Q signal by a coefficient corresponding to the gain error ΔG, the gain error can be compensated.

According to the nineteenth aspect of the present invention, there is provided a detector for detecting a received communication signal and outputting an I signal and a Q signal orthogonal to each other, and a memory in which error data generated in the detector is stored in advance. Reading out the error data from the memory, compensating the I signal and the Q signal based on the error data, and demodulating the data based on the compensated I signal and the Q signal output by the compensating means. A demodulation circuit, and the memory
The phase error .DELTA..phi. Between the I signal and the Q signal is preserved, and one of the amplitudes of the I signal and the Q signal is V1 (t) and the other is V2 (t).
基 づ き V2 based on the phase error Δφ
Since the calculator for calculating (t) + V1 (t) * sin (Δφ)｝ / cos (Δφ) is provided, the phase error can be compensated.

According to the twentieth aspect , when a test wave is input to the detector instead of the communication signal, the error data is converted based on the I signal and the Q signal from the detector. Since the error detecting circuit for obtaining the error and storing it in the memory is provided, the error can be detected even after the receiving device is shipped.

According to the twenty-first aspect of the present invention, when the error detection circuit obtains error data, a test signal generator that generates a sine wave and supplies the sine wave to the detector is provided. It can be done at any time.

According to the twenty-second aspect of the present invention, the low frequency component of the I signal is extracted by the
Since an i-channel low-pass filter that outputs an offset error Δi and a q-channel low-pass filter that extracts a low-frequency component of the Q signal and outputs a DC offset error Δq, a DC offset can be obtained as needed. Can be.

According to the twenty- third aspect of the present invention, a detector for detecting a received communication signal and outputting an I signal and a Q signal orthogonal to each other, and a memory in which error data generated in the detector are stored in advance. Reading out the error data from the memory, compensating the I signal and the Q signal based on the error data, and demodulating the data based on the compensated I signal and the Q signal output by the compensating means. A demodulation circuit, and an error detection circuit that, when a test wave is input to the detector as the communication signal, obtains the error data based on the I signal and the Q signal from the detector and stores the error data in the memory. An i-channel squaring circuit for squaring the I signal, a q-channel squaring circuit for squaring the Q signal, An i-channel low-pass filter for extracting a low-frequency component of the output signal of the multiplication operation circuit; a q-channel low-pass filter for extracting a low-frequency component of the output signal of the q-channel square operation circuit; Since there is provided a gain error calculation circuit for calculating the gain error ΔG based on the output of the pass filter and the output of the q-channel low-pass filter, the gain error can be obtained at any time.

According to the invention of claim 24, a detector for detecting a received communication signal and outputting an I signal and a Q signal orthogonal to each other, and a memory in which error data generated in the detector are stored in advance. Reading out the error data from the memory, compensating the I signal and the Q signal based on the error data, and demodulating the data based on the compensated I signal and the Q signal output by the compensating means. A demodulation circuit, and an error detection circuit that, when a test wave is input to the detector as the communication signal, obtains the error data based on the I signal and the Q signal from the detector and stores the error data in the memory. An i-channel squaring circuit for squaring the I signal, a q-channel squaring circuit for squaring the Q signal, An i-channel low-pass filter for extracting a low-frequency component of the output signal of the multiplication operation circuit; a q-channel low-pass filter for extracting a low-frequency component of the output signal of the q-channel square operation circuit; A gain error calculation circuit for calculating a gain error ΔG based on an output of the pass filter and an output of the q-channel low-pass filter, a multiplication circuit for multiplying the I signal and the Q signal, and an output signal of the multiplication circuit A low-pass filter for extracting the low-frequency component of, and a phase error calculation circuit for calculating a phase error Δφ based on the output of the low-pass filter and the output of the gain error calculation circuit. Can be requested at any time.

According to the twenty-fifth aspect of the present invention, since the low-pass filter control means for changing the frequency characteristic of the low-pass filter in response to the change of the communication rate is provided, the multi-rate system is supported. it can.

According to the twenty-sixth aspect of the present invention, a detector for detecting a communication signal and outputting an I signal and a Q signal orthogonal to each other, and an i-channel high-pass filter for extracting a high frequency component of the I signal A q-channel high-pass filter for extracting a high-frequency component of the Q signal; a demodulation circuit for demodulating data based on an output signal of the i-channel high-pass filter and an output signal of the q-channel high-pass filter; High-pass filter control means for controlling the i-channel high-pass filter and the q-channel high-pass filter so as to increase the cutoff frequency when the DC offset included in the I signal or the Q signal varies. , The influence of the DC offset fluctuation can be reduced, and the BER improves.

According to the twenty-seventh aspect , the above-mentioned i
The channel high-pass filter and the q-channel high-pass filter are each configured by a switched capacitor filter whose cutoff frequency changes in accordance with the frequency of a supplied clock, and the high-pass filter control means includes:
A reference signal generator for generating a reference signal; a counter for dividing the reference signal to generate the clock and supplying the clock to the i-channel high-pass filter and the q-channel high-pass filter, respectively; Is provided with a frequency division number control unit for lowering the frequency division number of the counter when the value fluctuates, so that the filter can be controlled with a simple configuration.

According to the twenty-eighth aspect of the present invention, there is provided a local oscillator for generating a local oscillation wave, and a detector for detecting a communication signal based on the local oscillation wave and outputting an I signal and a Q signal orthogonal to each other. An i-channel high-pass filter for extracting the high-frequency component of the I signal, a q-channel high-pass filter for extracting the high-frequency component of the Q signal, an output signal of the i-channel high-pass filter, and the q-channel height. A demodulation circuit that demodulates data based on an output signal of the band-pass filter; and, when an unmodulated signal is received, a difference between the frequency of the local oscillation wave and the frequency of the unmodulated signal is i.
A control circuit for controlling the local oscillator so as to be higher than both the cutoff frequency of the channel high-pass filter and the cutoff frequency of the q-channel high-pass filter, so that the level of the unmodulated signal is stable; BER is improved.

According to the twenty- ninth aspect of the present invention, there is provided a local oscillator for generating a local oscillation wave, and a detector for detecting a communication signal based on the local oscillation wave and outputting an I signal and a Q signal orthogonal to each other. , An i-channel high-pass filter for extracting the high-frequency component of the I signal, a q-channel high-pass filter for extracting the high-frequency component of the Q signal, and an output of the i-channel high-pass filter. An i-channel correction filter having an inverse characteristic to the pass characteristic of the above, and an input of the output of the q-channel high-pass filter, and a q-channel correction filter having an inverse characteristic to the pass characteristic of the filter; A demodulation circuit that demodulates data based on the output signal of the filter and the output signal of the q-channel correction filter. Is removed, BER is improved.

[0284] According to the thirtieth aspect of the present invention, there is provided a local oscillator for generating a local oscillation wave, and a detector for detecting a communication signal based on the local oscillation wave and outputting an I signal and a Q signal orthogonal to each other. An i-channel delay means for delaying the I signal, an i-channel low-pass filter for extracting a low-frequency component of the I signal, and an output of the i-channel delay means and an output of the i-channel low-pass filter. An i-channel subtractor for obtaining a difference, a q-channel delay unit for delaying the Q signal, a q-channel low-pass filter for extracting a low-frequency component of the Q signal, an output of the q-channel delay unit and the q-channel A q-channel subtractor for obtaining a difference from the output of the low-pass filter; and a demodulator for demodulating data based on the output signal of the i-channel subtractor and the output signal of the q-channel subtractor. Since a circuit, the error is reduced, BER can be improved.

According to the thirty-first aspect of the present invention, there is provided an antenna for transmitting and receiving, a detector for detecting a signal received from the antenna and outputting an I signal and a Q signal orthogonal to each other, A reception error memory in which the generated reception error data is stored in advance, the reception error data is read from the reception error memory, and the compensation means for compensating the I signal and the Q signal based on the reception error data; and A receiving unit including a demodulation circuit for demodulating data based on the compensated I signal and Q signal to be output, a transmission error memory for storing transmission error data, and an I signal and Q orthogonal to each other by modulating transmission data
A modulation signal generation circuit for outputting a signal, an error compensation circuit for reading the transmission error data from the transmission error memory, and compensating an I signal and a Q signal output from the modulation signal generation circuit based on the transmission error data; A modulator configured to generate a transmission signal based on the compensated I signal and Q signal output by the compensation circuit, a transmission unit including an amplifier that amplifies an output of the modulator and supplies the output to the antenna; A transmission error calculation circuit that determines the transmission error data by comparing the coordinates of the data output by the demodulation circuit with the coordinates of the transmitted transmission data, and stores the transmission error data in the transmission error memory of the transmission unit. When calculating the transmission error data, the transmission unit generates the transmission signal from the input transmission data and receives the transmission signal from the amplifier. And the receiving unit outputs to the transmission error calculation circuit compensated and demodulated the supplied transmission signal based on the reception error data stored in advance, and outputs the transmission error. The arithmetic circuit obtains the transmission error data by comparing the coordinates of the data output from the demodulation circuit with the coordinates of the transmission data. Therefore, the error of the transmission unit can be compensated and the BER is improved. Things.

According to the invention of claim 32 , a frequency converter for converting the frequency of a transmission signal supplied from the amplifier of the transmission section to the detector of the reception section to the frequency of the reception section is provided. With the provision, even when the transmission frequency and the reception frequency are different, the error of the transmission unit can be compensated.

[0287] According to the invention of claim 33, provided with a temperature sensor for measuring the temperature inside the apparatus, to the transmission error memory, a plurality of transmission error data corresponding to a plurality of temperatures are stored, the The error compensation circuit of the transmission unit reads out transmission error data corresponding to the temperature output from the temperature sensor and compensates for the I signal and the Q signal. Can be compensated.

According to the invention of claim 34 , a local oscillation frequency detector for detecting a frequency of a local oscillation wave of the modulator of the transmission section is provided, and a plurality of local oscillation frequencies are stored in the transmission error memory. A plurality of transmission error data corresponding to each are stored, and the error compensation circuit reads transmission error data corresponding to the frequency output by the local oscillation frequency detector and compensates the I signal and the Q signal. Even when the error fluctuates depending on the frequency, the transmission unit can be appropriately compensated.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a receiving device according to a first embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of an error detection circuit of the receiving device according to the first embodiment of the present invention.

FIG. 3 is a detailed configuration diagram of an error compensation circuit of the receiving device according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing an error extraction procedure and an error compensation procedure according to the first embodiment of the present invention.

FIG. 5 is a flowchart illustrating another error extraction procedure and an error compensation procedure according to the first embodiment of the present invention.

FIG. 6 is a configuration diagram of a receiving device according to a second embodiment of the present invention.

FIG. 7 is a detailed configuration diagram of an error detection circuit of the receiving device according to the second embodiment of the present invention.

FIG. 8 is a detailed configuration diagram of an error compensation circuit of the receiving device according to the second embodiment of the present invention.

FIG. 9 is a configuration diagram of a receiving device according to a third embodiment of the present invention.

FIG. 10 is a flowchart illustrating an error extraction procedure and an error compensation procedure according to a third embodiment of the present invention.

FIG. 11 is a configuration diagram of a receiving device according to a fourth embodiment of the present invention.

FIG. 12 is a diagram illustrating a spectrum of a received wave according to a fourth embodiment of the present invention.

FIG. 13 is a flowchart illustrating an error extraction procedure and an error compensation procedure according to a fourth embodiment of the present invention.

FIG. 14 is a configuration diagram of a receiving device according to a fifth embodiment of the present invention.

FIG. 15 is a waveform diagram of a received wave according to the fifth embodiment of the present invention.

FIG. 16 is a flowchart showing an error extraction procedure and an error compensation procedure according to Embodiment 5 of the present invention.

FIG. 17 is a configuration diagram of a receiving device according to a sixth embodiment of the present invention.

FIG. 18 is another configuration diagram of the receiving device according to the sixth embodiment of the present invention.

FIG. 19 is a detailed configuration diagram of a low-pass filter calculation unit according to Embodiment 7 of the present invention.

FIG. 20 is a configuration diagram of a receiving apparatus according to an eighth embodiment of the present invention.

FIG. 21 is a flowchart illustrating an error extraction procedure and an error compensation procedure according to Embodiment 8 of the present invention.

FIG. 22 is a configuration diagram of a receiving device according to a ninth embodiment of the present invention.

FIG. 23 is a diagram showing error data stored in a memory according to Embodiment 9 of the present invention.

FIG. 24 is a configuration diagram of a receiving device according to a tenth embodiment of the present invention.

FIG. 25 is a diagram showing error data stored in a memory according to Embodiment 10 of the present invention.

FIG. 26 is a configuration diagram of a receiving device according to an eleventh embodiment of the present invention.

FIG. 27 is a configuration diagram and a characteristic diagram of a switched capacitor filter according to Embodiment 11 of the present invention.

FIG. 28 is a waveform chart for explaining the operation of the receiver according to the eleventh embodiment of the present invention.

FIG. 29 is a configuration diagram of a receiver according to Embodiment 12 of the present invention.

FIG. 30 is another configuration diagram of the receiving device according to the twelfth embodiment of the present invention.

FIG. 31 is a configuration diagram of a receiving device according to Embodiment 13 of the present invention.

FIG. 32 is a waveform diagram of an impulse response of a filter for explaining the operation of the receiving apparatus according to Embodiment 13 of the present invention.

FIG. 33 is a configuration diagram of a receiver according to Embodiment 14 of the present invention.

FIG. 34 is another configuration diagram of the receiving device of Embodiment 14 of the present invention.

FIG. 35 is another configuration diagram of the receiving device of Embodiment 14 of the present invention.

FIG. 36 is a configuration diagram of a transmission / reception apparatus according to Embodiment 15 of the present invention.

FIG. 37 is another configuration diagram of the transmission / reception device according to Embodiment 15 of the present invention.

FIG. 38 is a configuration diagram of a transmission / reception apparatus according to Embodiment 16 of the present invention.

FIG. 39 is a configuration diagram of a transmission / reception apparatus according to Embodiment 17 of the present invention.

FIG. 40 is a configuration diagram of a communication system according to an eighteenth embodiment of the present invention.

FIG. 41 is a configuration diagram of a conventional receiving device.

FIG. 42 is an explanatory diagram of an error factor in a conventional receiving device.

FIG. 43 is a diagram illustrating a deformation of a spatial diagram due to a vector error according to the conventional receiving apparatus.

FIG. 44 is an explanatory diagram of BER degradation due to vector errors in a conventional receiving apparatus.

FIG. 45 is a configuration diagram of a conventional heterodyne receiver.

FIG. 46 is a configuration diagram of a conventional receiving device provided with a high-pass filter.

FIG. 47 is another configuration diagram of a conventional receiving device provided with a high-pass filter.

FIG. 48 is an explanatory diagram of an impulse response of a high-pass filter.

FIG. 49 is an explanatory diagram of distortion of a transmission code due to an impulse response of a high-pass filter.

FIG. 50 is an explanatory diagram of attenuation of an unmodulated wave by a high-pass filter.

FIG. 51 is an explanatory diagram of distortion of a transmission code due to an impulse response of a high-pass filter when a DC offset changes.

FIG. 52 is a configuration diagram of a conventional receiving device provided with an error compensation circuit.

FIG. 53 is a configuration diagram of a conventional transmission device.

FIG. 54 is another configuration diagram of the conventional transmission device.

[Explanation of symbols]

1 Low noise amplifier (LNA), 2 Bandpass filter (BP
F), 3 mixers (MIX), 40 degree distributor, 590 degree phase shifter, 6 quadrature mixer, 8 local oscillator (LO), 9 low-pass filter (LPF), 10 baseband amplifier (AMP)
, 11 AD converter, 12 demodulation operation circuit, 13 mixer (MI
X), 14 amplifier (AMP), 15 bandpass filter (BPF)
, 31 High Power Amplifier (HPA), 32 Transmit Mixer, 33 Upconverter, 34 Transmit Mixer, 360 ° Distributor, 37
90-degree phase shifter, 38 quadrature mixer, 54 low-pass filter (L
PF), 55 Baseband Amplifier (AMP), 56 DA Converter, 57 Modulation Signal Generator, 58 Down Converter, 60
High-pass filter (HPF), 101 error detection / compensation circuit, 102 memory, 103 error detection means, 104 error compensation means, 105 gain error detection circuit, 106 phase error detection circuit, 107 DC offset detection circuit, 108 subtraction circuit, 11
0 square operation circuit, 111 low-pass filter operation means,
112 arithmetic circuit 1, 113 multiplication circuit, 114 low-pass filter arithmetic means, 115 arithmetic circuit 2, 116 low-pass filter arithmetic means, 120 DC offset compensation circuit, 121
Gain error compensation circuit, 122 Phase error compensation circuit, 130
Error detection / compensation circuit, 133 receiving device, 134 transmitting device, 135 base station transmitting device, 136 base station transmitting device,
137 Calibration device, 138 receiver, 140 FIR filter, 141 tap coefficient rewriting means, 151 temperature sensor, 152 data conversion means, 153 high-pass filter using switched capacitor, 154 clock, 155 counter, 156 switch, 160 control circuit, 161 control circuit, 162 reference oscillator, 163 digital filter,
170 low-pass filter, 171 delay line, 172 subtractor, 173 adder, 200 arithmetic circuit, 201 memory, 20
2 Error compensation circuit, 203 switch, 204 band pass filter, 205 local oscillator (LO), 206 mixer (MIX) 207
Frequency converter, 210 data converter, 211 temperature sensor, 220 base station transmitter, 221 slave station receiver.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Tsutomu Nagatsuka 5-1-1, Ofuna, Kamakura City Mitsubishi Electric Corporation Electronic Systems Laboratory (56) References JP-A-7-177188 (JP, A) JP-A-6-268703 (JP, A) JP-A-1-135161 (JP, A) JP-A-5-122263 (JP, A) JP-A-4-271550 (JP, A) (58) Fields investigated (Int) .Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (34)

(57) [Claims] 1. A test signal is input as a reception signal to a receiving apparatus provided with a detector that detects a reception signal and outputs an I signal and a Q signal orthogonal to each other, and outputs an I signal and a Q signal of the test signal. together determine the gain error is the error between the signals, digital and calibration step of storing the error data of the upper Symbol gain error in the memory, receiving the communication signal the received signal from the analog
Is converted into, it reads the error data from the memory, compensation method of a receiving apparatus and a compensation step for compensating the I signal or Q No. signal of the communication signal based on the error data. 2. A test signal is input as a received signal to a receiving apparatus provided with a detector that detects a received signal and outputs an I signal and a Q signal orthogonal to each other, and outputs an I signal and a Q signal of the test signal. together determine the phase error which is an error between the signals, a calibration step of storing the error data of the upper Symbol phase error memory, reads the error data from said memory when receiving the communication signal, to the error data A compensating step of compensating the I signal or the Q signal of the communication signal based on the communication signal. The method according to claim 3 wherein said calibration step, inputs a test signal as said received signal, with obtaining an error between the I and Q signals of the test signal based on a predetermined value, the memory error data of the error a first calibration step of storing the reads the error data from said memory, a second calibration step of compensating the I signal or Q signal of the test signal based on the error data, to the I and Q signals with obtaining the error based, according to claim 1 or claim 2, characterized by being configured and a third calibration step of updating the error data by storing error data for the error in the memory
A method for compensating a receiving device according to any of the preceding claims. 4. The method according to claim 1 , further comprising the step of :
DC offset as an error in the I and Q signals
With finding a Tsu door error, of the DC offset error
The error data is stored in a memory.
A method for compensating a receiving device according to claim 1 or claim 2. 5. The method according to claim 5 , wherein a test signal is input as the reception signal , and the calibration step is performed based on a predetermined value.
There are errors in the I and Q signals of the test signal
Or, when the error between the I signal and the Q signal is determined,
Next, the first calibration mode for storing this error data in the memory
Read the error data from the memory
Based on the difference data, the sum of the I signal and the Q signal
A second calibration step for compensating at least one, and the I signal and the signal compensated by the second calibration step.
And the Q signal, or the I and Q signals
And calculate the error data above.
Update the above error data by saving to memory
A third calibration step.
The method for compensating a receiving device according to claim 4. The method according to claim 6 wherein the test signal to be input at the calibration step, the compensation method of a receiving apparatus according to any one of claims 5 claims 1, characterized in that the pilot signal from the outside. The method according to claim 7 wherein the test signal to be input at the calibration step, from the outside, claims 1, characterized in that the non-modulated signal transmitted prior to the data reception apparatus according to claim 5 Compensation method. 8. The DC offset error Δi of the I signal and the DC offset error Δq of the Q signal by extracting the test signal into a sine wave and extracting low frequency components of the I signal and the Q signal in the calibration step. And determining the DC offset error Δi of the I signal and the DC offset error Δq of the Q signal from the I signal and the Q signal of the communication signal to compensate for the offset. A method for compensating a receiving device according to any one of claims 1 to 7 . 9. A test signal is input as a received signal to a receiving apparatus including a detector that detects a received signal and outputs an I signal and a Q signal orthogonal to each other, and outputs an I signal and a Q signal of the test signal. Find the error that occurs in the signal,
A calibration step of storing these error data in a memory; and a compensating step of reading the error data from the memory when a communication signal is received, and compensating the I signal and the Q signal of the communication signal based on the error data. In the calibration step, when the test signal is a sine wave, one of the I signal and the Q signal with respect to the sine wave input is V1 (t), and the other is V2 (t). , And the low frequency components are extracted after squaring the I signal and the Q signal, respectively, to obtain the square values (V1 (t)) ² and (V2 (t)) ² of the amplitude.
A gain error ΔG is obtained by the following equation (a), and ΔG = {(V2 (t)) ² / (V1 (t)) ² } ^0.5 (a) In the above-mentioned compensation step, a signal corresponding to the above-mentioned amplitude V1 (t) A gain corresponding to the amplitude V2 (t) by dividing the signal corresponding to the amplitude V2 (t) by the gain error .DELTA.G. 10. A method for detecting a received signal and detecting I
A test signal is input as the received signal to a receiving apparatus including a detector that outputs a signal and a Q signal, and an error generated in the I signal and the Q signal of the test signal is obtained.
A calibration step of storing these error data in a memory; and a compensating step of reading the error data from the memory when a communication signal is received, and compensating the I signal and the Q signal of the communication signal based on the error data. In the calibration step, when the test signal is a sine wave, one of the I signal and the Q signal with respect to the sine wave input is V1 (t), and the other is V2 (t). , And the low frequency components are extracted after squaring the I signal and the Q signal, respectively, to obtain the square values (V1 (t)) ² and (V2 (t)) ² of the amplitude.
The gain error ΔG is obtained by the following equation (a), and ΔG = {(V2 (t)) ² / (V1 (t)) ² } ^0.5 (a) Further, after multiplying the I signal and the Q signal, A frequency component is extracted, and the extracted value is expressed as (V3 (t)) ²
Then, the phase error Δφ is obtained by the following equation (b), and Δφ = sin ⁻¹ {(V3 (t)) ² / (ΔG · (V1 (t)) ² )} (b) In the above compensation step, A method for compensating a receiving device, wherein {V2 (t) + V1 (t) * sin (Δφ)} / cos (Δφ) (c) compensates the phase by the following equation (c). 11. A detector for detecting a received communication signal to output an I signal and a Q signal orthogonal to each other, and converting the I signal and the Q signal output by the detector to
An A / D converter for converting an analog signal to a digital signal, and a memory in which error data of a gain error between the I signal and the Q signal generated in the detector obtained based on a test signal are stored in advance. , it reads the error data from said memory, and compensating means for compensating the I signal or the Q No. signal output from the a-D converter on the basis of the error data, after compensation the compensation means outputs I A demodulation circuit for demodulating data based on the signal and the Q signal. 12. A detector for detecting a received communication signal to output an I signal and a Q signal orthogonal to each other, and an error data of a phase error between the I signal and the Q signal generated in the detector. Pre-stored memory,
Above in conjunction with reading the error data from the memory, and compensating means for auxiliary <br/> amortization the I signal or the Q No. signal based on said error data, after compensation the compensation means outputs I
A demodulation circuit for demodulating data based on the signal and the Q signal. 13. A temperature sensor for measuring a temperature inside the apparatus, a plurality of error data corresponding to a plurality of temperatures are stored in the memory, and the compensating means detects the temperature output from the temperature sensor. 13. The receiving apparatus according to claim 11, wherein the corresponding error data is read to compensate for the I signal or the Q signal. 14. A local oscillation frequency detector for detecting a frequency of a local oscillation wave of the detector, a plurality of error data corresponding to a plurality of frequencies are stored in the memory, and the compensating means includes: 13. The receiving device according to claim 11, wherein error data corresponding to a frequency output by the local oscillation frequency detector is read to compensate for the I signal or the Q signal. 15. The memory according to claim 15, wherein the DC offset error Δi of the I signal and the DC offset error Δ of the Q signal are stored in the memory.
q is stored, and the compensating means includes an i-channel subtractor for subtracting the DC offset error Δi from the I signal, and a q-channel subtractor for subtracting the DC offset error Δq from the Q signal. Claim 11 or Claim as a feature
13. The receiving device according to 12 . 16. A temperature sensor for measuring a temperature inside the device.
And the memory has a plurality of temperatures.
Are stored and a plurality of error data corresponding to
Is the error data corresponding to the temperature output by the temperature sensor.
And read out the I and Q signals
16. The receiving device according to claim 15, wherein the other is compensated.
Communication device. 17. The frequency of the local oscillation wave of the detector is detected.
And a local oscillation frequency detector
Memory has multiple error data corresponding to each of multiple frequencies.
The local oscillation frequency.
Reads error data corresponding to the frequency output by the detector
To supplement at least one of the I signal and the Q signal.
The receiving device according to claim 15, wherein compensation is made. 18. A detector for detecting a received communication signal and outputting an I signal and a Q signal orthogonal to each other, and the detector
The I and Q signals output by the
A / D converter for converting log to digital, and test signal
Error data generated in the detector obtained based on
The error data is read, and the I signal and the Q output from the A / D converter based on the error data are read out.
A compensating means for compensating the signal; and a demodulation circuit for demodulating data based on the compensated I signal and the Q signal output by the compensating means, wherein the memory has a gain between the I signal and the Q signal. error .DELTA.G is stored, to the compensation means, to the I signal or the Q signal, the receiving apparatus characterized by comprising a multiplier for multiplying the coefficient corresponding to the gain error .DELTA.G. 19. A detector for detecting a received communication signal to output an I signal and a Q signal orthogonal to each other, a memory in which error data generated in the detector is stored in advance, and reading error data from the memory. And a compensating means for compensating the I signal and the Q signal based on the error data; and a demodulating circuit for demodulating data based on the compensated I signal and the Q signal output from the compensating means. , The phase error Δφ between the I signal and the Q signal is stored, and the compensating means sets one of the I signal and the Q signal to V1 (t) and the other to V2 (t). ), The equation {V2 (t) + V
1 A receiving device comprising a computing unit that computes (t) * sin (Δφ)｝ / cos (Δφ). 20. An error detection method for obtaining error data based on an I signal and a Q signal from the detector when a test wave is input to the detector instead of the communication signal, and storing the error data in the memory. claims, characterized in that it comprises a circuit
11 to the receiving apparatus according to claim 14. 21. The receiving apparatus according to claim 20 , further comprising a test signal generator that generates a sine wave and supplies the sine wave to the detector when the error detection circuit obtains error data. 22. An i-channel low-pass filter for extracting a low-frequency component of the I signal and outputting a DC offset error Δi to the error detection circuit, and a DC offset for extracting a low-frequency component of the Q signal. claims, characterized in that a q-channel low-pass filter for outputting the error Δq
Item 21. The receiving device according to item 20 . 23. A detector for detecting a received communication signal to output an I signal and a Q signal orthogonal to each other, a memory in which error data generated in the detector is stored in advance, and reading error data from the memory. A compensating means for compensating the I signal and the Q signal based on the error data; a demodulating circuit for demodulating data based on the compensated I signal and the Q signal output by the compensating means; An error detection circuit that obtains the error data based on the I signal and the Q signal from the detector and stores the error data in the memory when a test wave is input as a communication signal; An i-channel squaring circuit for squaring the signal, a q-channel squaring circuit for squaring the Q signal, and a low frequency of the output signal of the i-channel squaring circuit. And i-channel low-pass filter for extracting a component,
A gain error ΔG is determined based on a q-channel low-pass filter that extracts a low-frequency component of an output signal of the q-channel square arithmetic circuit, an output of the i-channel low-pass filter, and an output of the q-channel low-pass filter. A receiving device comprising: a gain error calculating circuit for calculating. 24. A detector for detecting a received communication signal to output an I signal and a Q signal orthogonal to each other, a memory in which error data generated in the detector is stored in advance, and reading error data from the memory. A compensating means for compensating the I signal and the Q signal based on the error data; a demodulating circuit for demodulating data based on the compensated I signal and the Q signal output by the compensating means; An error detection circuit that obtains the error data based on the I signal and the Q signal from the detector and stores the error data in the memory when a test wave is input as a communication signal; An i-channel squaring circuit for squaring the signal, a q-channel squaring circuit for squaring the Q signal, and a low frequency of the output signal of the i-channel squaring circuit. And i-channel low-pass filter for extracting a component,
A gain error ΔG is determined based on a q-channel low-pass filter that extracts a low-frequency component of an output signal of the q-channel square arithmetic circuit, an output of the i-channel low-pass filter, and an output of the q-channel low-pass filter. A gain error calculation circuit for calculating; a multiplication circuit for multiplying the I signal and the Q signal; a low-pass filter for extracting a low-frequency component of an output signal of the multiplication circuit; an output of the low-pass filter; A receiving apparatus comprising: a phase error calculating circuit that calculates a phase error Δφ based on an output of the gain error calculating circuit. 25. the preceding claims 22, characterized in that in correspondence with change of the communication rate with a low-pass filter control means for changing the frequency characteristic of the low pass filter
The receiving device according to claim 24 . 26. A detector for detecting a received communication signal to output an I signal and a Q signal orthogonal to each other, an i-channel high-pass filter for extracting a high frequency component of the I signal, and a high frequency filter for the Q signal. A q-channel high-pass filter for extracting components, a demodulation circuit for demodulating data based on an output signal of the i-channel high-pass filter and an output signal of the q-channel high-pass filter, and the I signal or the Q signal And a high-pass filter control means for controlling the i-channel high-pass filter and the q-channel high-pass filter so as to increase the cutoff frequency when the DC offset included in the fluctuates. 27. The i-channel high-pass filter and the q-channel high-pass filter each include a switched capacitor filter whose cut-off frequency changes according to a frequency of a supplied clock, and wherein the high-pass filter control is performed. Means, a reference signal generator for generating a reference signal, a counter for dividing the reference signal to generate the clock, and supplying the clock to the i-channel high-pass filter and the q-channel high-pass filter, respectively; When the DC offset fluctuates, a frequency division number control unit that lowers the frequency division number of the counter and raises the cutoff frequency of the i-channel high-pass filter and the q-channel high-pass filter is provided. Claims characterized
27. The receiving device according to 26 . 28. A local oscillator for generating a local oscillation wave,
A detector for detecting a communication signal received based on the local oscillation wave and outputting an I signal and a Q signal orthogonal to each other, an i-channel high-pass filter for extracting a high frequency component of the I signal, A q-channel high-pass filter for extracting high-frequency components; a demodulation circuit for demodulating data based on an output signal of the i-channel high-pass filter and an output signal of the q-channel high-pass filter; When the difference between the frequency of the local oscillation wave and the frequency of the unmodulated signal is larger than any of the cutoff frequency of the i-channel high-pass filter and the cutoff frequency of the q-channel high-pass filter. A control circuit for controlling a local oscillator. 29. A local oscillator for generating a local oscillation wave,
A detector for detecting a communication signal received based on the local oscillation wave and outputting an I signal and a Q signal orthogonal to each other, an i-channel high-pass filter for extracting a high frequency component of the I signal, A q-channel high-pass filter for extracting a high-frequency component, an i-channel correction filter having an input that is the output of the i-channel high-pass filter, and having an inverse characteristic to the pass characteristic of the filter, and a q-channel high-pass filter , And a q-channel correction filter having an inverse characteristic to the pass characteristic of the filter,
A receiving device comprising: a demodulation circuit that demodulates data based on the output signal of the i-channel correction filter and the output signal of the q-channel correction filter. 30. A local oscillator for generating a local oscillation wave,
A detector for detecting a communication signal received based on the local oscillation wave and outputting an I signal and a Q signal orthogonal to each other, an i-channel delay means for delaying the I signal, and extracting a low frequency component of the I signal An i-channel low-pass filter, an i-channel subtractor for calculating a difference between an output of the i-channel delay unit and an output of the i-channel low-pass filter, a q-channel delay unit for delaying the Q signal, A q-channel low-pass filter for extracting a low-frequency component of the Q signal; a q-channel subtractor for obtaining a difference between an output of the q-channel delay means and an output of the q-channel low-pass filter; And a demodulation circuit for demodulating data based on the output signal of the q-channel subtractor. 31. A transmitting and receiving antenna, a detector for detecting a reception signal from the antenna and outputting an I signal and a Q signal orthogonal to each other, and a reception device in which reception error data generated in the detector is stored in advance. Reading the reception error data from the error memory and the reception error memory, and based on the reception error data,
Compensating means for compensating the signal and the Q signal, a receiving unit including a demodulation circuit for demodulating data based on the compensated I signal and Q signal output from the compensating means, and a transmission error for storing transmission error data A memory, a modulation signal generation circuit for modulating transmission data to output I and Q signals orthogonal to each other, reading the transmission error data from the transmission error memory, and outputting the modulation signal generation circuit based on the transmission error data An error compensating circuit for compensating the I signal and the Q signal, a modulator for generating a transmission signal based on the compensated I signal and the Q signal output from the error compensating circuit, and an amplifier for amplifying the output of the modulator. A transmitting unit having an amplifier for supplying to an antenna; and comparing coordinates of data output by the demodulation circuit of the receiving unit with coordinates of the transmitted transmission data. A transmission error calculation circuit for obtaining the transmission error data, and storing the transmission error data in the transmission error memory of the transmission unit. A signal is generated, and the transmission signal is supplied from the amplifier to the detector of the reception unit. The reception unit compensates and demodulates the supplied transmission signal based on reception error data stored in advance. To the transmission error calculation circuit, wherein the transmission error calculation circuit obtains the transmission error data by comparing the coordinates of the data output from the demodulation circuit with the coordinates of the transmission data. apparatus. 32. A claims, characterized in that the frequency of the transmission signal supplied from the amplifier of the transmitting unit in the detector of the receiver, with a frequency converter for converting the frequency of the receiving section 31. The transmitting / receiving device according to item 31, 33. A temperature sensor for measuring a temperature inside the device, a plurality of transmission error data corresponding to each of a plurality of temperatures are stored in the transmission error memory,
Claims the error compensation circuit of the transmitting unit reads out the transmission error data corresponding to the temperature which the temperature sensor outputs and for compensating for the I signal and the Q signal
Item 32. The transmitting / receiving device according to Item 31 . 34. A local oscillation frequency detector for detecting a frequency of a local oscillation wave of the modulator of the transmission section, and a plurality of transmission error data respectively corresponding to a plurality of local oscillation frequencies are stored in the transmission error memory. Is stored, and the error compensation circuit reads out transmission error data corresponding to the frequency output from the local oscillation frequency detector, and
Claims, characterized in that to compensate for the signal and the Q signal
31. The transmitting / receiving device according to item 31,