JP3303852B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitor, and more particularly to a method for manufacturing a semiconductor memory device.

[0002]

2. Description of the Related Art As a conventional semiconductor device in which a capacitor is integrated on a semiconductor substrate, a dynamic random access memory is used.
Access memory (DRAM) has been put to practical use,
Recently, a non-volatile memory having a structure in which a ferroelectric film is laminated on a MOS type semiconductor device has been developed by the International Electron Devices Meeting (IEDM) '.
87, pages 850-851.

FIG. 5 shows an example of a nonvolatile semiconductor memory having a structure in which a ferroelectric film is laminated on a MOS semiconductor device.
In FIG. 5, reference numeral 501 denotes a P-type silicon substrate;
Reference numeral 2 denotes a LOCOS oxide film for element isolation, reference numeral 503 denotes an N-type diffusion layer serving as a source, and reference numeral 504 denotes an N-type diffusion layer serving as a drain. 505 is a gate electrode, and 506 is an interlayer insulating film. Reference numeral 507 denotes a dielectric film using a ferroelectric, and is sandwiched between a lower electrode 508 and an upper electrode 509 to constitute a capacitor. 510 is a second interlayer insulating film, and 511 is a wiring electrode.

[0004]

In a structure in which a planar capacitor is formed on a semiconductor substrate on which an active element is formed in such a manner as to be adjacent to the active element, at least one capacitor is connected to one memory cell. And the area of the capacitor is determined by the area of the memory cell. In addition, a step for forming the lower electrode 508, the dielectric film 507, and the upper electrode 509 of the capacitor is added, which leads to an increase in cost.

Also, since the lower electrode 508 and the upper electrode 509 are formed separately, the lower electrode 508 and the dielectric 507
And the interface state between the upper electrode 509 and the dielectric 507 are different from each other, resulting in a difference in capacitor characteristics such as polarization depending on the direction of the voltage applied to the electrodes, that is, asymmetry of the capacitor characteristics.

Accordingly, the present invention is to solve such a problem. It is an object of the present invention to reduce the area occupied by a capacitor while maintaining the same capacitance, or to use a region other than a memory cell as a capacitor. It is an object of the present invention to provide a high-performance and high-density semiconductor device at low cost by increasing the effective area of the capacitor, reducing the number of steps required for forming the capacitor, and eliminating the asymmetry of the capacitor characteristics.

[0007]

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention comprises the following steps. In a method of manufacturing a semiconductor device integrated on a semiconductor substrate on which an element is formed,
Forming an active element on the semiconductor substrate; forming an interlayer insulating film above the active element; forming a first contact hole and a second contact hole in a desired region of the interlayer insulating film ;
Forming a contact hole, the first contour
Forming a first embedded plug in the
Forming a second buried plug in the second contact hole
And electrically connecting the first buried plug.
Forming a first electrode having the second embedded plug
Forming a second electrode having an electrical connection to the
A ferroelectric substance is sandwiched between the first electrode and the second electrode.
Forming the ferroelectric so that the first
And forming the second buried plug and forming the first and second electrodes are performed only before the step of forming the ferroelectric. (2) In the step of forming the first and second electrodes ,
2. The method according to claim 1, further comprising the steps of: forming a thin film to be the electrode; and etching the thin film to form the first and second electrodes simultaneously. According to a third aspect of the present invention, there is provided the semiconductor device manufacturing method according to the first or second aspect.
Therefore, it is characterized by being formed.

[0008]

[0009]

[0010]

1 (a) to 1 (d) are main process sectional views showing a first embodiment of a semiconductor device according to the present invention. FIG.
(E) and (f) are main plan views showing a first embodiment of the semiconductor device according to the present invention. First, a first embodiment of the present invention will be described with reference to FIG. Here, for convenience of explanation, an example in which a silicon substrate is used and an N-channel transistor is used will be described.

(FIG. 1A) 101 is a P-type silicon substrate, for example, a wafer having a specific resistance of 20 Ω · cm. Reference numeral 102 denotes an insulating film for element isolation. For example, a silicon dioxide film 60
00 ° is formed. Reference numeral 103 denotes an N-type diffusion layer serving as a source of the transistor.
It is formed by ion implantation of ¹⁵ cm ^-2 . 104
Is an N-type diffusion layer serving as a drain, which is formed simultaneously with 103. Reference numeral 105 denotes a gate electrode, for example, using polysilicon doped with phosphorus. Reference numeral 106 denotes a first interlayer insulating film, which is formed of, for example, a phosphor glass of 4000 .ANG. By a chemical vapor deposition (hereinafter, referred to as CVD) method. 107
Is a wiring electrode, for example, tungsten is sputtered at 5000 °. 108 is a second interlayer insulating film, for example, C
Silicon dioxide is formed at 8000 ° by the VD method. At this time, it is desirable to sufficiently planarize using a combination of spin-on-glass and the like. Reference numeral 109 denotes a through hole buried plug, for example, formed of tungsten by a CVD method.

Reference numeral 110 denotes a dielectric according to the gist of the present invention, for example, lead zirconate titanate (Pb (Ti _0.6 Zr _0.4 ) O ₃ )
Is formed by a 2 μm sputtering method, and is formed into a predetermined pattern by photolithography. At this time, dielectric 1
Since the side wall of 10 is the surface in contact with the electrode of the capacitor,
The effective area of the capacitor increases as the height of the dielectric 110, that is, the thickness at the time of film formation, increases. In addition, since the width of the dielectric 110 is the distance between the electrodes of the capacitor, it is desirable that the width be as small as possible. Since the electrodes of the capacitor are formed only on the side walls of the dielectric 110, the dielectric 1
10 is preferably formed near a buried plug connecting the electrode of the capacitor and the wiring layer or the diffusion layer.

(FIG. 1B) Next, as a film 111 to be an electrode of a capacitor, for example, platinum is formed by sputtering.
000 mm.

(FIG. 1C) Next, the whole surface is etched by anisotropic etching. In this embodiment, the entire surface is etched by applying a beam in a direction perpendicular to the semiconductor substrate 101 by using ion beam etching using, for example, argon, which is an inert gas, as an ion source. Then, because of the anisotropic etching, the side walls of the dielectric 110 are not etched, and the electrodes 112 and 113 remain.
09 is connected in a self-aligned manner. In this embodiment, since the etching is performed using an inert gas, the second interlayer insulating film 108 of the film 111 serving as the electrode of the capacitor is formed.
The upper portions are redeposited on the sidewalls of the dielectric 110 after being etched. Therefore, the film 11 serving as the electrode of the capacitor
Even if the rotation of 1 is poor and not sufficiently deposited on the side wall of the dielectric 110, it is compensated by redeposition, so that the electrodes 112 and 113 of the capacitor can be formed with a sufficient thickness. At this time, as shown in FIG. 1E and FIG.
If a pattern having a closed curve is provided, a step of separating the two capacitor electrodes 112 and 113 is not required.
In FIG. 1E and FIG. 1F, reference numeral 115 denotes a buried plug for connecting one electrode to a wiring layer.

(FIG. 1D) Finally, passivation 1
As 14, for example, silicon nitride (SiN _x ) is formed to a thickness of 1 μm by a CVD method.

The above is a first embodiment of the present invention.

As described above, if the dielectric 111 of the capacitor is formed perpendicular to the semiconductor substrate 101 and two electrodes are formed on both sides thereof, the dielectric 111 can be formed parallel to the semiconductor substrate as shown in the prior art of FIG. When the same electrode area and the same electrode interval are used, the occupied area of the capacitor can be reduced as compared with the case where the capacitors are arranged. In this embodiment, the height of the dielectric 107 is set to 2 μm. However, by further increasing the height, the capacitance of the capacitor can be increased without increasing the area occupied by the capacitor. Further, since the electrodes 112 and 113 of the capacitor are formed simultaneously and without the need for a photolithography step, the number of steps can be reduced, and the interface state between the electrode and the dielectric 111 is symmetrical. There was no difference in capacitor characteristics such as polarization, dielectric constant, and dielectric tangent depending on the direction of the voltage applied to the electrodes.

FIG. 2 is a main sectional view showing a second embodiment of the semiconductor device according to the present invention. A second embodiment of the present invention will be described with reference to FIG. Here, for convenience of description, an example in which a silicon substrate is used and an N-channel transistor is used will be described.

Reference numeral 201 denotes a P-type silicon substrate, for example, a wafer having a specific resistance of 20 Ω · cm. Reference numeral 202 denotes an insulating film for element isolation.
A silicon dioxide (SiO ₂ ) film is formed at 6000 ° by the OS method. 203 is an N-type diffusion layer serving as the source of the transistor, for example, is formed by phosphorus 80keV5 × 10 ¹⁵ cm ^-2 ion implantation. Reference numeral 204 denotes an N-type diffusion layer serving as a drain, which is formed simultaneously with 203. 2
A gate electrode 05 uses, for example, polysilicon doped with phosphorus. 206 is a first interlayer insulating film,
For example, phosphor glass is formed at a thickness of 4000 ° by a CVD method.

Reference numeral 207 denotes a dielectric of the capacitor according to the gist of the present invention. For example, strontium titanate (SrTiO ₃ ) having a high dielectric constant is formed in a width of 0.5 μm and a height of 2 μm.
Reference numerals 208 and 209 denote electrodes of the capacitor according to the present invention. For example, after sputtering platinum at 2000 °, 208 and 209 are formed by a conventional photolithography technique.
Is formed in a desired pattern.

Reference numeral 210 denotes a second interlayer insulating film, which is formed by, for example, 2000 nm of silicon dioxide by a CVD method. 211 is a wiring electrode, for example, aluminum is sputtered at 5000 °.

The above is a second embodiment of the present invention.

As described above, when the dielectric 207 of the capacitor is formed perpendicular to the semiconductor substrate 201 and two electrodes are formed on both sides thereof, the dielectric 207 is formed in parallel with the semiconductor substrate as shown in the prior art of FIG. When the same electrode area and the same electrode interval are used, the occupied area of the capacitor can be reduced as compared with the case where the capacitors are arranged. In this embodiment, the height of the dielectric 207 is set to 2 μm. However, by increasing the height, the capacitance of the capacitor can be increased without increasing the area occupied by the capacitor. Since the electrodes 208 and 209 of the capacitor are formed at the same time, the interface state between the electrode and the dielectric 207 is symmetrical, and there are differences in the capacitor characteristics such as polarization, dielectric constant, and dielectric tangent depending on the direction of the voltage applied to the electrodes. There was no.

FIGS. 3A to 3D are cross-sectional views showing main steps of an embodiment (hereinafter, referred to as a third embodiment) of a method of manufacturing a semiconductor device according to the present invention. According to FIG.
A third embodiment of the present invention will be described. Here, for convenience of description, an example in which a silicon substrate is used and an N-channel transistor is used will be described.

(FIG. 3A) 301 is a P-type silicon substrate, for example, a wafer having a specific resistance of 20 Ω · cm. Reference numeral 302 denotes an insulating film for element isolation. For example, a silicon dioxide film is formed by a conventional LOCOS method.
00 ° is formed. Reference numeral 303 denotes an N-type diffusion layer serving as a source of the transistor.
It is formed by ion implantation of ¹⁵ cm ^-2 . 304
Is an N-type diffusion layer serving as a drain, which is formed simultaneously with 303. A gate electrode 305 is made of, for example, phosphorus-doped polysilicon. Reference numeral 306 denotes a first interlayer insulating film.
Å Form.

(FIG. 3B) Next, for example, platinum is formed to 3 μm as an electrode of the capacitor by a sputtering method, and is formed into a desired pattern by a photolithography technique.

At this time, since the distance between the electrodes 307 and 308 is the distance between the electrodes of the capacitor, it is desirable to reduce the capacitance as much as possible. In this embodiment, the distance between the electrodes 307 and 308 is 1 μm.
m. Further, since the thickness of the electrodes 307 and 308 is one side of the surface that contributes to the capacitance of the capacitor, it is desirable that the thickness be as large as possible.

(FIG. 3C) Next, as the dielectric 309, for example, lead zirconate titanate (Pb (Ti _0.6 Zr _0.4 ) O ₃ )
Is formed by a sol-gel method. At this time, it is necessary to fill the narrow gap between the electrodes 307 and 308 with the dielectric 309. Therefore, the dielectric 309 is preferably formed by a sol-gel method, a CVD method, or the like. Thereafter, the dielectric 309 is sintered at 600 ° C., and is formed into a desired pattern by using a photolithography technique. Without using photolithography, the dielectric 309 can be left only in the gap between the electrodes 307 and 308 by etch back on the entire surface.

(FIG. 3D) Next, the second interlayer insulating film 3
For example, as silicon dioxide, 2
000mm, and holes are drilled where needed. Then, for example, aluminum is formed as the wiring electrode 311 by 1 μm,
Form into a desired pattern.

The above is the third embodiment of the present invention.

As described above, by forming the electrodes 307 and 308 at the same time, the two electrodes required for the capacitor can be formed by one photolithography, so that the manufacturing process can be shortened. Also,
Since the dielectric 309 is formed after the electrodes 307 and 308 are formed, the orientation of the dielectric 309 can be controlled by the orientation of the electrodes.

FIG. 4 is a main sectional view showing an embodiment (hereinafter, referred to as a fourth embodiment) of a semiconductor device according to the present invention. Referring to FIG. 4, a fourth embodiment of the present invention will be described. Again, for convenience of explanation, a silicon substrate is used and N
An example using a channel transistor will be described.

Reference numeral 401 denotes a P-type silicon substrate, for example, a wafer having a specific resistance of 20 Ω · cm. Reference numeral 402 denotes an insulating film for element isolation.
A silicon dioxide film is formed to a thickness of 6000.degree. By the OS method.
403 is an N-type diffusion layer serving as the source of the transistor, for example, is formed by phosphorus 80keV5 × 10 ¹⁵ cm ^-2 ion implantation. Reference numeral 404 denotes an N-type diffusion layer serving as a drain, which is formed simultaneously with 403. A gate electrode 405 uses, for example, polysilicon doped with phosphorus. Reference numeral 406 denotes a first interlayer insulating film, which is formed, for example, of a phosphor glass of 4000 .ANG. By a CVD method. 40
Reference numeral 7 denotes a wiring electrode, for example, tungsten of 5000
Sputter. Reference numeral 408 denotes a second interlayer insulating film, which is formed of, for example, silicon dioxide at 8000 ° by a CVD method.
At this time, it is desirable to sufficiently planarize using a combination of spin-on-glass and the like. Reference numeral 409 denotes a plug for burying a through hole, for example, tungsten is formed by a CVD method.

410 and 411 are according to the gist of the present invention.
These are two electrodes of a capacitor. For example, after forming platinum of 4 μm by sputtering, 410 and 411 are simultaneously formed in a desired pattern. 412 is a dielectric capacitor according to the spirit of the present invention, for example, lead zirconate titanate _{(Pb (Ti 0.6 Zr 0.4)} O 3) sol - forming gel method, sintering at 500 ° C..

The above is the fourth embodiment of the present invention.

As described above, since the portion of the dielectric 412 that contributes to the capacitance is formed perpendicular to the semiconductor substrate 401, the area occupied by the capacitor can be reduced as in the first embodiment. Furthermore, since the dielectric 412 is formed so as to cover not only the capacitor portion but also the entire device, an effect as passivation can be obtained, so that the steps involved in passivation formation can be reduced.

[0037]

According to the present invention, the surface of the capacitor that contributes to the capacitance of the dielectric is perpendicular to the semiconductor substrate, so that the area occupied by the capacitor can be reduced.

Further, according to the present invention, since the two electrodes of the capacitor are formed before and at the same time as the formation of the dielectric, an increase in the number of steps related to the formation of the capacitor can be suppressed.
In addition, the crystal orientation of the dielectric can be controlled by the orientation of the electrodes, and furthermore, there is an effect that differences in characteristics such as the dielectric constant of the capacitor depending on the direction of the applied voltage, that is, asymmetry can be eliminated.

Further, according to the present invention, the passivation of a part of the dielectric of the capacitor has an effect that the number of steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view and a plan view of main steps of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a main cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a main step in a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a main cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a main cross-sectional view of a semiconductor device according to a conventional technique.

[Explanation of symbols]

 Reference Signs List 101 semiconductor substrate 102 element isolation film 103 source region 104 drain region 105 gate electrode 106 first interlayer insulating film 107 wiring electrode 108 second interlayer insulating film 109 buried plug 110 dielectric 111 film to be a capacitor electrode 112 capacitor electrode 113 capacitor electrode 114 Passivation 115 buried plug 201 semiconductor substrate 202 element isolation film 203 source region 204 drain region 205 gate electrode 206 first interlayer insulating film 207 dielectric 208 capacitor electrode 209 capacitor electrode 210 second interlayer insulating film 211 wiring electrode 301 semiconductor substrate 302 element isolation Film 303 source region 304 drain region 305 gate electrode 306 first interlayer insulating film 307 capacitor electrode 308 capacitor electrode 309 dielectric 310 second interlayer insulating film 311 wiring electrode 401 semiconductor substrate 402 element isolation film 403 source region 404 drain region 405 gate electrode 406 first interlayer insulating film 407 wiring electrode 408 second interlayer insulating film 409 buried plug 410 capacitor electrode 411 capacitor electrode 412 Dielectric 501 Semiconductor substrate 502 Element isolation film 503 Source region 504 Drain region 505 Gate electrode 506 First interlayer insulating film 507 Ferroelectric film 508 Lower electrode 509 Upper electrode 510 Second interlayer insulating film 511 Wiring electrode

Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8242 H01L 21/822 H01L 27/04 H01L 27/108

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor device in which a pair of electrodes and a capacitor having a ferroelectric material sandwiched between the pair of electrodes are integrated on a semiconductor substrate on which an active element is formed. Forming an interlayer insulating film above the active element; and forming a first contact hole in a desired region of the interlayer insulating film.
Forming a second contact hole and a first buried plug in the first contact hole
Is formed, and a second filling is performed in the second contact hole.
Forming a first plug having an electrical connection with the first embedded plug.
Forming an electrode and electrically connecting to the second embedded plug
Forming a second electrode having: a ferroelectric material between the first electrode and the second electrode;
Forming the ferroelectric so that the ferroelectric is formed, wherein the step of forming the first and second embedded plugs and the step of forming the first and second electrodes form the ferroelectric. A method of manufacturing a semiconductor device, the method being performed only before the step of performing. 2. A process for forming said first and second electrodes.
In extent, forming a possible thin film and the electrode, method of manufacturing a semiconductor device according to claim 1, characterized in that it comprises a step of forming the first and second electrodes by etching the thin film at the same time. 3. The manufacturing of the semiconductor device according to claim 1.
A semiconductor device formed by a fabrication method.