JP3301691B2 - Digital information playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information reproducing method and a digital information reproducing apparatus for reproducing original digital information from an analog signal reproduced from a recording medium.

[0002]

2. Description of the Related Art PRML signal processing that combines partial response equalization and Viterbi decoding is used as a method for demodulating digital information recorded at high density on a recording medium. When high-density recording is performed on a recording medium, interference between codes occurs due to frequency characteristics of a recording / reproducing system. Partial response equalization can improve the S / N value compared to conventional Nyquist equalization by giving known intersymbol interference. On the other hand, Viterbi decoding is effective when there is a correlation before and after the code. Since partial response equalization gives a known intersymbol interference by giving a correlation between codes, a combination with Viterbi decoding is effective.

However, since Viterbi decoding uses amplitude information of a reproduced signal, it is strongly affected by amplitude fluctuations. For example, in the case of an optical disk which is one of recording media, a level fluctuation occurs in a reproduced signal waveform due to a defocus, a change in reflectivity of the disk, a change in recording power of a laser, and the like.

FIG. 16 is a block diagram showing a schematic configuration of a digital information reproducing apparatus in a conventional optical disk drive. The operation of the digital information reproducing apparatus shown in FIG.
The reflected light from the optical disk 1 is detected by the optical head 2 as a reproduction signal. The detected reproduced signal is amplified by a preamplifier 3 and shaped by an equalizer (hereinafter referred to as EQ) 4. The waveform-shaped reproduced signal is compared with a predetermined slice level in the comparator 7, and a zero-cross point of the reproduced signal is detected.

[0005] The VCO 10 is an oscillation circuit that generates a clock signal by voltage control. The phase comparator 8 compares the timing of the zero-cross point with the timing of the edge of the clock signal output from the VCO 10, and outputs a pulse having a width corresponding to the phase error amount. When the output signal from the phase comparator 8 is supplied to the LPF 9, only the signal component to be followed in the reproduced signal is extracted.

[0006] The VCO 10 is controlled by a signal extracted by the LPF 9. The clock signal oscillated by the VCO 10 is supplied to the A / D converter 5 and the maximum likelihood decoder 6. A
The / D converter 5 quantizes the reproduction signal whose waveform has been shaped by the EQ 4 according to the timing of the clock signal. When the quantized data is input, the maximum likelihood decoder 6 determines the maximum likelihood state transition according to a partial response equalization (hereinafter referred to as PR equalization) method and a state transition determined by a modulation code. Estimate and decode the original digital information.

FIG. 17 shows an example of a signal waveform of each section in a conventional digital information reproducing apparatus. FIG.
As shown by the solid line in (a), consider the case where the reproduced signal is biased by δA in the negative direction due to the influence of the level fluctuation. In the digital information reproducing apparatus described above, even if the VCO 10 outputs the optimal timing signal, the comparator 7
Determines whether the reproduced signal is at a high level or a low level by comparing with a predetermined slice level. When a zero cross point is detected, a pulse having a fixed width is output as shown in FIG. The phase comparator 8 is shown in FIG.
17B. The output of the comparator 7 shown in FIG. 17B is compared with the clock signal of the VCO 11 shown in FIG.
Is output to the LPF 9. Further, the LPF 9 extracts only necessary low-frequency components and outputs a signal shown in FIG.

Accordingly, the comparator 7, the phase comparator 8,
In a conventional timing signal extraction circuit composed of an LPF 9 and a VCO 10, a VC that outputs an optimal timing signal
For O10, a phase error is detected and phase control is performed.

[0009]

Therefore, the clock signal output from the VCO 10 is affected by the level fluctuation included in the reproduced signal. In extreme cases,
In the case of a reproduction signal in which the level fluctuation has a large effect and the zero cross point does not exist for a long time, a state where a phase error cannot be detected may occur. If such a state continues, the reproduction side eventually loses synchronization, causing a fatal error in the PRML signal processing. When the level of the reproduced signal fluctuates in this way, there is a problem that not only a target error rate cannot be achieved, but also accurate clock reproduction cannot be realized.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and provides an accurate A / D converter for quantizing a reproduction signal even when a level fluctuation occurs in the reproduction signal. It is an object of the present invention to provide a digital information reproducing method and a digital information reproducing apparatus for supplying a clock signal and reproducing an original digital signal having a high likelihood.

[0011]

To solve this problem, a digital information reproducing apparatus according to claim 1 has a minimum polarity.
Recorded on a recording medium with a recording code having an inversion interval of 3 or more.
A digital information reproducing apparatus for reproducing original digital information, wherein a, b, c, and d are arbitrary constants, and k is an integer.
When T is the period of the timing signal, the impulse response h (t) of the recording / reproducing system satisfies (Equation 1).
A partial response equalizer for performing waveform shaping, a quantizer for performing quantization using the timing signal ,
Partial response equalizing means and quantization means
(Equation 1) based on the reproduced signal processed by
And the maximum likelihood decoding means for estimating the maximum likelihood state transition sequence from the state transition obtained from the restriction by the minimum polarity inversion interval and reproducing the original digital information .

[0012] The invention according to claim 2 of the present application is a digital camera according to claim 1.
In the total information reproducing apparatus, the a is equal to the d,
It is characterized in that b is equal to c.

The invention of claim 3 of the present application is directed to claim 1 or 2
Digital information reproducing apparatus, the maximum likelihood decoding means
Is between the constraint by the above (Equation 1) and the minimum polarity inversion.
Based on the restriction due to the distance, an operation relating to the cumulative addition of the absolute value of the difference between the amplitude information of the reproduction signal and the expected amplitude is performed.
In addition , the original digital information is decoded by obtaining the maximum likelihood state transition sequence using the operation result .

The invention of claim 4 of the present application is directed to claim 1 or 2
Digital information reproducing apparatus, the maximum likelihood decoding means
Is between the constraint by the above (Equation 1) and the minimum polarity inversion.
Based on the constraint by the interval , perform an operation relating to the cumulative addition of the square of the difference between the amplitude information of the reproduction signal and the expected amplitude,
The method is characterized in that a maximum likelihood state transition sequence is obtained using the calculation result to decode the original digital information.

The invention of claim 5 of the present application is directed to claim 3 or 4
Digital information reproducing apparatus, the maximum likelihood decoding means
Holds the calculation result as the difference between the certainty of each state.
It is characterized by having .

[0016] The invention of claim 6 of the present application is the invention of claims 1 to 5
In the digital information reproducing apparatus of any one, provided with a timing signal extracting means for the extracting said timing <br/> grayed signal from the phase error information output from the maximum likelihood decoding means for providing said quantization means, The maximum likelihood decoding means outputs the reproduced signal.
The phase error information is generated from an expected amplitude value of the signal.

The invention of claim 7 of the present application is directed to claims 1 to 5
In the digital information reproducing apparatus according to any one of the above, the timing signal is extracted by using a predetermined clock and phase error information output from the maximum likelihood decoding means, and the quantization signal is extracted. > A timing signal extracting means for giving the maximum likelihood
The decoding means determines the phase error from the expected amplitude of the reproduced signal.
It is characterized by generating difference information .

The invention according to claim 8 of the present application is a digital camera according to claim 7.
In the digital information reproducing apparatus, the timing signal extracting means includes: a phase comparator for comparing the phase of the predetermined clock with the VCO output; an LPF for band-limiting an output signal of the phase comparator; A band limiting circuit for limiting the phase error information from the
A selector circuit that inputs the output of the F and the output of the band limiting circuit, switches the output with a gate signal indicating the start of the operation of extracting the timing signal, and receives a center frequency control signal and outputs a signal based on the output of the selector circuit. and controls the frequency to generate the VCO output Te, before the VCO output
V given as serial timing signal to said A / D conversion means
CO, and a counter circuit for measuring the time from the time when the gate signal becomes effective to the present time, wherein the frequency characteristic of the band limiting circuit and the transfer function of the VCO are determined by the output of the counter circuit. Is changed.

According to the ninth aspect of the present invention, the digital
In the total information reproducing apparatus, the timing signal extracting means delays the predetermined clock based on a phase control signal.
Was cast, and the phase shift circuit for outputting a clock obtained by the delay as said timing signal, and a band limiting circuit which the limit to the signal components necessary phase error information from the maximum likelihood decoding means,
A variable amplifier that variably amplifies an output signal of the band limiting circuit and outputs the output signal to the phase shift circuit as a phase control signal, and a gate that receives a timing signal from the phase shift circuit and indicates a start of an operation of extracting the timing signal A counter circuit for measuring the time from the time when the signal becomes effective to the present time, wherein the frequency characteristic of the band limiting circuit and the amplification factor of the variable amplifier are changed by the output of the counter circuit. It is characterized by making it.

The invention according to claim 10 of the present application is directed to claims 1 to 5
In the digital information reproducing apparatus according to any one of the above, a timing signal extraction for extracting the timing signal from the phase error information output from the maximum likelihood decoding means and predetermined initial phase information and initial frequency information. Means ,
The maximum likelihood decoding means calculates the maximum likelihood from the expected amplitude of the reproduced signal.
The phase error information is generated, and the quantizing means generates a predetermined
A / D conversion for oversampling signal at lock cycle
Means sampled by said A / D conversion means.
D /
And D conversion means .

The invention of claim 11 of the present application is the invention of claim 10
In the digital information reproducing apparatus, the timing signal extracting unit includes a band limiting unit that limits the phase error information from the maximum likelihood decoding unit to a necessary signal component, and a phase error information band-limited by the band limiting unit. Frequency setting means for oscillating the timing signal as a control voltage, and a timing signal from the frequency setting means are inputted, and the time from the time when the gate signal indicating the start of the timing signal extraction operation becomes valid to the present is measured. A time measuring means for changing the frequency characteristic of the band limiting means and the transfer function of the frequency setting means according to the output of the time measuring means to switch the timing signal between the initial operation and the steady operation. It is characterized by the following.

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

(Embodiment 1) A digital information reproducing method according to a first embodiment of the present invention will be described with reference to the drawings. A run-length-limited code (hereinafter, referred to as an RLL code) that satisfies a so-called (d, k) restriction (d, k is an integer satisfying d, k ≧ 0) as a modulation code, and particularly a condition of a minimum run-length. A code that satisfies (d = 2) is used. The recording code modulates the modulation code by NRZI (Non Return to Zero Inverted).
The impulse response h is used as a partial response equalization.
It is assumed that an equalization method in which (t) satisfies (Expression 1) is used.
If a, b, c, and d are arbitrary constants, k is an integer, and T is the period of the timing signal, (Equation 1) holds.

(Equation 2)

In this embodiment, for the sake of simplicity, so-called PR (1, 3, 3, 1) equalization is taken up, and constants in the impulse response are a = d = 1 and b = c =
3 is assumed. When the recording code with the minimum polarity reversal distance of 3 and the PR (1, 3, 3, 1) equalization method are combined as in the present embodiment, the original digital information b _t (t represents time and is an integer of 0 or more. amplitude value x _t of that) and the PR equalization output follows the state transition diagram of FIG.

In FIG. 1, the symbol S (l, m, n) is assigned to each state.
Is added. S (l, m, n) is 1-bit previous recording code c _t-1 is l, record code c _t-2 of 2 bits before the m
Indicates that the recording code _ct-3 three bits before is n . The symbol of the recording code _ct is set to 0 or 1. In v / u added to the path indicating each state transition in FIG. 1, v is the value of the original digital information b _t input at the current time, and u is the expected amplitude value (amplitude) of the PR equalization output. shows the value) x _t.

The state transition diagram of FIG. 1 developed in the time axis direction is called a trellis diagram, which is shown in FIG. In the figure, k is a discrete value at time t. The trellis diagram is an index indicating the likelihood of each state in performing maximum likelihood decoding. A value obtained as a result of sampling the reproduction signal with the timing signal extracted from the reproduction signal is represented by a reproduction signal amplitude value y.
_{Let t} . Squared cumulatively added every time the absolute value of the difference between the reproduction signal amplitude value y _t and PR equalization output amplitude expected value x _t, and selects a state transition so as to always takes the minimum value. The accumulated value at each time is called a metric value. This metric value is represented by L ^{(l, m, n)} _t at each time t in the trellis diagram.
Are added to each state.

Considering time t, in each state at time t, of the possible state transitions from time t−1,
Select the most likely state transition. Here the state transition is pathi
(I is an integer from 0 to 7), and each state transition is defined as follows.

The metric value L of each state at time t-1
^(1,1,1) _t-1 , L ^(1,1,0) _t-1 , L ^(1,0,0) _t-1 , L
^(0,1,1) _t-1 , L ^(0,0,1) _t-1 , L ^(0,0,0) _t-1 ,
Given the reproduced signal amplitude value y _{t at} time t, six state transitions are selected from eight possible state transitions at each time.

Here, from the state L ^(1,1,1) _t-1 to L ^(1,1,1)
state transition to _t is path7, state L ^(1,1,0) _t-1 to L
State transition to ^(1,1,1) _t is path 6, state L ⁽ 1,0,0 ⁾ _t-1
State transition from L to ^(1,1,0) _t to path 5, state L
State transition from ^(0,0,0) _t-1 to L ^(0,0,1) _t is path4,
The state transition from state L ^(1,1,1) _t-1 to L ^(0,1,1) _t
th3, state transition from state L ^(0,1,1) _t-1 to L ^(0,0,1) _t is path2, state L ^(0,0,1) _t-1 to L ^(0,0, _t ^{) 0)} State transition to _t is path1, state L ^(0,0,0) _t-1 to L ^(0,0,0)
The state transition to _t is called path0.

As described above, the metric value is obtained at each time, and the most likely state transition is selected. The selection result is stored in a register having a predetermined length. Then, from the plurality of state transition sequences, only one state transition sequence according to the trellis diagram in the time axis direction is obtained. This maximum likelihood status transition sequence, so-called survival path p _t. The surviving path p _t from the original digital information b _t is values are found uniquely, maximum likelihood decoding can be realized.

FIG. 3 is a block diagram showing a schematic configuration of a digital information reproducing apparatus according to the first embodiment of the present invention.
In FIG. 1, a reproduced signal reproduced from an optical disk 1 as a recording medium via an optical head 2 and a preamplifier 3 is input to an equalizer (EQ) 4. In the EQ4, the waveform is shaped so that the frequency characteristic of the recording / reproducing system becomes a predetermined PR equalization method. The A / D converter 16 quantizes the waveform-shaped reproduced signal based on the timing signal extracted by the timing signal extractor 18. The maximum likelihood decoding unit 17 estimates the maximum likelihood state transition sequence from the input quantized data,
Play back the original digital information. Further, the maximum likelihood decoding means 17 outputs phase error information to the timing signal extracting means 18 using the decoding result. The timing signal extracting means 18 generates a timing signal based on the phase error information,
/ D conversion means 16. Hereinafter, the configuration and operation of each block will be described in detail.

FIG. 4 is a block diagram showing the configuration of the maximum likelihood decoding means 17 used in the digital information reproducing apparatus of the first embodiment. The maximum likelihood decoding means 17 includes a branch metric calculation means 11 (hereinafter, referred to as BMU), an addition / comparison / selection means 12
(Hereinafter referred to as ACS), surviving path detecting means 13
(Hereinafter, referred to as SMU), smoothing means 14 (hereinafter, LP)
F) and a shift register 15 (hereinafter referred to as REG).

Here, the operation of the maximum likelihood decoding means 17 will be described in detail. The expected amplitude values of the eight PR equalized outputs output from the LPF 14 are represented by x _{i, t} . Where i is the aforementioned 8
Among the types of state transitions, the numbers of path _i (i = 0 to 7) are indicated, and t indicates time. The BMU 11 calculates a so-called branch metric of the absolute value of the difference between the reproduced signal amplitude value y _t and the PR equalized output amplitude value x _{i, t} expressed by the following (Equation 2). − (Y _t −x _{i, t} ) ² i is an integer of 0 to 7 (formula 2)

The expected amplitude value x _{i, t} represents the amplitude value after PR equalization when each state transition occurs in the response characteristics of the recording / reproducing system. For example, an ideal PR (1, 3, 3,
1) In the case of equalization, as shown in FIGS. 1 and 2, x _{7, t} =
8, x _{3, t} = x _{6, t} = 7, x _{2, t} = x _{5, t} = 4, x _{1, t}
= X _{4, t} = 1, x _{0, t} = 0.

Here, a method of selecting the most likely state transition from the possible state transitions from time t-1 in each state at time t will be described. Using (Equation 2), the following (Equation 3) is obtained. _{^{L (1,1,1) t = max [}} L (1,1,1) t-1 - (y t - x 7, t) 2, L (1,1,0) t-1 - (y t -x _{6, t} ) ² ] L ^(1,1,0) _t = L ^(1,0,0) _t-1- (y _t -x _{5, t} ) ² L ^(1,0,0) _t = _{^{L (0,0,0) t-1 -}} (y t - x 4, t) 2 L (0,1,1) t = L (1,1,1) t-1 - (y t - x 3 _{, t} ) ² L ^(0,0,1) _t = L ^(0,1,1) _t-1- (y _t -x _{2, t} ) ² L ^(0,0,0) _t = max [L ^{( _{0,0,1) t-1 - (y}} t - x 1, t) 2, L (0,0,0) t-1 - (y t - x 0, t) 2] ··· ( formula 3 Here, max [α, β] is an operator that selects a larger value from α and β.

Further, the difference M of the metric value of each state
_{j, t} (j is an integer from 1 to 6) is defined as the following (Equation 4). M _{1, t} = L ^(0,0,0) _t -L ^(0,0,1) _t M _{2, t} = L ^(0,0,1) _t -L ^(0,1,1) _t M _{3 , t} = L ^(0,1,1) _t -L ^(1,1,1) _t M _{4, t} = L ^(1,0,0) _t -L ^(0,0,0) _t M _{5, t} = L ^(1,1,0) _t- L ^(1,0,0) _t M _{6, t} = L ^(1,1,1) _t- L ^(1,1,0) _t ... (Equation 4 )

By substituting (Equation 3) into (Equation 4), the following (Equation 5) is obtained. M _{2, t} = M _{3, t-1} + (y _t -x _{3, t} ) ^2- (y _t -x _{2, t} ) ² M _{5, t} = M _{4, t-1} + (y _t -x _{(4, t} ) ² − (y _t −x _{5, t} ) ² M _{1, t−1} ≧ (y _t −x _{0, t} ) ² − (y _t −x _{1, t} ) ^2, then M _{1, t = M 1, t-1 +} M 2, t-1 + (y t -x 2, t) 2 - (y t -x 0, t) 2 M 4, t = (y t -x 0, t) 2 _{- (y t -x 4, t} ) 2 M 1, t-1 <(y t -x 0, t) 2 - (y t -x 1, t) 2 if _{M 1, t = M 2,} t _{-1 + (y t -x 2,} t) 2 - (y t -x 1, t) 2 M 4, t = M 1, t-1 + (y t -x 1, t) 2 - (y t −x _{4, t} ) ² M _{6, t-1} ≧ (y _t −x _{7, t} ) ² − (y _t −x _{6, t} ) ² If M _{3, t} = (y _t −x _{7, t} ) ^2- (y _t -x _{3, t} ) ² M _{6, t} = M _{5, t -1} + M _{6, t -1} + (y _t -x _{5, t} ) ^2- (y _t -x _{7, t} ) ² M _{6, t-1} <(y _t −x _{7, t} ) ² − (y _t −x _{6, t} ) ^2, then M _{3, t} = M _{6, t−1} + (y _t −x _{6 , t} ) ² − (y _t− x _{3, t} ) ² M _{6, t} = M _{5, t−1} + (y _t −x _{5, t} ) ² − (y _t −x _{6, t} ) ² (Equation 5)

FIG. 5 shows the first BMU 1 in this embodiment.
It is a block diagram which shows the structure of 1A. BMU11A is
It is composed of an absolute value calculator 11a of eight circuits, a square calculator 11b, and a subtractor (sub) 11c. The BMU 11A calculates the square value of the absolute value of the difference between the quantized data of the reproduced signal amplitude value y _t and the amplitude expected value x _{i, t} of the PR equalization output, that is, a so-called branch metric. The operation is performed, and the operation results E01, _t , E76, _t , E32, _t , E45, _t , E20, _t ,
E04, _t , E21, _t , E14, _t , E73, _t , E57, _t ,
E63, _t and E56, _t are output to the ACS 12.

E 01, _t = (y _t −x _{0, t} ) ² − (y _t −x _{1, t} ) ² E 76, _t = (y _t −x _{7, t} ) ² − (y _t −x _{6, ^{t) 2 E32, t = (}} y t -x 3, t) 2 - (y t -x 2, t) 2 E45, t = (y t -x 4, t) 2 - (y t -x 5, ^{_{t) 2 E20, t = (}} y t -x 2, t) 2 - (y t -x 0, t) 2 E04, t = (y t -x 0, t) 2 - (y t -x 4, ^{_{t) 2 E21, t = (}} y t -x 2, t) 2 - (y t -x 1, t) 2 E14, t = (y t -x 1, t) 2 - (y t -x 4, ^{_{t) 2 E73, t = (}} y t -x 7, t) 2 - (y t -x 3, t) 2 E57, t = (y t -x 5, t) 2 - (y t -x 7, ^{_{t) 2 E63, t = (}} y t -x 6, t) 2 - (y t -x 3, t) 2 E56, t = (y t -x 5, t) 2 - (y t -x 6, _t ) ² ... (Equation 6)

FIG. 6 is a block diagram of the ACS 12 in this embodiment. ACS12 has eight adders (add)
12a, two comparators (comp) 12b, four selectors (sel) 12c, six registers (reg) 12
d. The ACS 12 always stores the difference M _{j, t-1} (j is an integer from 1 to 6) of the metric value at the time t−1 in the register 12d at the time t. And ACS
12 is an input signal E01, _t , represented by (Equation 6) at time _t .
E76, _t , E32, _t , E45, _t , E20, _t , E04, _t ,
E21, _t , E14, _t , E73, _t , E57, _t , E63, _t ,
E56, _t and the difference between the metric values at time t-1, M1 _{, t-1} , M2 _{, t-1} , M3 _{, t-1} , M4 _{, t-1} , M5 _{, t-1} ,
From M _{6, t−1} , the time t is calculated by the following equation (Equation 7).
Metric value differences M _{1, t} , M _{2, t} , M _{3, t} ,
M _{4, t} , M _{5, t} , M _{6, t} are obtained respectively.

[0047] _{M 2, t = M 3,} t-1 + E32, t M 5, t = M 4, t-1 + E45, t M 1, if _{t-1 ≧ E01, t M} 1, t = M 1 _{, t-1 + M 2,} t-1 + E20, t M 4, t = E04, t M 1, t-1 <E01, t if _{M 1, t = M 2,} t-1 + E21, t M 4, _{t = M 1, t-1} + E14, t M 6, t-1 ≧ E76, t if _{M 3, t = E73, t} M 6, t = M 5, t-1 + M 6, t-1 + E57, _t M6 _{, t-1} <E76, if _t , M3 _{, t} = M6, _{t -1} + E63, tM6 _{, t} = M5, _{t -1} + E56, _t (Equation 7)

Since the value stored in the register 12d is the difference between the metric values of the two states, it always indicates a value smaller than a predetermined value. Therefore, no matter what value the metric value of each state has, the difference M _{j, t-1} (j is an integer from 1 to 6) of the metric value can be represented by a predetermined bit width.

Further, the ACS 12 obtains the difference between the metric values, and simultaneously outputs to the SMU 13 which of the eight state transitions has been selected as 2-bit information. These two-bit output signals are called selection signals,
SEL0 and SEL1. Here, a specific operation of the ACS 12 will be described. At every time t, the ACS 12 sets path2, pa
Be sure to select th3, path4 and path5. Where M
_{If 1, t-} 1.gtoreq.E01, _t , path0 is selected, and a selection signal SEL0 indicating a high level is output to the SMU13. Conversely, M
_{If 1, t-1} <E01, _t , path1 is selected, and a selection signal SEL0 indicating a low level is output to the SMU13. Also M
_{6, if t-} 1≥E76, _t , path7 is selected, and a selection signal SEL1 indicating a high level is output to the SMU13. Conversely, M
_{If 6, t-1} <E76, _t , path6 is selected, and a selection signal SEL1 indicating a low level is output to the SMU13.

FIGS. 7 to 9 are block diagrams showing the configuration of the SMU 13 according to the present embodiment. The operation of the SMU 13 will be described in detail. The SMU 13 has eight channels of registers (hereinafter, referred to as path memories) of a predetermined length (hereinafter, referred to as path memory length m), and based on the selection signal input from the ACS 12, stores the result of the state transition selection. Store in path memory. Since eight state transitions can occur, 1
A number of registers corresponding to the path memory length are prepared for each state transition.

This path memory is represented by MEM _{i, n} . i is an integer from 0 to 7 and represents the number of the state transition path _i .
For simplicity, only the integer i is added to the subscript. Further, n indicates the address of the path memory, and takes a value from 1 to the path memory length m. The SMU 13 includes a plurality of logic circuits A, a logic circuit B, and a register D. The logic circuit A outputs a signal f that satisfies f = a × (b + c) from three inputs a, b, and c. Note that the symbol x represents a logical product,
The symbol + represents a logical sum. The logic circuit B outputs a signal g satisfying g = d × e from two inputs d and e.
The logic circuit A and the logic circuit B can remove, from the path memory, a state transition that does not survive at the time t + 1 among the state transition selection results at the time t from the state transition selection results at the time t and the time t + 1.

For example, time t, time t + 1, and time t +
2, the selection signals SEL0 and SEL0 both at a high level
The case where SEL1 is input will be described. As described above, since the selection signals SEL0 and SEL1 are at the high level, the path
0 and path7 are selected, and path1 and path6 are not selected.

At time t, the SMU 13 selects the selection signal SEL0.
And SEL1 are input, the path memories MEM _0,1 , MEM _2,1 , ME
M _3,1, MEM _4,1, stores MEM _5,1, respectively MEM _{7, 1} '1', and stores "0" in the MEM _{1, 1} and MEM _6,1. Here '1'
Indicates that the data stored in the register is at a high level, and '0' indicates that the data stored in the register is at a low level.

When the selection signals SEL0 and SEL1 are input at time t + 1, the path memories MEM _0,1 , MEM _1,1 , MEM _2,1 , ME
The data stored in M _3,1 , MEM _4,1 , MEM _5,1 , MEM _6,1 , MEM _7,1 is transferred to the path memories MEM _0,2 , MEM _1,2 , MEM _2,2 , ME
M _3,2 , MEM _4,2 , MEM _5,2 , MEM _6,2 , MEM _7,2 , respectively, and the path memories MEM _0,1 , MEM _2,1 , MEM _3,1 , MEM _4,1 , MEM
'1' to _5,1 and MEM _7,1 respectively, '1' to MEM _1,1 and MEM _6,1
0 'is stored.

Further, at time t + 2, the selection signal SEL0 and
When SEL1 is input, the input “a” of the logic circuit A becomes data “1” of MEM _0,2 , the input “b” of the logic circuit A becomes data “1” of MEM _0,1 and data “1” of MEM _4,1 . Assuming that 1 'is the input c of the logic circuit A, the output of the logic circuit A becomes f =' 1 'and is stored in _MEM0,3 .

The input “a” of the logic circuit A becomes data “0” of MEM _1,2 , the input b of the logic circuit A becomes data “1” of MEM _0,1 and data “1” of MEM _4,1. Is the input c of the logic circuit A, the output of the logic circuit A becomes f = '0', and the value of f is stored in MEM _1,3 .

Further, the data “1” of MEM _2,2 is transferred to the logic circuit B.
And the data '0' of MEM _1,1 is input e of the logic circuit B, the output of the logic circuit B becomes g = '0'.
stores the value of g in MEM _2,3.

Further, the data “1” of MEM _3,2 is transferred to the logic circuit B.
When the data d of MEM _{2 , 1} is input e of the logic circuit B, the output of the logic circuit B becomes g = '1', and the value of g is stored in MEM _3,3 .

Further, the data “1” of MEM _4,2 is transferred to the logic circuit B.
If the data d of MEM _5,1 is input e of the logic circuit B, the output of the logic circuit B becomes g = '1', and the value of g is stored in MEM _4,3 .

Also, the data “1” of MEM _5,2 is transferred to the logic circuit B
And the data '0' of MEM _6,1 as the input e of the logic circuit B, the output of the logic circuit B becomes g = '0'.
Store the value of g in MEM _5,3 .

The input “a” of the logic circuit A becomes data “0” of MEM _6,2 , the input “b” of logic circuit A becomes data “1” of MEM _3,1 and data “1” of MEM _7,1. Is the input c of the logic circuit A, the output of the logic circuit A becomes f = '0', and the value of f is stored in _MEM6,3 .

Further, the input “a” of the logic circuit A becomes data “1” of MEM _7,2 , the input “b” of the logic circuit A becomes data “1” of MEM _3,1 and data “1” of MEM _7,1. Is the input c of the logic circuit A, the output of the logic circuit A becomes f = '1', and the value of f is stored in _MEM7,3 .

By the above operation, from time t to time t + 1
, Path2 and path5 have been removed.
Further, the path memories MEM _0,1 , MEM _1,1 , MEM _2,1 , MEM _3,1 , ME
The data stored in M _4,1 , MEM _5,1 , MEM _6,1 , MEM _7,1 is changed to path memories MEM _0,2 , MEM _1,2 , MEM _2,2 , MEM _3,2 , MEM
_4,2 , MEM _5,2 , MEM _6,2 , MEM _7,2 , respectively, and the path memories MEM _0,1 , MEM _2,1 , MEM _3,1 , MEM _4,1 , MEM _5,1 , MEM
The respective _7,1 '1' stores '0' MEM _{1, 1} and MEM _6,1.

When the operation in the path memory MEM _{i, 3} (i is an integer from 0 to 7) is also performed on MEM _{i, n} (n is an integer of 4 or more and the path memory length or less), the path memory length becomes sufficiently large. If it is larger, '1' will be stored in only one of the eight path memories MEM _{i, m} .
This is the surviving path.

As described with reference to the state transition diagram of FIG. 1, if “1” is stored in the path memory MEM _{3, m or} “1” is stored in the path memory MEM _{4, m} , the SMU 13 Outputs '1' as the decoding result, otherwise SMU
13 outputs '0' as a decoding result. Thereby, the original digital information b _t is reproduced. The SMU 13 uses 8-bit information p _{i, t} (i is an integer from 0 to 7 and t is an integer indicating time) indicating the surviving path as p _{i, t} = MEM
Output to the LPF 14 so as to satisfy _{i, m} (m is the path memory length), and output to the timing signal extracting means 18 described later as phase error information.

In the SMU 13 of the first embodiment, the logic circuit A and the logic circuit B use the state transition selection result at time t and time t + 1 to determine the state transition that does not survive at time t + 1 among the state transition selection results at time t. It is configured to be removed from the path memory. However, from time t to time t + r (r
The same effect can be obtained by removing the state transitions that cannot survive from the time t + 1 to the time t + r from the path memory out of the state transition selection results at the time t from the state transition selection results at the time t.

In FIG. 4, a shift register (REG)
15 outputs a reproduction signal amplitude value y _t of treatment time period delayed by the BMU11 and ACS12 and SMU13 the LPF 14. It also outputs the phase error information to the timing signal extracting means 18 described later.

The LPF 14 performs two operations, an initial operation and a steady operation. The initial operation is a so-called acquisition mode, which is an operation for extracting a timing signal from a specific pattern on a recording medium at a high speed and synchronizing with it.
The steady operation is called a tracking mode, and is an operation for extracting a timing signal from a reproduction signal and following the timing signal.

The LPF 14 has the expected amplitude values x _{7, t} , x _{6, t} ,
has a register for storing _{x 5, t, x 4,} t, x 3, t, x 2, t, x 1, t, x 0, t, performs a calculation that satisfies the following equation (8), Store the operation result in the register.

If p _{i, t} is “1”, x _{i, t + 1} = (1 / N) × y _t + ((N−1) / N) × x
_{i, t} where N is a positive integer i is an integer from 0 to 7 (Equation 8)

In the initial operation, an externally supplied 8
Initial expected values x _{7, init of} the two PR equalized outputs
x _{6, init} , x _{5, init} , x _{4, init} , x _{3, init} , x _{2, init} ,
Although x _{1, init} and x _{0, init} are output to the BMU 11, in the steady operation, the operation of (Equation 8) is performed, and the updated register data is used as the expected amplitude x _{7, t of the} eight PR equalized outputs. , X
_{6, t} , x5 _{, t} , x4 _{, t} , x3 _{, t} , x2 _{, t} , x1 _{, t} , x
Output to the BMU 11 as _{0, t} . This means that the response characteristic of the recording / reproducing system is detected from the maximum likelihood decoding result, and the PR equalization characteristic is adaptively changed from the detection result.

The timing signal extracting means 18 outputs the SMU1
Survivor path is output from the 3 P _i, and _t, and inputs the reproduction signal amplitude value y _t output from REG15, shown below calculated according to (Equation 9) performed. If p _{i, t} is “1”, level _{i, t} = (1 / N) × y _t + ((N−1) / N) ×
level _{i, t-1} where N is a positive integer i = 2 or 5 (Equation 9)

When there is no phase error in the timing signal used for quantization of the reproduction signal and the equalization characteristic of the recording / reproduction system has an impulse response represented by (Equation 1), level _{2 and t} indicate the rising _edge of the reproduction signal. Take the value of the amplitude value c + d of the falling waveform,
Level _{5 and t} take the value of the amplitude value a + b of the rising waveform of the reproduction signal. Considering the case of a symmetrical impulse response for simplicity, a = d and b = c, so level _{2, t} = level
_{5, t} is satisfied. Therefore, the phase error amount is calculated by the following (Equation 10).
Defined by phase_error _t = level _{2, t} -level _{5, t} ... (Equation 10)

[0074] Phase error amount phase _error _t, when a positive value is progressing from the sampling position phase should quantization timing signals, delayed from the sampling position phase should quantization timing signal when a negative value Will be. Timing signal extracting means 18
Generates a predetermined timing signal based on the phase error amount, the amplification factor of the amplifier for amplifying the phase error amount, and the initial phase information, and outputs the signal to the A / D converter 16.

FIG. 10 is a block diagram showing the configuration of the second branch metric calculation means 11B in the maximum likelihood decoding means 17. In the first branch metric calculating means 11A, when calculating the branch metric, illustrating a method of calculating the square of the absolute value of the difference between the amplitude expected value x _t of the PR equalization output (Equation 2). In the second branch metric calculation means 11B,
Replaced by (Equation 2) shown below (Equation 11), and calculates the absolute value of the difference between the amplitude expected value x _t of the PR equalization output. In this method, a square calculator is not required, so that the circuit scale can be reduced.

-ABS [y _t -x _{i, t} ] i is an integer from 0 to 7 ABS [α] is an operator for obtaining the absolute value of α (Equation 11)

(Embodiment 2) Next, a digital information reproducing apparatus according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a block diagram showing a basic configuration of a digital information reproducing apparatus according to the second embodiment. Here, the reproduction signal reproduced from the recording medium is oversampled by the A / D converter 19 at a fixed clock. The data sampled by the A / D converter 19 is requantized by the D / D converter 20. The timing signal input to the D / D converter 20 is
Provided from the timing signal extracting means 22, the D / D converting means 20 outputs quantized data synchronized with the timing signal included in the reproduction signal.

The maximum likelihood decoding means 21 estimates the maximum likelihood state transition from the input quantized data, and reproduces and outputs the original digital information. The maximum likelihood decoding means 21 gives the phase error information to the timing signal extracting means 22 from the decoding result.
The timing signal extracting means 22 performs an LPF process of removing high frequency components from the phase error information, and calculates a phase error amount. Then, the timing signal extracting means 22 obtains the oscillation frequency from the initial phase information (hereinafter, referred to as init_timing), the initial frequency information (hereinafter, referred to as init_interval), and the phase error amount, and outputs a timing signal.

The operation of the present embodiment will be described in more detail. Timing signal extracting means 22 inputs the reproduction signal amplitude value y _t delayed surviving path p _i which is output from the maximum likelihood decoding section _{21, t} and BMU11 and ACS12 and SMU13 spent in were treated only time, the following (Equation 9 ). The calculation result is stored in a register (not shown)
Store as _{i, t} . If p _{i, t} is “1”, level _{i, t} = (1 / N) × y _t + ((N−1) / N) ×
level _{i, t-1} where N is a positive integer i = 2 or 5 (Equation 9)

When there is no phase error in the timing signal used for quantization in the D / D converter 20 and the equalization characteristic of the recording / reproducing system is an impulse response represented by (Equation 1), le
vel _{2, t} has a value of amplitude values c + d falling waveform of the reproduced _signal, level _{5, t} has a value of amplitude values a + b of the rising waveform of the reproduced signal. Considering the case of a symmetrical impulse response for simplicity, a = d and b = c.
_{2, t} = level _{5, t} is satisfied. Therefore, the phase error amount is defined by (Equation 10) described above. phase_error _t = level _{2, t} -level _{5, t} ... (Equation 10)

[0081] Phase error amount phase _error _t, when a positive value is progressing from the sampling position phase should quantization timing signals, delayed from the sampling position phase should quantization timing signal when a negative value Will be. Further, the set frequency interval of the frequency setting means included in the timing signal extracting means 22
_t is defined by the following (Equation 12). interval _t = init_interval / (1−GAIN × phase_error _t × init_interval) where GAIN is an amplification factor of the frequency setting means. ... (Equation 12)

When the impulse response is asymmetric, (Equation 12) is transformed into the following (Equation 13). interval _t = init_interval / (1-GAIN × (phase_error _t- (a + bcd)) × init
Here, GAIN is the amplification factor of the frequency setting means. ... (Equation 13)

Further, the timing signal extracting means 22 defines the timing _{t of the} timing signal by the following (Equation 14). timing _t = timing _t−1 + intervel _t where timing ₀ = init_time. ... (Equation 14)

The timing signal extracting means 22 outputs the extracted timing signal timing _t to the D / D converting means 20. The result of the A / D converter 19 oversampling the reproduced signal with a fixed clock having a period T is represented by z _m (m
Is an integer of 1 or more). The D / D conversion means 20 is an A / D
The result z _m sampled by the conversion means 19 and the timing signal timing _t output by the timing signal extraction means 22
From calculates the reproduced signal amplitude value y _t quantized a reproduction signal by the following equation (15). If T × (m−1) ≦ timing _t <T × m, then y _t = ((timing _t− T × (m−1)) / T) × z _m + ((T × m−timing _t ) / T ) × z _m-1 ··· (equation 15) thus obtained reproduction signal amplitude value y _t maximum likelihood decoding means 2
Output to 1.

As described above, an accurate timing signal can be extracted from a reproduced signal and can follow the extracted timing signal. In addition, since all operations can be realized by digital signal processing, the adjustment that was required when a conventional analog circuit was used is unnecessary.

The steady operation following the timing signal included in the reproduction signal has been described above. A method for extracting a timing signal from a specific pattern on a recording medium and synchronizing at a high speed will be described. It is assumed that the format of the recording medium is configured in sector units, and data and a VFO pattern of a predetermined length, so-called run-up, are included at the beginning of the data. The gate signal is a signal indicating the range of a valid reproduction signal in a sector according to the format of the recording medium. In this embodiment, the signal processing operation is started according to the gate signal. In a normal run-up, a signal of a single pattern is recorded and used for a pull-in operation of a PLL circuit.

FIG. 12 is a block diagram of the timing signal extracting means 22 of the present embodiment. The phase error information output from the maximum likelihood decoding means 21 is input to the band limiting means 23. The band limiting unit 23 calculates ( Equation 9 ) and ( Equation 10 ), obtains the phase error amount, and outputs it to the frequency setting unit 24. The frequency setting means 24 calculates (Equation 12) or (Equation 13) and (Equation 14)
, An oscillation frequency is obtained from the initial phase information, the initial frequency information, and the phase error amount, and a timing signal is output to the D / D conversion means 20. When the gate signal becomes valid, the time measuring unit 25 counts the timing signal, and changes the value of N in ( Expression 9 ) and the value of GAIN in (Expression 12) or (Expression 13) when the timing signal reaches a predetermined value. So that the band limiting means 2
3 and a control signal to the frequency setting means 24.

In the initial operation, the value of N in ( Equation 9 ) is reduced,
The value of GAIN in (Equation 12) or (Equation 13) is set to be high, and in steady operation, the value of N in ( Equation 9 ) is increased, and the value of GAIN in (Equation 12) or (Equation 13) is decreased. , The time measuring means 25 controls. With the above operation, the transition from the initial operation to the steady operation can be realized at high speed.

Embodiment 3 Next, a digital information reproducing apparatus according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a block diagram showing a basic configuration of a digital information reproducing apparatus according to the third embodiment. In the present embodiment, the timing signal extracting unit 28 converts the phase error information output from the maximum likelihood decoding unit 27 into a built-in V using the phase error amount defined by ( Equation 10 ).
The configuration is such that the oscillation frequency of the CO is controlled.

The reproduced signal reproduced from the recording medium is A /
The data is sampled by the D conversion means 26 and converted into quantized data. The maximum likelihood decoding means 27 estimates the maximum likelihood state transition from the input quantized data, and reproduces and outputs the original digital information. The maximum likelihood decoding means 27 outputs phase error information from the decoding result to the timing signal extracting means 28.
The timing signal extracting unit 28 performs an LPF process for removing unnecessary signal components from the phase error information, and calculates a phase error amount. Then, the timing signal extracting means 28 determines the oscillation frequency from the input recording clock and the phase error amount, and outputs the timing signal to the A / D converting means 26.

Here, the operation of the digital information reproducing apparatus of the present embodiment will be described in detail. Timing signal extracting means 28
Inputs the 8-bit information p _{i, t} indicating the surviving path output as the phase error information from the maximum likelihood decoding means 27 and the reproduced signal amplitude y _t, and performs A / D conversion using the oscillation output as a timing signal. Output to means 26.

FIG. 14 is a block diagram of the first timing signal extracting means 28A in this embodiment. The center frequency of the VCO 30 is set by a center frequency control signal. If the gate signal is not valid, the phase comparator 29 compares the input recording clock with the phase of the oscillation output of the VCO 30 and outputs the comparison result to the LPF 31.

The LPF 31 extracts a signal component necessary for the VCO 30 to follow the recording clock, and outputs the signal component to the selector circuit 32. The selector circuit 32 is controlled by a gate signal, and outputs an output signal of the LPF 31 to the VCO 30. Therefore, the VCO 30 oscillates in synchronization with the recording clock. Next, when the gate signal becomes valid, the band limiting circuit 33 outputs the phase error amount defined by ( Equation 10 ) to the D / A converter 34. The D / A converter 34 outputs the conversion result to the selector circuit 32. Then, the selector circuit 32
The output signal of the D / A converter 34 is output to the VCO 30.
Therefore, the timing signal can be controlled based on the phase error information from the maximum likelihood decoding means 27.

A method for synchronizing at a higher speed will be described. When the gate signal indicating the start of the operation of the signal processing is enabled, the counter circuit 35 counts the timing signal reaches the predetermined value, the band limiting circuit 33 (Formula
9 ) The band limiting circuit 33 and the VCO 30 are controlled so as to change the value of N and the amplification factor of the VCO 30. Generally, when the gate signal becomes valid, a run-up pattern is input. Therefore, in the initial operation, the value of N in ( Equation 9 ) is reduced,
The value of the amplification factor of CO30 is set high. In the steady operation, the counter circuit 35 controls so that the value of N in ( Equation 9 ) is large and the value of the amplification factor of the VCO 30 is low. With the above operation, the transition from the initial operation to the steady operation can be realized at high speed.

Next, the operation of another timing signal extracting means for controlling the phase of the recording clock using the phase error will be described in detail. FIG. 15 is a block diagram showing a configuration of the second timing signal extracting means 28B in the present embodiment. If the gate signal is not valid, the phase shift circuit 36 uses the recording clock as a timing signal to output the A / D converter 2
6 is output. When the gate signal becomes valid, the band limiting circuit 37 outputs the phase error amount defined by ( Equation 10 ) to the variable amplifier 38. The variable amplifier 38 amplifies the amount of phase error and outputs the operation result to the phase shift circuit 36. The phase shift circuit 36 controls the phase of the recording clock using a built-in variable delay circuit based on the amplified phase error amount.

A method for synchronizing at a higher speed will be described. When the gate signal indicating the start of the operation of the signal processing is enabled, the counter circuit 39 counts the timing signal reaches the predetermined value, the band limiting circuit 37 (Formula
9 ) To change the value of N and the amplification factor of the variable amplifier,
A control signal is output to the band limiting circuit 37 and the variable amplifier 38. In general, the gate signal is enabled, the run-up pattern is input, the initial operation decreases the value of N in Equation (9), the value of the amplification factor of the variable amplifier 38 is set high, in the steady operation (Equation 9) Of the counter circuit 3 so that the value of N of the variable amplifier 38 becomes large and the value of the amplification factor of the variable amplifier 38 becomes low.
9 gives control. With the above operation, the transition from the initial operation to the steady operation can be realized at high speed.

The operation of the maximum likelihood decoding means 17 in FIG. 3 has been described using a run-length limiting code with a minimum polarity inversion interval of 3, but other run-length limiting codes may be used.

[0098]

As described above, according to the digital information reproducing apparatus of the present invention, the timing signal extracting means classifies the quantized data based on the surviving path obtained during the Viterbi decoding operation, and classifies the quantized data. Detect the response characteristics of the recording and reproduction system using the quantized data obtained, find the level fluctuation included in the reproduction signal, calculate the level fluctuation component due to the phase shift of the timing signal output from the timing signal extraction means, The phase of the timing signal is controlled based on the calculation result. Thus, accurate timing signal extraction can be realized. Further, by performing the operation of extracting the timing signal included in the reproduction signal by a digital method, a configuration suitable for digital signal processing that does not require analog adjustment is provided.

Further, when the phase of the timing signal is controlled using the detection result of the phase shift of the timing signal, the control characteristic is changed between the initial operation and the steady operation of the timing signal extracting operation to achieve a high-speed steady operation. Can be migrated.

Further, according to the digital information reproducing apparatus of the present invention, Nyquist equalization is achieved by a combination of a modulation code having a minimum polarity inversion interval of 3 or more and PR equalization allowing more intersymbol interference. , The S / N value can be improved and a good error rate can be realized.

[Brief description of the drawings]

FIG. 1 shows a recording code having a minimum polarity reversal distance of 3 and PR (1,
FIG. 3 is a state transition diagram in the case of combining with (3, 3, 1) equalization method.

FIG. 2 shows a recording code having a minimum polarity reversal distance of 3 and PR (1,
FIG. 3 is a trellis diagram in the case of combining with (3,3,1) equalization method.

FIG. 3 is a schematic configuration diagram of a digital information reproducing device according to the first embodiment of the present invention.

FIG. 4 is a block diagram of a maximum likelihood decoding unit in the digital information reproducing device of the first embodiment.

FIG. 5 is a block diagram of a first branch metric calculating means (BMU) 11A in the digital information reproducing apparatus of the first embodiment.

FIG. 6 is a block diagram of an addition / comparison / selection operation unit (ACS12) in the digital information reproducing apparatus according to the first embodiment.

FIG. 7 is a block diagram (No. 1) of a surviving path detecting means (SMU) 13 in the digital information reproducing apparatus of the first embodiment.

FIG. 8 is a block diagram (part 2) of the surviving path detecting means (SMU) 13 in the digital information reproducing apparatus of the first embodiment.

FIG. 9 is a block diagram (part 3) of a surviving path detecting means (SMU) 13 in the digital information reproducing apparatus of the first embodiment.

FIG. 10 is a block diagram of a second branch metric calculation unit (BMU) 11 in the digital information reproducing apparatus of the first embodiment.

FIG. 11 is a schematic configuration diagram of a digital information reproducing device according to a second embodiment of the present invention.

FIG. 12 is a configuration diagram of a timing signal extracting unit 22 in the digital information reproducing device of the second embodiment.

FIG. 13 is a schematic configuration diagram of a digital information reproducing device according to a third embodiment of the present invention.

FIG. 14 is a configuration diagram of a first timing signal extracting unit 28A in the digital information reproducing device of the third embodiment.

FIG. 15 is a configuration diagram of a second timing signal extracting unit 28B in the digital information reproducing device of the third embodiment.

FIG. 16 is a block diagram illustrating a configuration example of a conventional digital information reproducing device.

FIG. 17 is a signal waveform diagram illustrating an operation of a conventional digital information reproducing device.

[Explanation of symbols]

Reference Signs List 1 optical disk 2 optical head 3 preamplifier 4 EQ 5 A / D converter 6 maximum likelihood decoder 7 comparator 8, 29 phase comparator 9, 31 LPF 10, 30 VCO 11, 11A, 11B branch metric calculation means (BM
U) 11a Absolute value calculator 11b Square calculator 11c Subtractor 12 Addition comparison selection calculation means (ACS) 12a Adder 12b Comparator 12c Selector 12d Register 13 Survival path detection means (SMU) 14 Smoothing means (LPF) 15 Shift register (REG) 16, 19, 26 A / D conversion means 17, 21, 27 Maximum likelihood decoding means 18, 22, 28, 28A, 28B Timing signal extraction means 20 D / D conversion means 23 Band limiting means 24 Frequency setting Means 25 Time measuring means 32 Selector circuit 33, 37 Band limiting circuit 34 D / A converter 35 Counter circuit 36 Phase shift circuit 38 Variable amplifier 39 Counter circuit

Continuation of the front page (56) References JP-A-4-232668 (JP, A) JP-A-7-287937 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20 / 10-20/18

Claims (11)

(57) [Claims] A recording code having a minimum polarity inversion interval of 3 or more.
A digital information reproducing apparatus for reproducing original digital information recorded on a recording medium by using a constant , a, b, c, and d as arbitrary constants, k as an integer, and T as
When the period of the timing signal is set, the impulse response h (t) of the recording / reproducing system is expressed as follows. Partial response that performs waveform shaping to satisfy
It means a quantization means for performing quantization using said timing signal
And the partial response equalizing means and the quantizing means.
Based on the reproduced signal processed by the stage,
1) and the minimum polarity reversal interval .
From the state transition obtained from
A digital information reproducing apparatus , comprising: maximum likelihood decoding means for reproducing original digital information. 2. The method according to claim 1, wherein a is equal to d, and b is
2. The digital of claim 1, wherein c is equal to c.
Information playback device . 3. The maximum likelihood decoding means sets the constraint according to the expression (1) and the minimum polarity inversion interval.
Based on the above restrictions, an operation relating to the cumulative addition of the absolute value of the difference between the amplitude information of the reproduced signal and the expected amplitude is performed , and the maximum likelihood state transition sequence is obtained using the operation result to decode the original digital information. 3. The digital information reproducing apparatus according to claim 1, wherein 4. The maximum likelihood decoding means sets the constraint by the equation (1) and the minimum polarity inversion interval.
Based on the above restrictions, an operation relating to the cumulative addition of the square of the difference between the amplitude information of the reproduced signal and the expected amplitude is performed , and the maximum likelihood state transition sequence is obtained using the operation result to decode the original digital information. 3. The digital information reproducing apparatus according to claim 1, wherein 5. The maximum likelihood decoding means holds the operation result as a difference in the likelihood of each state.
The digital information according to claim 3 or 4, wherein
Playback device . 6. comprising a timing signal extracting means for supplying the extracted and the quantization hand <br/> stage the timing signal from the phase error information output from the maximum likelihood decoding means, said maximum likelihood decoding means Before the expected amplitude of the reproduced signal.
Generating the phase error information .
6. The digital information reproducing apparatus according to claim 5. 7. comprising a timing signal extracting means for supplying to said quantization means extracts said timing signal by using the phase error information output from a predetermined clock and the maximum likelihood decoding means, the maximum likelihood decoding The means is configured to calculate a value of
Generating the phase error information .
6. The digital information reproducing apparatus according to claim 5. 8. The timing signal extracting means includes: a phase comparator for comparing a phase of the predetermined clock with a VCO output; an LPF for band-limiting an output signal of the phase comparator; A band limiting circuit that limits the phase error information to a required band component, a selector that inputs the output of the LPF and the output of the band limiting circuit, and switches the output by a gate signal indicating the start of the timing signal extraction operation A center frequency control signal, and controlling the frequency based on the output of the selector circuit to generate the VCO output;
Are those comprising the VCO providing the A / D converting means the VCO output as said timing signal, a counter circuit for measuring the time until the current from the time when the gate signal becomes effective, and the counter circuit 8. The digital information reproducing apparatus according to claim 7, wherein a frequency characteristic of said band limiting circuit and a transfer function of said VCO are changed according to the output of said digital information reproducing apparatus. 9. The timing signal extracting means delays the predetermined clock based on a phase control signal.
So, a phase shift circuit for outputting a clock obtained by the delay as said timing signal, said a band limiting circuit which limits the signal components necessary phase error information from the maximum likelihood decoding means, an output signal of the band limiting circuit A variable amplifier that variably amplifies and outputs to the phase shift circuit as a phase control signal, and a timing signal from the phase shift circuit is input, and from the time when the gate signal indicating the start of the timing signal extraction operation becomes valid A counter circuit for measuring a time up to the present, wherein an output of the counter circuit changes a frequency characteristic characteristic of the band limiting circuit and an amplification factor of the variable amplifier. 8. The digital information reproducing device according to 7 . 10. comprising a timing signal extracting means for extracting the timing signal from the initial phase information and the initial frequency information that defines the phase error information as well as pre-output from the maximum likelihood decoding means, said maximum likelihood decoding means, Before the amplitude expected value of the reproduction signal
The quantization means generates the phase error information, and the quantization means A oversamples the signal at a constant clock cycle.
/ D conversion means, and a signal sampled by the A / D conversion means.
D / D converter for resampling with the timing signal
Any of claims 1 to 5, characterized by comprising a stage, a
One wherein the digital information reproducing apparatus according. 11. A timing signal extracting unit, comprising: a band limiting unit for limiting the phase error information from the maximum likelihood decoding unit to a required signal component; and controlling the phase error information band-limited by the band limiting unit. and frequency setting means for oscillating said timing signal as a voltage, and inputs the timing signal from the frequency setting means to measure the time up to the present from the time the gate signal indicating the start became effective extraction operation of the timing signal A time measuring unit, wherein the output of the time measuring unit changes a frequency characteristic of the band limiting unit and a transfer function of the frequency setting unit, and switches a timing signal in an initial operation and a steady operation. The digital information reproducing apparatus according to claim 10, wherein: