JP3288371B2 - Random access memory or electronic device and method of manufacturing the same - Google Patents

Description

The present invention relates to a structure of an electronic device having a unit cell including one transistor and one capacitor and a method of manufacturing the same.
In particular, a random access memory (hereinafter abbreviated as RAM) having a memory cell of one transistor and one capacitor type (hereinafter abbreviated as 1TrlC type) and a high-speed, high-density dynamic random access memory (hereinafter abbreviated as DRAM) The present invention relates to a device structure and a manufacturing method thereof.

<Prior Art> Conventionally, a high-density DRAM having an lTrlC type memory cell has been widely used because it has few components and the cell area can be easily miniaturized. In recent years, DRAMs have been pursued with higher densities and smaller elements have been required. However, lTrlC
In the type memory cell, the capacitance of the memory cell must be reduced as much as possible in order to prevent destruction of stored information or maintain the ease of information determination. Therefore, as a conventional technique, a groove is formed in a semiconductor substrate, the side surface of the groove is used as a capacitor portion, and the bottom surface of the groove is also used as an element isolation region. Density was being improved. For example, in the configuration shown in FIGS. 4A to 4C, a groove is formed in the p-type semiconductor substrate 51, a capacitor plate electrode 57 is buried, a capacitor is provided on a part of the groove side surface, and a channel stop element is provided on the groove bottom surface. The separation layer 53 was formed. here,
52 is an n + diffusion layer, 54 is a gate insulating film, 55 is a contact window, 56 is a word line or gate electrode, 58 is a bit line, 59
Is a capacitor insulating film, and 60 is an interlayer insulating film. The above is, for example, IEDM'84 (International Electron Device M
eeting) Technical Digest PP.236-239
Has been stated.

<Problem to be Solved by the Invention> In the conventional configuration, there is a problem that the memory of the memory cell is destroyed by the leak current in the groove side surface portion 61 immediately below the transfer gate. Forming a high-concentration diffusion layer for channel stop on the side surface adversely affects the electrical characteristics of the transfer gate. For example, a phenomenon that hinders the miniaturization of elements, such as an increase in channel width dependence and an increase in substrate bias dependence. I was In the example shown in FIG. 4, although the memory cell area can be reduced, the ratio (aspect ratio) of the groove depth to the opening is, for example, as shown in FIG. 4 (d). When the (Si oxide film thickness conversion) was 100 °, the value was extremely large, such as about 5 / 0.8 = 6.25, and when it was 150 °, about 8 / 0.8 = 10, which was accompanied by manufacturing difficulty. The present invention has been made in view of such a problem, and has a high leakage current-free and easy to miniaturize the element, as well as greatly reducing the difficulty in manufacturing as compared with the conventional configuration. This is to provide a new device structure that is advantageous for high-density and high-speed operation.

<Means for Solving the Problems> In the RAM of the present invention, a large number of memory cells are arranged in a hexagonal shape in a two-dimensional planar shape, and the planar shape of the 1Tr1C type memory cell is changed to a hexagonal shape. , A bit diffusion region is provided at the center of the hexagon,
It is characterized by comprising a transfer gate, a charge storage capacitor and an inter-cell insulating region. Further, a groove is formed by digging the substrate at regular intervals along an outer periphery having a hexagonal planar shape, and at least a high-concentration impurity region of a conductivity type opposite to that of the substrate is provided on one side surface of the groove. Subsequently, a thin insulating film (for example, 50-500 °) for a capacitor is formed. On the other hand, a high-concentration impurity region of the same conductivity type as the substrate is provided on the bottom surface of the groove, and this is used as an inter-cell insulating portion that contributes to electrical isolation between memory cells.
In addition, similarly to the side surface of the groove, an insulating film is also formed on the bottom surface of the groove, and then the groove portion is buried with a low-resistance material such as Doped-poly-Si. It is characterized in that it is configured as a field plate of an inter-insulation section.

<Operation> The present invention is free from the conventional problems due to the above configuration. That is, the major difference between the conventional technology and the structure of the present invention is that in the conventional structure, the bit diffusion region or the drain region is formed by both the load line or the gate electrode and the groove side surface or the channel stop diffusion region on the groove side surface. In the above configuration of the present invention, the bit diffusion region or the drain diffusion region is surrounded only by the gate electrode via the insulating film. It is in. Therefore, the former involves a leak current accompanying the vicinity of the groove side just below the transfer gate, or increases the channel width dependence on the electrical characteristics of the transfer gate by forming a channel stop impurity layer on the groove side to prevent this. There has been an adverse effect on miniaturization of element elements such as an increase in bias dependency. On the other hand, in the present invention, the periphery of the plane of the bit diffusion region is surrounded by the gate electrode alone, so that it is free from the leak current. According to the present invention, in addition to the above-described structure, the planar shape of the memory cell is made hexagonal, and its components are concentrically arranged from the center of the hexagon toward the periphery, and the bit diffusion region → transfer gate → capacitor → element insulating portion. This is characterized in that they are arranged, and furthermore, a capacitor and an element insulating portion are formed on the side and bottom surfaces of the groove, respectively. By doing so, 1) the area of the element insulating portion was minimized. The element insulating portion is generally located around the memory cell, but the regular hexagonal planar shape is one of the shapes without gaps that can minimize the peripheral length. 2) Since the planar area of the capacitor is substantially zero and the capacitor is provided on the outermost peripheral side next to the element insulating portion, the peripheral length is longer.
The groove depth can be made smaller than the required actual capacitor area. 3) By arranging the bit diffusion region or the drain diffusion region at the center of the memory cell, the area can be minimized, and the capacitance associated with the bit line can be minimized. This is advantageous for high-speed access of cell information.

Embodiment An embodiment of the present invention is shown in FIGS. 1 and 2 (a). FIG. 1 schematically shows a plan configuration of a memory cell array according to one embodiment of the present invention, and FIG. 2 (a) is AA 'of FIG.
It is a line sectional view. For ease of explanation, the same components will be described with common numbers. Here, 1 is a p-type semiconductor substrate, 2 is an n-type impurity diffusion layer (source and drain of a transfer gate and a charge storage electrode of a capacitor),
2 'is an n ^{+ -type} impurity diffusion layer (bit diffusion region), 3 is a p ^{+ -type} impurity diffusion layer (channel stop at the bottom of the trench), 4 is a gate insulating film, 6 is a gate electrode or word line, and 7 is a trench. A low-resistance material such as Doped-poly-Si or policyide (a plate electrode of a trench side capacitor and a field plate of a trench bottom element isolation portion) used for embedding, 8 is a beat line formed of Al or the like, and It is electrically connected to the n ^{+ -type} impurity diffusion layer via the contact window 5. Reference numeral 9 denotes a capacitor insulating film constituting a trench side surface capacitor, and reference numeral 10 denotes an interlayer insulating film formed of SiO ₂ or the like. Here, the transfer gate electrode 6 completely concentrically surrounds the contact window 5 and the bit diffusion region or the drain region 2 ′, 2 in a plane and concentrically. Here, an example of the manufacturing method of the present embodiment will be briefly described. After forming a groove 7 'in the p-type substrate 1 by RIE or the like, an n-type impurity layer 2 is formed on the side surface of the groove by ion implantation or the like. Next, only the groove bottom is etched by RIE or the like so that an n-type impurity layer is not formed on the groove bottom. The capacitor insulating film 9 in the groove side, after forming the insulating film for element isolation in the trench bottom, by ion implantation only in the groove bottom portion, to form a p ⁺ -type diffusion layer 3. Then 'After moderately etched back embedded in low-resistance material such as Doped-poly-Si or Policide, flattened 10 by further buried etch back or the like of the interlayer insulating film such as SiO _2' groove 7 to form a. Next, in a normal process, a gate oxide film 4 is formed, and a word line 6 is formed.
The drain n-type diffusion layer 2 is formed by ion implantation or the like. After that, an interlayer insulating film 10 is deposited by CVD or the like, a contact window 5 is formed by etching, an n ⁺ impurity layer 2 ′ is formed by ion implantation or the like, and then the bit line 8 is formed of a normal resistance material such as Al. It is formed by a process. FIG. 2B is a schematic view of a cross-sectional structure showing another embodiment of the present invention. The difference from FIG. 2A is that a p-type low-concentration impurity layer 1 ″ formed by epitaxial growth or the like is formed on a p ^{+ -type} high-concentration substrate 1 ′ instead of the p-type substrate. And the channel stop 3 of the p ^{+ -type} diffusion layer and the process thereof are omitted. The other components are the same and will not be described.

<Effect of the Invention> FIG. 3 shows the results of the embodiment of the present invention described above. This shows the relationship between the depth of the trench (trench) formed around the memory cell and the cell capacitance (Cs). Compared with FIG. 4 (d) of the prior art,
In the case of Tox = 100 °, the conventional technique requires a depth of about 5 μ for almost the same memory cell area, whereas in the present embodiment, it may be about 2 μ, and in the case of Tox = 150 °, Approximately 2.5 μm, which is about 8 μm, and about 3 μm in this embodiment. Further, as described above in comparison with the prior art, the present invention can significantly reduce manufacturing difficulties in addition to leak current free and easy miniaturization of elements associated with an inter-cell insulating portion and a transfer gate. It is possible to realize a RAM which is advantageous for high-density and high-speed operation.

As described above, the description of the present invention is limited to the RAM, but it is needless to say that the present invention is applicable to all electronic elements or electronic devices including 1Tr1C type memory cells.
Also, while embodiments of the method and apparatus of the present invention have been disclosed in connection with a particular semiconductor memory structure, many changes in detail may be made as a result of technical selection without departing from the spirit of the invention. It should be understood that

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a memory cell in one embodiment of the present invention, FIGS. 2 (a) and 2 (b) are cross-sectional views taken along the line AA 'of FIG.
FIG. 3 shows a cell capacitance (Cs) -groove (trench) depth characteristic of the present invention. 4 (a)-(d) show the prior art, FIG. 4 (a) is a schematic plan view,
(B) is a schematic perspective view, and FIG. 4 (c) is a in FIG. 4 (a).
FIG. 4D is a schematic cross-sectional view taken along line −a ′, showing cell capacitance (Cs) -groove (trench) depth characteristics. 1 ... Semiconductor substrate, 1 '... High-concentration semiconductor substrate, 1 "... Low-concentration impurity layer, 2 ... N-type impurity layer (source, drain, storage electrode for cell capacitor), 2' ... N ^{+ type} Impurity layer (bit diffusion region), 3 ... p ⁺ impurity layer, 4 ... Gate insulating film, 5 ... Contact window, 6 ... Gate electrode or word line, 7 ... Cell capacitor plate electrode, 8 ... Bit line, 9 ... Capacitor insulating film, 10 ... Interlayer insulating film.

Claims (24)

(57) [Claims] A plurality of unit cells each having a regular hexagonal planar shape are densely arranged on a substrate. The unit cell includes a transistor and a capacitor. A random access device having at least a part of a boundary between the element isolation region and the capacitor region to be electrically separated and parallel to a current flow in a channel region of the transistor;
Memory or electronic device. 2. A plurality of unit cells each having a regular hexagonal planar shape are densely arranged on a substrate, and
In a wiring method of a bit line in a cell array in which a plurality of the unit cells are integrated, the bit lines may be formed by connecting the unit cells through contacts formed in the form of a regular hexagon. Characteristic random access memory or electronic device. 3. The electronic device according to claim 1, wherein the bit lines connect the unit cells that are not adjacent to each other. 4. The unit cell includes at least one transistor.
4. A random access memory or electronic device according to claim 2 or 3, including a capacitor element. 5. A unit cell comprising: a bit diffusion region provided at the center of the regular hexagon on the surface of the substrate; and a transfer gate, a charge storage capacitor, and a device isolation region arranged in order on the outer periphery of the bit diffusion region. Each has a continuous,
Further, the unit cell includes a part of a trench having a width in a cell array, dug along a periphery of the regular hexagon on a surface of the substrate; and forming the trench as one electrode of the charge storage capacitor. An impurity diffusion layer of a conductivity type opposite to that of the substrate formed on the side surface of the substrate; a capacitor insulating film formed adjacent to the impurity diffusion layer; A heavily doped region of the same conductivity type as the substrate, formed as a part of the element isolation region contributing to the optical isolation; an isolation insulating film formed adjacent to the heavily doped region; The trench bottom field plate of the element isolation region and the other electrode of the charge storage capacitor are filled with the trench and flattened, and the capacitor insulating film and the doped polysilicon formed on the isolation insulating film, for example. The low resistance material, such as etc .; include the unit paragraph following claims, including cell or paragraph 2 or 3 or a random access memory or electronic apparatus paragraph wherein. 6. A method of manufacturing a random access memory or an electronic device, comprising: (a) forming a trench (groove) by etching in a p-type substrate; (b) forming an n-type impurity layer on a side surface of the trench by a first step. (C) etching the bottom of the trench to remove a portion of the n-type impurity layer from the bottom of the trench; (d) the n-type impurity layer on the side surface of the trench Forming a capacitor insulating film adjacent to the trench and an element isolation insulating film adjacent to the bottom of the trench; (e) forming a p ⁺ -type diffusion layer through the device isolation insulating film at the bottom of the trench; f) filling the trench with a low-resistance material as a second capacitor electrode; (g) forming a first interlayer insulating film on the low-resistance material for planarization; (h)
Forming a gate insulating film on a part of the surface of the substrate;
(I) forming a gate electrode or a word line on the gate insulating film and the first interlayer insulating film; (j) forming an n-type diffusion layer as a source or a drain; Forming an insulating film on the word line and the n-type diffusion layer; (l) forming a contact window reaching the n-type diffusion layer through the second interlayer insulating film; (m) the n-type diffusion Forming an n ⁺ -type impurity layer as a bit diffusion region in the layer; and (n) forming a bit line made of a low-resistance material on the second interlayer insulating film and reaching the bit diffusion region through the window. A method of manufacturing a random access memory or an electronic device. 7. A method of manufacturing a random access memory or an electronic device, wherein: (a) forming a p-type epitaxial layer on a p ⁺ -type impurity layer formed on a substrate; (b) said p-type epitaxial layer etching the bottom of the (d) the trench; forming a n-type impurity layer on the side surface of the (c) the trench as the first capacitor electrode; and after the step of forming by etching a trench reaching the p ⁺ -type impurity layer Removing a part of the n-type impurity layer from the bottom portion by using the method;
(E) forming a capacitor insulating film on the n-type impurity layer on the side surface of the trench and an element isolation insulating film on the bottom of the trench; (f) using the trench as a second capacitor electrode (G) forming a first interlayer insulating film on the second capacitor electrode and flattening; (h) forming a gate insulating film on a part of the surface of the substrate (I) forming a gate electrode or a word line on the gate insulating film and the first interlayer insulating film;
(J) a step of forming an n-type diffusion layer as a source or a drain; (k) a step of forming a second interlayer insulating film on the word line and the n-type diffusion layer; (l) the second interlayer insulating film Forming a contact window reaching the n-type diffusion layer through
(M) forming an n ⁺ -type impurity layer as a bit diffusion region in the n-type diffusion layer; and (n) a low-resistance material reaching the bit diffusion region through the window on the second interlayer insulating film. Forming a bit line consisting of: a method for manufacturing a random access memory or an electronic device. 8. The unit cell includes a bit diffusion region provided at the center of the regular hexagon on the surface of the substrate, and a transistor (transfer gate) and a capacitor (charge) arranged sequentially on the outer periphery of the bit diffusion region. Storage capacitor) and an element isolation region, each being continuous.
The first or second or third or third aspect, wherein the periphery of a plane of the bit diffusion region or the source or drain diffusion region of the transistor is surrounded by only a gate electrode of the transistor via an insulating film. A random access memory or electronic device according to claim 4. 9. A unit cell including at least one transistor and one capacitor element, wherein said unit cell is a substrate of one conductivity type, each of which is densely arranged on a plurality of said unit cells having a planar shape of a regular hexagon. A first diffusion layer provided at the center of the regular hexagon on the surface of the substrate; the transistor, the capacitor, and the second diffusion layer which are sequentially arranged on the outer periphery of the first diffusion layer; The unit cell having a trench having a certain width in a cell array in which a large number of the unit cells are densely formed, dug along the outer periphery of the regular hexagon on the surface of the substrate; Part); a third diffusion layer formed on one side of the trench as one electrode of the capacitor; a first insulating film formed adjacent to the third diffusion layer; On the bottom surface, connect between adjacent unit cells The second diffusion layer; a second insulation film formed adjacent to the second diffusion layer; and filling and flattening the trench to cover the first insulation film and the second insulation film. A random access memory or an electronic device including the unit cell, comprising: a low resistance material such as, for example, doped polysilicon formed on the substrate; 10. The random access memory or electronic device according to claim 9, wherein said first diffusion layer is of a conductivity type different from said one conductivity type. 11. The random access memory or electronic device according to claim 10, wherein said second diffusion layer is of the same conductivity type as said one conductivity type. 12. The random access memory or electronic device according to claim 11, wherein said third diffusion layer is of a conductivity type different from said one conductivity type. 13. A large number of bit lines interconnect a large number of said unit cells in a row direction, and a large number of word lines intersect said bit lines in a column direction via an insulating film to interconnect said large number of said unit cells. A random access memory or an electronic device according to any one of claims 1 to 5 or 8 to 12, which claims. 14. The random access memory or electronic device according to claim 13, wherein said word line is the same as or connected to a gate electrode of said transfer gate or said transistor. 15. The random access memory or electronic device according to claim 14, wherein said bit line is connected to said bit diffusion region or said first diffusion layer. 16. A trench along a periphery of a regular hexagon on a surface of a substrate having a cell array in which a plurality of unit cells each having a regular hexagonal planar shape are densely arranged on the substrate.
Forming a second insulating film at least in a region including a bottom surface of the groove; forming a first insulating film in a region including at least a side surface of the groove; Forming two or more capacitors in which at least one electrode is electrically separated at the bottom of the groove by forming a low-resistance material adjacently, in a region including at least a side surface of the groove. A method for manufacturing a random access memory or an electronic device. 17. The number of wirings per unit cell is one for the word line or two for the beat line or one for the word line and one for the bit line. 16. The random access memory or electronic device according to claim 13, wherein the number of connections is one for the word line and one for the bit line. 18. The method according to claim 17, wherein said adjacent bit lines are formed in different layers via an interlayer insulating film. An electronic device or a random access memory according to claim 15. 19. A random access memory or electronic device comprising a cell array in which a plurality of unit cells are densely arranged on a substrate, wherein a trench is formed along an outer periphery of the unit cell of the substrate. In the manufacturing method, (a) a step of forming the trench (groove) in the one-conductivity-type impurity layer of the substrate by etching; (b) a step of forming a two-conductivity-type impurity layer on a side surface of the trench as a first capacitor electrode; And (c) etching the bottom of the trench to remove a part of the impurity layer of the two conductivity type from the bottom of the trench. Method. 20. The method for manufacturing a random access memory or an electronic device according to claim 19, wherein said one conductivity type and said two conductivity types are different conductivity types from each other. 21. The method according to claim 19, wherein the width of the trench is formed larger than the width of the cell array in the outermost periphery in the cell block in which a large number of the unit cells are integrated. 21. A method for manufacturing a random access memory or an electronic device according to item 20 or 20. 22. An electronic device or a random access memory according to claim 1, wherein said electronic device is a one-transistor one-capacitor random access memory. Manufacturing method of memory or random access memory or electronic device. 23. The method for manufacturing a random access memory or an electronic device according to claim 16, wherein said regular hexagon is a hexagon. 24. A method according to claim 1, wherein said regular hexagon is a hexagon. A random access memory or an electronic device according to any of the claims 22.