JP3278764B2 - Delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal delay circuit built in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a configuration of a conventional delay circuit. An input signal IN is input from an input terminal 1 and inverted by an inverter 2. The inverted signal is supplied to one end of a resistor 3. A capacitor 4 is connected between the other end of the resistor 3 and a ground potential. A connection point a between the capacitor 3 and the capacitor 4 has a waveform formed by connecting two ends of a P-channel field-effect transistor 9 as a positive switch element and an N-channel field-effect transistor 10 as a negative switch element. It is input to a shaping circuit (inverter) 12. Also,
The other end of the P-channel field-effect transistor 9 is connected to the power supply terminal 7, the other end of the N-channel field-effect transistor 10 is grounded, and the output b point of the waveform shaping circuit 12 is connected to the inverter 13 , 14 and an output terminal 15 from which an output signal O is output.
The UT is output. The delay time of this delay circuit is determined by the resistance 3
And the time constant according to the value of the capacitor 4 and the logic threshold voltage Vth of the waveform shaping circuit 12.

FIG. 5 is a timing chart of a voltage waveform and a current waveform of the circuit of FIG. The operation of the circuit of FIG. 4 will be described below with reference to FIG. When the input signal IN from the input terminal 1 changes from the low level to the high level at the timing of the time t1, the output of the inverter 2 changes from the high level to the low level, and the potential Va at the point a becomes the resistance 3 and the capacitance 4 , And begins to descend in a discharge curve according to the time constant. When the discharge curve of Va becomes equal to or lower than the logical threshold voltage Vth of the waveform shaping circuit 12 at the timing of the time t2, the output at the point b of the waveform shaping circuit 12 changes from the low level to the high level. The output signal OUT is output through the output terminal 15 and changes from a low level to a high level.

Similarly, when the input signal IN from the input terminal 1 changes from the high level to the low level at the time t3, the output of the inverter 2 changes from the low level to the high level, and the potential Va at the point a becomes The charging curve corresponding to the time constant of the resistance 3 and the capacity 4 starts to rise, and rises at time t4.
When the voltage Va reaches the logical threshold voltage Vth of the waveform shaping circuit 12 at the timing of the above, the output point b of the waveform shaping circuit 12 changes from the high level to the low level, and the output signal OUT also changes from the high level to the low level. . The point b current shown in FIG. 5 indicates a through current flowing through the waveform shaping circuit 12, and
The power supply current indicates the current consumption of the entire circuit shown in FIG.

However, in the conventional circuit shown in FIG.
The potential Va at the point a, which is an input to the waveform shaping circuit 12, is a resistor 3
Charge and discharge with the time constant of the capacitor 4 and the capacitor 4, there is a drawback that the through current continues to flow for a while even after the output is inverted, and the waveform shaping circuit 1 near the logical threshold voltage Vth.
Since the gain of No. 2 is high, there is a problem that the output is easily influenced by noise even after the output is inverted once.

FIG. 6 shows another conventional signal delay circuit and FIG. 7 shows a timing chart thereof (see JP-A-6-296123). The circuit shown in FIG.
In comparison with the circuit of FIG.
7, the delay output is fed back, and when the output changes at the timing of time t12 shown in the timing chart of FIG. 7, the output is forced as shown in the waveform of the signal S23 at the connection point between the resistor 22 and the capacitor 24. Signal S
23, the through current flowing through the inverter 23 is suppressed, and similarly, the potential of the signal S23 is forcibly pushed down at the timing of the time t14, whereby the inverter 2
3 is reduced.

However, in the example of FIG. 6, the problem of the conventional example of FIG. 4 is solved, but the connection point indicated by the signal S23 swings out of the power supply voltage range as is apparent from FIG. Therefore, if you try to configure on an integrated circuit,
Unnecessary current flows to the power supply and the board due to the parasitic diode,
There has been a problem that there is a risk of latch-up and a cause of noise.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is an object of the present invention to provide a delay circuit which suppresses the risk of latch-up and noise, and reduces the through current and power consumption. With the goal.

[0009]

According to the first aspect of the present invention,
Delay the input signal using the time constant of resistance and capacitance and output
In the delay circuit, the rise of the input signal, delay means for delaying is raised or lowered in accordance with each of the falling time constant of the resistor and the capacitor, and a waveform shaping circuit for shaping the output waveform of the delay means , When on
Supplying power to the waveform shaping circuit and turning off the waveform shaping circuit
Switch means for stopping supply of power to the power supply, and the output waveform of the delay means reaches a logic threshold voltage of the waveform shaping circuit, and immediately after the output of the waveform shaping circuit changes, the switch means is turned off and the waveform is turned off. And control means for turning off a through current of the shaping circuit.

[0010] According to the second aspect of the present invention, the time constant of the resistance and the capacitance is determined.
Delay circuit that delays an input signal using
The rising and falling edges of the input signal.
Is raised or lowered according to the time constant of the resistance and capacitance.
Delay means for adjusting the output waveform of the delay means.
A waveform shaping circuit, and the waveform between a power supply terminal and GND.
First and second switches connected in tandem with the shape shaping circuit.
And a waveform shaping circuit for outputting the output waveform of the delay means.
, And the output of the waveform shaping circuit is
Immediately after changing from the first level to the second level, the first
Of the second level to the first level.
Immediately after changing to the bell, the second switch means is turned off.
Control means for turning off the through current of the waveform shaping circuit
And a delay circuit comprising:

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a delay circuit according to one embodiment of the present invention. In this figure, the input terminal 1 is connected to the input of the inverter 2, the input of the NOR gate 5, and the input of the NAND gate 6, the output of the inverter 2 is connected to one end of the resistor 3, and the other end of the resistor 3 is connected to the capacitor. 4 and one end of the capacitor 4 is grounded. Further, between the power supply terminal 7 and GND, P-channel field effect transistors 8 and 9 as positive switching elements are provided.
And N-channel field-effect transistors 10 and 11 as negative switch elements are cascaded, and the P-channel field-effect transistor 9 and the N-channel field-effect transistor 10 at this time are configured as a waveform shaping circuit 12. . Further, the output of the NOR gate 5 and the gate of the P-channel field effect transistor 8 are connected to form a NAND
The output of the gate 6 and the gate of the N-channel field effect transistor 11 are connected. Also, a resistor 3 and a capacitor 4
The gate of the P-channel field-effect transistor 9 and the gate of the N-channel field-effect transistor 10 are connected to a point a, which is a connection point. Further, the input of the inverter 13 is connected to the output point b of the waveform shaping circuit 12, the input of the inverter 14 is connected to the output of the inverter 13,
The output of the inverter 14 is connected to the input of the NOR gate 5,
The input of the ND gate 6 and the output terminal 15 are connected.

Next, the operation of the delay circuit having the above configuration will be described with reference to FIG. At the timing of the time t0, the input signal IN from the input terminal 1 is at a low level, and therefore, at a point a, is at a high level via the inverter 2.
As a result, the P-channel field effect transistor 9 is turned off, and the N-channel field effect transistor 10 is turned on. Since the low level is also input to the input of one end of the NAND gate 6, the output of the NAND gate 6 is also at the high level. As a result, the N-channel field effect transistor 11 is turned on, and the waveform shaping circuit 12 is grounded. From the above, the output at the point b of the waveform shaping circuit 12 becomes low level,
The output signal OUT of the output terminal 15 output via the
Low level is determined. At this time, since the low level is also input to the input of one end of the NOR gate 5, the NOR end is input to the other end together with the low level input from the input terminal 1.
The high level of the output of the gate 5 is also determined, and the P-channel field effect transistor 8 is turned off. Therefore, the waveform shaping circuit 12 is disconnected from the power supply terminal 7, so that even if noise or the like enters the point a, a through current does not flow through the waveform shaping circuit 12, and the low level is output from the output terminal 15 stably. Is done.

Next, when the input signal IN of the input terminal 1 changes from low level to high level at the timing of the time t1, one end of the input of the NOR gate 5 changes to high level, so that the output of the NOR gate 5 becomes high. Change from level to low level. As a result, the P-channel field effect transistor 8 is turned on and connected to the power supply terminal 7, and the potential Va at the point a becomes

(Equation 1) However, since VDD is the power supply voltage, CR is the time constant of the resistor 3 and the capacitor 4, and t is the time after the input has changed, the discharge curve begins to fall, and the output terminal 15 remains at the low level. The output of the NAND gate 6 also remains at the high level, and the grounded N-channel field effect transistor 11 is kept on. Therefore, the P-channel field-effect transistor 8 and the N-channel field-effect transistor 11 are on until the time t2 when the potential Va at the point a reaches the logic threshold voltage Vth of the waveform shaping circuit 12, so that the waveform The power is supplied to the shaping circuit 12 to be in an active state, and the output at the point b of the waveform shaping circuit 12 maintains a low level until the potential Va at the point a becomes equal to or lower than the logic threshold voltage Vth of the waveform shaping circuit 12.

However, when the potential Va at the point a reaches the logic threshold voltage Vth of the waveform shaping circuit 12 at the time t2, the output at the point b of the waveform shaping circuit 12 is inverted to a high level, and the output terminal 15 Outputs a high level, but at the same time, the output of the NAND gate 6 is also determined to be low, and the N-channel field effect transistor 11 is turned off. As a result, the waveform shaping circuit 12 is disconnected from the GND side so that no through current flows, and a high level is stably output from the output terminal 15.

Next, at the timing of time t3, when the input signal IN of the input terminal 1 changes from the high level to the low level, the low level is also input to the input of one end of the NAND gate 6, so that The output changes from low level to high level. As a result, the N-channel field effect transistor 11 is turned on, and the potential Va at the point a becomes

(Equation 2) However, since VDD is the power supply voltage, CR is the time constant of the resistor 3 and the capacitor 4, and t is the time after the input change, the charging curve starts to rise, and the output terminal 15 remains at the high level. The output of the NOR gate 5 maintains the low level, and the P-channel field effect transistor 8 maintains the ON state. Therefore, the potential Va at the point a
Until the time t4 when the signal reaches the logic threshold voltage Vth of the waveform shaping circuit 12, the P-channel field-effect transistor 8 and the N-channel field-effect transistor 1
1 is in the ON state, the power is supplied to the waveform shaping circuit 12 again, and the waveform shaping circuit 12 becomes active.
The point output is maintained at a high level until the potential Va at the point a becomes equal to or higher than the logical threshold voltage Vth of the waveform shaping circuit 12.

However, when the potential Va at the point a reaches the logic threshold voltage Vth of the waveform shaping circuit 12 at the timing of the time t4, the output at the point b of the waveform shaping circuit 12 is inverted to a low level, and at the same time, the NOR gate 5 The high level of the output is determined, and the P-channel field effect transistor 8 is turned off. Thereby, the power supply terminal 7 of the waveform shaping circuit 12
And the through current stops flowing, and a low level is stably output from the output terminal 15. Hereinafter, the state of the above-mentioned times t0 to t4 is repeated.

As described above, in the delay circuit according to the embodiment of the present invention, the voltage Va at the point "a" swings out of the range of the power supply voltage as in the example described in Japanese Patent Application Laid-Open No. 6-296123. There is no such thing as. As a result, there is an advantage that a highly reliable delay circuit that suppresses the possibility of latch-up and the generation of noise can be obtained. Further, except for the period until the input signal changes and the output signal changes, either the switch element on the power supply terminal side or the switch element on the GND side is turned off, and the potential Va at the point a has an intermediate potential. There is an advantage that a through current does not flow through the shaping circuit and power consumption can be reduced. In particular, depending on the time constant of the circuit, the power consumption of the waveform shaping circuit can be reduced to less than half. For example, in the delay circuit of FIG. 1 of the present invention and the delay circuit of FIG.
(KΩ) and simulation waveforms when the capacitance is 10 (pF) are shown in FIG. 2 and FIG. 5, respectively. Looking at the point b current, which is a through current of each waveform shaping circuit, the conventional example (FIG. 5) In contrast to 11 (μA), in the embodiment of the present invention (FIG. 2), it can be reduced to 4 (μA).

FIG. 3 shows another embodiment of the present invention.
Now, the waveform shaping circuit 12, the P-channel field-effect transistor 8, and the N-channel field-effect transistor 11
Although the order of the tandem connection is changed, the same effect as in the above embodiment can be obtained even in such a connection state.

[0019]

According to the present invention, the switching means is connected in series to the waveform shaping circuit, and the switching means is turned off immediately after the output of the waveform shaping circuit changes, so that a through current flowing through the waveform shaping circuit is obtained. Therefore, the effect of suppressing generation of noise and reducing power consumption can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a delay circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing waveforms of respective parts of the delay circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a delay circuit according to another embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a delay circuit according to a conventional technique.

5 is a diagram showing waveforms of respective parts of the delay circuit shown in FIG.

FIG. 6 is a circuit diagram showing another configuration of the delay circuit according to the related art.

7 is a diagram showing waveforms of respective parts of the delay circuit shown in FIG.

[Explanation of symbols]

 1. Input terminal 2. Inverter 3. Resistance 4. Capacity 5. NOR gate 6. NAND gate 7. Power supply terminal 8,9. P-channel field effect transistor 10, 11. 11. N-channel field effect transistor Waveform shaping circuit 13,14. Inverter 15. Output terminal

Claims (2)

(57) [Claims] An input signal is obtained by using a time constant of a resistance and a capacitance.
In the delay circuit for delaying and outputting the rising of the input signal, delay means for delaying is raised or lowered in accordance with each of the falling time constant of the resistor and capacitor, to shape the output waveform of the delay means A waveform shaping circuit, which supplies power to the waveform shaping circuit when on, and
Switch means for stopping supply of power to the waveform shaping circuit, and the switch means immediately after the output waveform of the delay means reaches a logic threshold voltage of the waveform shaping circuit and the output of the waveform shaping circuit changes. Control means for turning off the through current of the waveform shaping circuit as off. 2. An input signal is obtained by using a time constant of resistance and capacitance.
In the delay circuit for delaying and outputting the rising of the input signal, delay means for delaying is raised or lowered in accordance with each of the falling time constant of the resistor and capacitor, to shape the output waveform of the delay means a waveform shaping circuit, and the waveform shaping circuit between the power supply terminal and GND together
The output waveforms of the cascade-connected first and second switch means and the delay means reach the logic threshold voltage of the waveform shaping circuit, and the output of the waveform shaping circuit changes from the first level to the second level.
The first switch means is turned off immediately after the change to the first level, and the second switch means is turned off immediately after the change from the second level to the first level to turn off the through current of the waveform shaping circuit. Control means for controlling the delay.