JP3262747B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a heterojunction field-effect transistor using a SiGeC layer or a SiGe layer, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, high integration of semiconductor devices has been progressing. However, miniaturization of MOS type transistors has an effect of a short channel effect in a super miniaturized region where a gate length is less than 0.1 μm. It is expected that the current drive capability will be saturated due to an increase in the resistance component and the like, and the performance improvement as in the past cannot be expected. In particular, fine MOS
In order to increase the driving force of a transistor, it is important to improve the carrier mobility of the channel and reduce the resistance of the source / drain electrode contacts.

[0003] Therefore, instead of a complementary semiconductor device (CMOS device) using Si of a single composition formed on a silicon substrate, a heterostructure CMOS device (Heterostructure CMO) using a Si / SiGe system (Group IV mixed crystal) is used.
S: hereinafter abbreviated as HCMOS device). This uses a heterojunction interface made of two kinds of semiconductors having different band gaps instead of a Si / Si02 interface as a channel. Si / SiGe giving higher carrier mobility than such Si
It is expected that higher-speed devices can be realized by using a system. In the Si / SiGe system, it is possible to form an epitaxial growth layer having a desired amount of strain and a desired band gap value on a Si substrate by controlling the composition. IBM's Ismail is, Si / SiGe system of HC
(K. Ismail, "Si / SiGe High Speed Field-Effec
tTransistors ", IEDM Tech. Dig. 1995, p509. and M.
A. Armstrong et al, "Design of Si / SiGe Hetrojuncti
on Complementary Metal-Oxide-Semiconductor Transis
tors "IEDM Tech. Dig. 1995, p761.).

FIG. 15 is a sectional view showing an example of the HCMOS device. As shown in FIG.
A field effect transistor including a source / drain region 109, a gate insulating film 107, and a gate electrode 110 thereon is provided in a part of the transistor 1. The so-called channel region between the source region and the drain region below the gate electrode 110 includes the SiGe buffer layer 102, the δ-doped layer 115, and the spacer layer 1
03, i-Si layer 104, and i-SiGe layer 105
And an i-Si layer 106 are formed. In these regions, the SiGe buffer layer 102 applies tensile strain to the i-Si layer 104 to form the n-channel layer 112 between the i-Si layer 104 and the i-SiGe layer 105. . This SiGe buffer layer 10
2, the Ge composition ratio was 0 immediately above the Si substrate 101.
%, And at the top, the Ge composition ratio is 30%.
The composition ratio is changed stepwise.

When a negative bias is applied, i-
In the Si layer 104, the lower SiGe buffer layer 10
An n-channel layer 112 is formed at the hetero interface with the second. The δ-doped layer 115 supplies electrons as carriers to the n-channel layer 112 formed above. Further, the spacer layer 103 is formed on the δ formed below.
The ions of the doped layer 115 and the upper n-channel layer 112
Are spatially separated from each other to prevent a decrease in mobility due to ion scattering of carriers.

When a positive bias is applied, i-S
In the iGe layer 105, a p-channel layer 111 is formed at a hetero interface with the upper i-Si layer 106. Gate insulating film 107 is for insulating gate electrode 110 and p-channel layer 111.

As described above, the hetero field effect transistor is characterized in that a channel is formed at a hetero interface between two kinds of semiconductor layers having different band gaps. Therefore, there are at least two types of semiconductor layers having different band gaps for channel formation.
In addition, in order to form a channel through which electrons or holes move at high speed in the semiconductor layer, it is necessary to have a conduction band or a valence band discontinuity at the hetero interface. In the above-mentioned Si / SiGe system, holes are used for the SiGe layer 1
Since 05 has a discontinuity in the valence band with respect to the i-Si layer 106, a channel for holes is formed (see the left part of FIG. 15). However, since there is almost no discontinuity in the conduction band, a tensile strain is applied to the i-Si layer 104 in order to form a channel for electrons, so that the conduction band is formed at the hetero interface with the i-SiGe layer 105. (See the right part of FIG. 15).

The HCMOS device having such a structure is a conventional CCMOS using a channel of Si / Si02.
It is expected from simulation results that twice the high-speed operation can be realized with half the power consumption with the same processing dimensions as compared with the MOS device. That is, a semiconductor element in which a heterointerface is formed by combining a Si semiconductor and a SiGe mixed crystal to form a high mobility channel, and high-speed operation of an element utilizing a heterojunction and large-scale integration of a MOS device are achieved. It has attracted much attention as a compatible element.

[0009]

However, a hetero device utilizing a group IV mixed crystal such as SiGe as described above is greatly expected as a method for overcoming the performance limit of a conventional CMOS device, but is typically represented by SiGe. Be done
Hetero-field-effect transistors using Group IV mixed crystals have been delayed in research and development compared to hetero-bipolar transistors, which are hetero devices using the same SiGe mixed crystals, due to the difficulty of their manufacture, and still exhibit their expected performance. It cannot be said that possible structures and manufacturing methods have been sufficiently studied. In the case of a so-called hetero MOS structure having an insulating film between a gate electrode and a semiconductor layer as described above, a stable and good insulating film cannot be formed in the SiGe layer. An oxide film made of SiO2 is used as the film. Therefore, immediately below the gate insulating film must be a Si layer, but Si has a characteristic that the band gap is always larger than that of SiGe.

For this reason, the conventional HCMOS device has the following problems.

First, as described above, in order to form an electron channel on the Si substrate 101, the i-Si layer 104 is formed.
Is applied with tensile strain to form a band discontinuity at the Si / SiGe hetero interface. However, changing the lattice constant involves the introduction of dislocations due to lattice relaxation.

FIG. 16 is a sectional view showing the SiGe buffer layer 102 and the i-Si layer 104 thereon. Since the i-Si layer 104 has a smaller lattice constant than the SiGe buffer layer 102, tensile strain is accumulated at the stage of crystal growth. When the accumulation of the strain increases, dislocations enter the i-Si layer 104 as shown in FIG. Thus, the i-Si layer 104 and the SiG
Introduction of dislocations and defects due to lattice mismatch distortion between the e-buffer layer 102 and the e-buffer layer 102 cannot be avoided. Therefore, aside from the initial characteristics of an element using this crystal, it is considered that the influence of characteristic deterioration due to propagation of dislocations and the like will occur from the viewpoint of reliability and life.

A SiGe buffer layer 102 made of SiGe having a larger lattice constant than Si on a Si substrate 101.
Are stacked, and tensile strain is accumulated in the i-Si layer 104 grown thereon. When the thickness of the SiGe buffer layer 102 is increased, the lattice constant of the From the lattice constant to the original SiGe
Exceeds the critical thickness at which the lattice constant changes, lattice relaxation occurs, and defects such as dislocations are also introduced into the SiGe buffer layer 102.

Although these defects may have little effect on the initial characteristics of the device, they may cause serious problems from the viewpoint of long-term reliability and life. That is, there is a possibility that the propagation of defects due to the current or the deterioration due to diffusion of the metal or the impurities through the defects may occur, and the reliability may be reduced.

A first object of the present invention is to use a heterojunction that is lattice-matched or almost lattice-matched while having a band discontinuity that can form a carrier accumulation layer as a structure in a channel region below a gate of an HCMOS device. Accordingly, an object of the present invention is to provide a highly reliable semiconductor device having high carrier mobility.

Second, a hetero field effect device using a group IV mixed crystal represented by SiGe is a conventional fine CMOS.
Although it is an effective technology as an element structure that overcomes the performance limitations of the device, at the present time, studies on optimizing the contact between the source and drain electrodes are still inadequate compared to studies on improving channel mobility. It cannot be said that the structure is fully utilized. In the above-mentioned technology of hetero CMOS devices by IBM, detailed studies have been made on improving the mobility of the channel region. However, contact between source / drain electrodes, which is another important factor for improving the performance of fine transistors, is discussed. Almost no studies have been made on lowering the resistance.

That is, in the CMOS device structure using the Si single crystal, various studies have been made on the structure of the contact region on the substrate side connected to the source / drain electrodes. Optimal contact area structure and formation method
It is necessary to study whether the device structure is optimal even in hetero field effect devices having different element structures.

A second object of the present invention is to provide a semiconductor device having a contact region capable of exhibiting a small contact resistance without deteriorating the excellent characteristics of a hetero field effect device, and a method of manufacturing the same.

[0019]

According to the present invention, there is provided a semiconductor device comprising:
Formed on a part of a semi-conductor substrate comprises a field effect transistor having a gate electrode and the source and drain regions and a channel region between said source and drain regions, to the channel region, a first Si layer, the A first Si _1-xy Ge _x C _y layer formed in contact with the Si layer (0 ≦ x ≦ 1, 0 <
y ≦ 1), a second Si layer, and a second Si ₁₋ layer formed in contact with the second Si layer and having a band gap different from that of the first Si _1-xy G _x C _y layer. _xy Ge _x C _y
Layer (0 ≦ x ≦ 1,0 ≦ y ≦ 1) and is provided, the area adjacent to the first Si layer in the first Si _1-xy Ge _x C _y layer, the first 2 Si _1-xy Ge _x
First and second carrier accumulation layers for confining carriers of different conductivity types are formed in a region of the C _y layer adjacent to the second Si layer, respectively.

As a result, a semiconductor device having an n-channel field-effect transistor and a p-channel field-effect transistor each having a channel with high carrier confinement efficiency and high operation speed can be obtained. Moreover, the first Si _1-xy G
Between the e _x C _y layer and the first Si layer, can be controlled so as lattice mismatch is eliminated or extremely small, crystal defects does not enter the first Si _1-xy Ge _x C _y layer It can be configured as follows. Therefore, a highly reliable semiconductor device can be obtained.

The C composition ratio y in the second Si _1-xy Ge _x C _y layer can be set to zero.

[0022] The above formed on a semiconductor substrate, further provided more Rukoto the MOS transistor to the channel region of the semiconductor layer having a single composition, in a portion operating speed is required, the first Si _1-xy A transistor having a Ge _x C _y layer in a channel region is arranged, and in other portions,
By arranging ordinary MOS transistors, the application range of the semiconductor device can be expanded.

It is preferable that the composition ratio y of C in the first Si _1-xy Ge _x C _y layer is 0.01 to 0.03.

[0024] The composition ratio of each element of said first Si _1-xy Ge _x C _y layer, the a first Si _1-xy Ge _x C _y layer and said first Si layer are lattice-matched composition By adjusting the ratio, a semiconductor device having a highly reliable field-effect transistor without lattice distortion can be obtained.

The first Si _1-xy Ge _x C _y layer has a lattice constant smaller than that of the first Si layer and has a film thickness that does not cause lattice relaxation. it allows to join the tensile strain in the first Si _1-xy Ge _x C _y layer, it is possible to increase the amount of band discontinuity between the first Si layer, improved confinement efficiency of carrier I do.

It is preferable that the carriers accumulated in the first carrier accumulation layer be negative carriers and the carriers accumulated in the second carrier accumulation layer be positive carriers.

The first S in the first Si layer
i to _1-xy Ge _x C _y close to the layer region, it is preferable that the carrier supply layer for supplying carriers to said first carrier accumulation layer is further formed.

The first and second Si _1-xy Ge _x C _y
Si _1-xy Ge _x C of at least one of the layers
_{The y} layer is preferably a quantum well region.

The first and second Si _1-xy Ge _x C _y
Preferably further comprising a source-drain contact layers made of a conductor film of low resistance formed directly on formed above the Si _1-xy Ge _x C _y layer of the layers.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having an n-channel field-effect transistor and a p-channel field-effect transistor, wherein a first Si is formed on a semiconductor substrate. A first Si _1-xy having a first carrier accumulation layer serving as a channel of the n-channel field effect transistor in a region in contact with the first Si layer and in proximity to the first Si layer;
A first step of forming a Ge _x C _y layer (0 ≦ x ≦ 1, 0 <y ≦ 1), a second Si layer and a second Si layer on the semiconductor substrate, The first Si _1-xy
Ge _x C _y layer has a different band gap and a second Si ₁ having a second carrier accumulation layer serving as a channel of the second Si the p- channel field effect in the region close to the layer transistor _-xy Ge _x C _y layer (0 ≦ x ≦ 1,
0 ≦ y ≦ 1), and an S layer located above the first and second Si _1-xy G _x C _y layers.
After depositing a conductor film on the i _1-xy Ge _x C _y layer, the conductor film is patterned to form gate electrodes of the n-channel field effect transistor and the p-channel field effect transistor, respectively. Step 3, using the gate electrode of each transistor as a mask, the n-channel field effect transistor forming region is filled with an n-type impurity at least to a depth reaching the first carrier accumulation layer, and the p-channel field effect transistor is formed. A p-type impurity is introduced at least to a depth reaching the second carrier accumulation layer in the p-channel transistor formation region, and the source / drain regions of the n-channel field-effect transistor and the p-channel field-effect transistor are respectively changed. And a fourth step of forming.

According to this method, a semiconductor device having the above structure can be easily formed.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment An HCMOS device according to a first embodiment is a SiGe device.
/ Si system is made of a ternary mixed crystal of SiGeC obtained by adding C, and the SiGeC layer and the Si layer are almost lattice-matched, and an electric field which forms a band discontinuity at a hetero interface due to a difference in band gap energy. It is an effect transistor.

FIG. 1 shows an HCMOS according to the first embodiment.
It is sectional drawing which shows the structure of a device. As shown in FIG. 1, an NMOS transistor and a PMOS transistor are formed on a silicon substrate 10.
The structure of the MOS transistor will be described.

In the NMOS transistor, a p-well 11 (high-concentration p-type silicon layer) is formed on a Si substrate 10, and a δ-doped layer with a high-concentration V group element and a spacer are further formed thereon. S with layer
i layer 13n and SiGeC layer 14n (C composition ratio is 1
%, And the composition ratio of Ge is 8.2%). As will be described later, the composition ratio of each element in the SiGeC layer 14n is different from the SiGeC layer 14n and the S
The value is lattice-matched to the i-layer 13n.

At the hetero interface between the SiGeC layer 14n and the Si layer 13n, as shown in the right part of FIG. 1, there is a band discontinuity of the conduction band Ec having a band offset value ΔEc. A carrier accumulation layer for confining electrons, which are negative carriers, as a two-dimensional electron gas (2DEG) is formed in the band discontinuity. The carrier accumulation layer formed near the interface on the SiGeC layer 14n side serves as a channel through which electrons travel at high speed. Si
In the GeC layer 14n, the mobility of electrons is higher than in the Si layer, and the operating speed of the NMOS transistor can be increased.

Further, on this SiGeC layer 14n,
A SiGe layer 15n (the composition ratio of Ge is 30% and the composition ratio of Si is 70%) and a Si layer 17n are sequentially formed, and a gate insulating film 19 made of a silicon oxide film is formed on the surface.
n is formed. Since the Si layer 17n exists under the gate insulating film 19n, the gate insulating film 19n having high crystallinity can be easily formed only by oxidizing the surface of the Si layer 17n. A gate electrode 18n is formed on the gate insulating film 19n.
8n, the source / drain layers 1
6n are formed. The traveling of the electrons in the SiGeC layer 14n is controlled by the voltage applied to the gate electrode 18n. The source / drain layers 16n are
Although it is formed to a depth reaching the p-well 11, it may be formed at least to a depth of a portion to be a channel formed in the SiGeC layer 14n.

On the other hand, the PMOS transistor has substantially the same configuration as the NMOS transistor described above. An n-well 12 (high-concentration n-type Si
Layer) formed thereon, and further thereon an Si layer 13 having a δ-doped layer doped with a group V element at a high concentration
p and the SiGeC layer 14p (the composition ratio of Ge is 8.2%,
C is 1%). further,
On this SiGeC layer 14p, a SiGe layer 15p (G
e is 30%, the composition ratio of Si is 70%) and Si
The layers 17p are sequentially formed. In the case of the PMOS transistor, carriers are holes, and a channel through which the holes flow is formed on the SiGe layer 15p side at the interface between the SiGe layer 15p and the Si layer 17p. This SiGe layer 1
At the hetero interface between 5p and the Si layer 17p, there is a band discontinuity in the valence band having a band offset value ΔEv, and a carrier accumulation layer is formed at this discontinuity. Therefore, the holes travel through the channel of the carrier accumulation layer formed at the interface on the SiGe layer 15p side.
Since the mobility of holes is larger in p than in the Si layer,
The operation speed of the PMOS transistor also increases.

In the PMOS transistor, the Si layer 1
7p, a gate insulating film 1 made of a silicon oxide film
9p is formed. A source / drain layer 16p is formed on both sides of the gate electrode 18p, and the SiGe layer 15p
Is controlled by the voltage applied to the gate electrode 18p.

A trench isolation 20 is formed between the NMOS transistor and the PMOS transistor by embedding a groove formed in the substrate with a silicon oxide film. The trench isolation 20 allows the NMOS transistor and the PMOS transistor to be connected to each other. Are electrically separated from each other.

Each Si layer 13n, 13p, each SiG
eC layers 14p, 14n, SiGe layers 15n, 15p,
Each of the Si layers 17n and 17p is simultaneously formed by crystal growth. The dimensions of each layer can be, for example, the following dimensions. However, it is not necessarily limited to the following dimensions.

The thickness of each of the Si layers 13n and 13p is, for example, about 0.6 μm, and preferably ranges from 0 to 1 μm. The thickness of the spacer layer is, for example, about 30 nm, and is preferably in the range of 0 to 50 nm. Each S
The thickness of the iGeC layers 14p and 14n is preferably 3 to 50 nm. The thickness of each of the SiGe layers 15n and 15p is about 5 nm, and is preferably in the range of 3 to 5 nm. The thickness of each of the Si layers 17n and 17p is about 1 nm, and is preferably in the range of 0.5 to 5 nm. The thickness of the gate insulating films 19n and 19p is, for example, about 5 nm.

The gate length of the gate electrodes 18n, 18p is 0.25 μm, the gate width is 2.5 μm, the width of the source / drain region is about 1.2 μm, and the contact area of the source / drain electrodes 21n, 21p is , 0.5μ
It is about m × 0.6 μm. The doping concentration of each of the wells 13n and 13p is about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ , and the doping concentration of the δ-doped layer is 1 × 10 ¹⁸ to 1 × 10 ^18.
It is about × 10 ²⁰ cm ⁻³ .

The feature of the HCMOS device (heterostructure CMOS device) in this embodiment is that
The point is that a GeC layer is used. This SiGeC layer is
By adjusting the composition ratio of each of Si, Ge, and C, the amount of band gap and the lattice mismatch rate with respect to silicon can be changed. Here, Si, G in the present embodiment
The relationship between the composition ratio of e and C and the amount of strain and band offset of each layer will be described in detail.

FIG. 2 shows that when the horizontal axis indicates the composition ratio (%) of C (carbon) and the vertical axis indicates the composition ratio (%) of Ge, S
This shows how the lattice mismatch (%) (misfit) between the iGeC layer and the Si layer changes. The line with zero misfit indicates that the lattice constants of the SiGeC layer and the Si layer are equal. Since the lattice constant of Ge (germanium) single crystal is larger than the lattice constant of Si single crystal and the lattice constant of C (carbon) single crystal is smaller than the lattice constant of Si single crystal, the composition ratio of Ge and C is adjusted. By doing, Si
The lattice constant of the GeC layer 14n and the lattice constant of the Si layer 13n can be matched.

FIG. 3 is a characteristic diagram showing the relationship between the composition ratio of the three elements Si, Ge and C and lattice matching. The three vertices in the figure indicate that the composition ratio of Si, Ge, and C is 10
It is a point of 0% (composition ratio is 1), and shows how the lattice mismatch ratio with Si changes by adjusting the composition ratio of the ternary mixed crystal system of the SiGeC layer. The hatched area in FIG.
FIG. 5 shows a region of a composition ratio that gives tensile strain to the iGeC layer,
The solid line in the figure shows the condition of the composition ratio of each element for making the lattice mismatch between the SiGeC layer and the Si layer zero, that is, both are lattice matched. Since the lattice constant of Ge is 4.2% larger than the lattice constant of Si and the lattice constant of C is 34.3% smaller than the lattice constant of Si, the composition ratio of Ge is 8.2 times that of C. By increasing the lattice constant, the lattice constant of the SiGeC layer can be made to match the lattice constant of the Si layer.

In the SiGeC layer 14n according to the present embodiment, the Ge composition ratio is 8.2% (x = 0.082).
Since the composition ratio of C is 1% (y = 0.01), the lattice mismatch with the Si substrate is 0 from FIG.
It can be seen that the iGeC layer 14n and the lower Si layer 13n have the same lattice constant.

Next, FIG. 4 shows the composition ratio of C on the horizontal axis,
When the energy level is plotted on the vertical axis, the band offset value ΔEc of the conduction band and the band offset value ΔEv of the valence band at the interface between the SiGeC layer and the Si layer.
Shows a state in which changes. The black circles represent the band offset value ΔEv of the valence band, and the white circles represent the band offset value ΔEc of the conduction band. In addition, the origin of the energy is the energy value at the lower end of the conduction band of Si for the conduction band and the energy value at the upper end of the valence band of Si for the valence band. The solid line in the figure corresponds to the strain-free system, and the dotted line in the figure corresponds to the tensile strain system.

As shown in FIG. 4, the SiGe of this embodiment is
The band offset values of the conduction band and the valence band at the interface between the C layer (C composition ratio is 0.01) and the Si layer are as follows:
The values are 300 meV and 0 meV, respectively. At the interface between the SiGeC layer and the Si layer, there is no band discontinuity in the valence band, and a band discontinuity is formed only in the conduction band. Further, since the composition ratio of C in the SiGeC layer 14n of the present embodiment is 0.01, the SiGeC layer 14n
And the Si layer 13n are lattice-matched. Therefore, 2
SiGe in which a channel through which a three-dimensional electron gas travels is formed
In the C layer 14n, the occurrence of defects such as dislocations due to lattice mismatch with the lower Si layer 13n can be prevented.

On the other hand, the SiGeC layer 1 according to the present embodiment
Since there is no band discontinuity in the valence band at the interface between 4n and the Si layer 13n, holes cannot be confined in the SiGeC layer 14n. Therefore, in the case of a PMOS transistor using holes as carriers, the SiGe layer 15p
And a heterojunction between the Si layer 17p. SiG
The lattice constant of the e single crystal is larger than the lattice constant of the Si single crystal, and the SiGe layer 15p is located on the SiGeC layer 14p lattice-matched with the Si layer 13p. The band offset value in the valence band is large. In this case as well, holes are two-dimensionally confined (2DHG) due to band tilt when an electric field is applied from the gate, and the holes become carrier accumulation layers.
Therefore, the carrier accumulation layer in the SiGe layer 15p becomes a channel for holes to travel at high speed.

As described above, according to the structure of this embodiment, in the NMOS transistor, the SiGeC layer 1
By adjusting the composition ratio of each element Si, Ge, and C at 4n, while maintaining the band offset value of the conduction band at a value sufficient to accumulate the two-dimensional electron gas, the SiGeC layer and the SGe
Lattice matching with the i-layer can be achieved. Therefore, S
It is possible to achieve high reliability by reducing the defect density while realizing a high operation speed utilizing high carrier mobility of the two-dimensional electron gas in the iGeC layer.
Further, since there is no band discontinuity in the valence band at the interface between the SiGeC layer 14n and the Si layer 13n, the SiGe
Although holes cannot be confined in the C layer 14n, S
By utilizing the heterojunction between the iGe layer 15p and the Si layer 17p, a channel of a PMOS transistor using holes as carriers can be formed, and high-speed operation can be realized.

By integrating a high-speed NMOS transistor and a high-speed PMOS transistor by forming a valence band discontinuous portion using SiGe, a high-performance HCMOS device can be realized. it can.

In this embodiment, the composition ratio of Ge is set to 8.2% and the composition ratio of C is set to 1%. However, FIG.
Can be maximized by increasing the composition ratio of C. By providing such a large band offset value ΔEv, the two-dimensional electron gas (2DEG) confined at the hetero interface does not cross the hetero interface even when the electron concentration becomes high, and runs stably. Can be. In particular, it is preferable to adjust the composition ratio of C in the range of 0.01 to 0.03. Within this range, a band offset value ΔEv (= −0.2 to −0.6) suitable for forming a carrier accumulation layer for confining the two-dimensional electron gas in both the strain-free system and the tensile strain system. V) can be obtained.

In this embodiment, the SiGe layer 15p
In the above, the Ge composition ratio is set to 30%, but the Ge composition ratio may be increased so as to maximize the band offset value, and the compression strain may be increased.

Since the HCMOS device is formed on a Si substrate, the HCMOS device is used where the speed of the element is required, and the HCMOS device is otherwise formed on an active region having a normal Si composition. CMO formed
An S device may be manufactured. With this configuration, integration with a MOS field-effect transistor that is directly formed on a Si substrate is also possible. It is not necessary to form p-type and n-type transistors on the same substrate as a device using SiGeC. For example, in the case of an integrated circuit used in a mobile communication device, an amplifier, a mixer, and the like used in a high-frequency region where high-speed operation is required do not need to constitute a complementary circuit. It is conceivable to configure a MOS device using only (for example, n-type) SiGeC and a CMOS device using a single Si composition for a portion for performing digital signal processing that needs to configure a complementary circuit. .

Next, a method of manufacturing the HCMOS device according to the first embodiment will be described with reference to FIGS. FIGS. 5A to 5F show the HC shown in FIG.
FIG. 10 is a cross-sectional view showing an example of a manufacturing process for realizing the structure of the MOS device.

First, in the step shown in FIG. 5A, a p-well 11 and an n-well 12 are formed in an Si substrate 10 by ion implantation.

Next, in the step shown in FIG. 5B, a Si layer 13 including a δ-doped layer and a SiGeC layer 14 (Ge: 8.2) are formed on each of the wells 11 and 12 by UHV-CVD.
%, C: 1%), and a SiGe layer 15 and a Si layer 17 are respectively grown. Although a δ-doped layer and a spacer layer are also formed, these layers are not shown for easy viewing.

Next, in the step shown in FIG.
After forming a trench for trench isolation in order to electrically isolate the transistor and the NMOS transistor, the trench is filled with a silicon oxide film to form a trench isolation 20. By this processing, the Si layer 13, the SiGeC layer 14,
The SiGe layer 15 and the Si layer 17 are respectively composed of the Si layer 13n, the SiGeC layer 14n, and the SiGe on the NMOS transistor side.
Layer 15n, Si layer 17n, Si layer 13p, SiGeC layer 14p, and SiGe layer 15 on the PMOS transistor side.
p and the Si layer 17p. Further, the Si layer 17
The surfaces of n, 17p are oxidized to form gate insulating films 19n, 19p.
p is formed.

Next, in the step shown in FIG. 5D, after a polysilicon film is deposited on the entire surface of the substrate, it is patterned and formed on the gate insulating films 19n and 19p of the NMOS transistor and the PMOS transistor. Gate electrode 18
n and 18p are formed respectively. Thereafter, using the gate electrodes 18n and 18p as masks, source / drain regions 16n are formed by implanting phosphorus ions (P +) on the NMOS transistor side, and boron ions (B +) are implanted on the PMOS transistor side. Thereby, the source / drain regions 16p are respectively formed. The depth of the source / drain region 16n of the NMOS transistor may be at least deeper than the carrier accumulation layer in the SiGeC layer 14n.
The depth of 6p may be at least deeper than the carrier accumulation layer in the SiGe layer 15p. This is the SiGeC layer 1
This is because a channel is formed in each carrier accumulation layer in the 4n, SiGe layer 15p.

Next, in the step shown in FIG. 5E, the source / drain regions 16 of the gate insulating films 19n and 19p are formed.
Openings are formed above the n and 16p, and in the step shown in FIG. 5F, source / drain electrodes 21n and 21p are formed in the openings of the gate insulating films 19n and 19p, respectively.

Thus, the NMOS on the Si substrate 10
HCMO consisting of transistors and PMOS transistors
An S device is formed.

As described above, according to the manufacturing method of this embodiment, although it is necessary to form different channels in the NMOS transistor and the PMOS transistor, crystal growth can be performed in common by the NMOS transistor and the PMOS transistor, and Can be manufactured.

(Second Embodiment) In the first embodiment described above, a field-effect transistor is formed by using a SiGeC layer lattice-matched to silicon. In such a case, a strain is positively introduced into the SiGeC layer within a range where no distortion occurs, and a transistor utilizing a change in the band structure due to the strain is obtained. The structure of the HCMOS device according to this embodiment is basically the same as that of the PMC according to the first embodiment shown in FIG.
The structure is such that the OS transistor and the NMOS transistor are realized in one transistor.

FIGS. 6A to 6C respectively show SiGe
When compressive strain is generated in the C layer, the SiGeC layer is
Lattice matched to the layer (no strain) and SiGeC
FIG. 4 is a diagram showing a state of a crystal structure in a case where tensile strain is caused in a layer. As shown in FIG.
When the lattice constant of the eC layer is made larger than the lattice constant of the Si layer, compressive strain occurs in the SiGeC layer, and the band gap value between the lower end of the conduction band and the upper end of the valence band in the SiGeC layer is increased. On the other hand, as shown in FIG.
If the lattice constant of the eC layer is smaller than that of the Si layer, tensile strain occurs in the SiGeC layer, and the band gap between the lower end of the conduction band and the upper end of the valence band in the SiGeC layer is reduced. That is, since the band structure changes due to the strain of the SiGeC layer, the band offset value of a layer such as a Si layer adjacent to the SiGeC layer can be changed by positively utilizing this effect.

Here, even when the lattice constant of the SiGeC layer is deviated from the lattice constant of the Si layer, the thickness of the SiGeC layer is set to such an extent that lattice relaxation does not occur and strain is accumulated, thereby reducing crystal defects such as dislocations. It is possible to effectively prevent a decrease in the reliability of the element due to the occurrence.

FIGS. 7A and 7B are a band structure diagram and a cross-sectional view in the channel region of the field-effect transistor according to the present embodiment. After growing a Si layer 13n on a Si substrate, the SiGeC layer 1 with a higher C composition ratio
By growing 4n (10% of Ge and 4% of C), the band gap value of the SiGeC layer 14n can be set to be large and the lattice constant to be small. The SiGeC layer 14n is subjected to tensile strain by reducing the thickness of the SiGeC layer 14n to such an extent that strain is accumulated without causing lattice relaxation. Therefore, in addition to the effect of increasing the band gap value by increasing the composition ratio of C, the tensile strain of the SiGeC layer 14n causes the Si layer 13n to move from the Si layer 13n.
The band offset value of the conduction band at the interface of n increases, and the confinement efficiency of two-dimensional electron gas (2DEG) improves.

Furthermore, since the SiGeC layer 14n is not lattice-relaxed, the lattice constant on the upper surface matches the lattice constant of the Si layer 13n. Therefore, when the SiGe layer 15p is grown on the SiGeC layer 14n, the SiGe layer 15p
Since the lattice constant of p is larger than the lattice constant of the Si layer 13n, the SiGe layer 15p receives compressive strain.

Therefore, according to the semiconductor device of this embodiment, the SiGeC layer 14n has tensile strain and SiG
By introducing compressive strain into the e-layer 15p, SiGe
The band offset value at the conduction band at the interface between the C layer 14n and the Si layer 13n is increased, and the band offset value at the valence band at the interface between the SiGe layer 15p and the Si layer 17p is increased. NMO
When used as an S transistor, the SiGeC layer 1
4n, while using it as a PMOS transistor, by using the channel formed in the SiGe layer 15p, it is possible to have a common gate electrode and source / drain regions, Different HCMOS devices can be formed.

Furthermore, by properly setting the thickness of each layer, it is possible to obtain an HCMOS device having a highly reliable field effect transistor with good crystallinity without dislocations or defects due to lattice mismatch. .

Note that the broken line in FIG. 4 described above indicates a composition in which 0.25% tensile strain is applied to the SiGeC layer 14n in the present embodiment. Generally, SiGeC
Since the lattice matching with the Si layer occurs when the Ge composition ratio in the layer is 8.2 times the C composition ratio, SiGe is reduced by making the Ge composition ratio smaller than 8.2 times the C composition ratio.
Tensile strain can be introduced into the C layer 14n. When the composition ratio of C is y, the composition of Ge is 8.2y.
In the case of −0.12, the lattice constant of the SiGeC layer 14n can be made 0.25% smaller than the lattice constant of the Si layer 13n.

As shown in FIG. 4, at the interface between the SiGeC layer 14n and the Si layer 13n, there is no band discontinuity in the valence band and only in the conduction band at the interface between the SiGeC layer 14n and the Si layer 13n. It is understood that it is done. When the composition ratio of C is 2% or less, the band offset value of the conduction band is almost the same as in the case of no distortion. Even if it deviates, it is possible to obtain almost the same element characteristics as the lattice matching system. This means that the conditions can be varied from the viewpoint of controlling the composition ratio of C and the composition ratio of Ge when growing the SiGeC layer 14n, thereby facilitating the crystal growth of the SiGeC layer. To Further, when the composition ratio of C is 2% or more, the band offset value can be increased even at the same composition ratio of C, as compared with the case where there is no distortion. This allows
It is also possible to cope with a case where it is necessary to increase the band offset value.

Here, although the lattice constant of SiGeC is used smaller than that of Si, the thickness of the layer is set to such an extent that lattice relaxation does not occur and strain is accumulated. The reliability of the device does not decrease.

(Third Embodiment) In the first embodiment described above, a heterostructure in which a SiGeC layer is lattice-matched to a Si layer is formed in the channel region of a field-effect transistor, and a band at a hetero interface is not formed. Electrons or holes were confined in the continuous portion and used as carriers.

In the present embodiment, the quantum well structure is formed not in the hetero interface but in the Si / SiGeC / Si or Si / SiGe / Si structure in the region for confining carriers, and the quantum wells (SiGeC, Si
A transistor that operates using Ge) as a channel is provided.

FIG. 8 is a sectional view of the HCMOS device according to this embodiment. CMO in which an NMOS transistor and a PMOS transistor are formed on a Si substrate 30
This is an S device structure. In this structure, the silicon substrate 3
The point in which a p-well 31 and an n-well 32 are provided on 0 and the points in which first Si layers 33n and 33p having a δ-doped layer doped with a group V element at a high concentration are provided thereon. HCMO shown in FIG. 1 in the first embodiment
It has the same structure as the S device. However, this first S
PMOS transistors on i-layers 33n and 33p, NMO
The structure of the S transistor is different from the structure of the first embodiment.

In the NMOS transistor, a SiGeC layer 34n having a composition lattice-matched to the first Si layer 33n is formed on the first Si layer 33n.
Further, a second Si layer 35n is laminated on the SiGeC layer 34n. In the present embodiment, the first Si layer 33n
In the conduction band extending from the SiGeC layer 34n to the second Si layer 35n, there is a quantum well region (SiGeC layer 34n) sandwiched between two band discontinuities. The carrier accumulation layer for confining the two-dimensional electron gas (2DEG) is formed (see the band diagram on the right side of FIG. 8). That is, when the NMOS transistor operates, S
A channel is formed in the iGeC layer 34n. The second
36n having a small film thickness on the Si layer 35n
And a third Si layer 37n are sequentially formed.

With this structure, as in the first embodiment, SiGeC having a higher electron mobility than the Si layer is used.
Since a channel for moving carriers is formed in the layer 34n, an NMOS transistor with a high operation speed can be obtained. In addition, since the thickness of the SiGeC layer 34n serving as the quantum well layer is small, the carrier confinement efficiency is reduced to the first level.
It can be realized with a system having a smaller mixed crystal ratio than the structure of the embodiment. Therefore, it is possible to suppress factors that deteriorate the mobility of electrons serving as carriers, such as scattering of carriers due to deterioration of the regularity of the crystal structure due to the mixed crystal.

Also in the PMOS transistor, on the first Si layer 33p, a SiGeC layer 34p having a composition lattice-matched to the first Si layer 33p, and a second Si layer 3
5p, the SiGe layer 36p having a small thickness, and the third Si
The point that the layer 37p is sequentially formed is the same as the structure of the NMOS transistor. However, in the case of a PMOS transistor, the second Si layer 35p-SiGe layer 36
In the valence band extending over the p-third Si layer 37p, there is a quantum well region (SiGe layer 36p) sandwiched between two band discontinuities, and holes serving as carriers are two-dimensionally formed in the quantum well region. A carrier accumulation layer for confining the substrate is formed. That is, during the operation of the PMOS transistor, a channel is formed in the SiGe layer 36p. SiG
The e-layer 36p also has a higher hole mobility than the Si layer, so that the operation speed of the PMOS transistor also increases.

Further, an NMOS transistor and a PMOS
In the transistor, gate insulating films 39n and 39p made of a silicon oxide film are formed on a substrate, and gate electrodes 38n and 3p are formed on the gate insulating films 39n and 39p.
8p is formed. Source / drain layers 42n and 42p are formed on both sides of the gate electrodes 38n and 38p, respectively.
Source / drain regions 42n and 42p
The drain electrodes 41n and 41p are in contact. Needless to say, NMOS transistors, PMOs
In the S transistor, SiGe which is a quantum well region is used.
The traveling of electrons and holes in the C layer 34n and the SiGe layer 36p is controlled by voltages applied to the gate electrodes 38n and 38p, respectively.

A trench isolation 40 is formed between the NMOS transistor and the PMOS transistor by embedding a silicon oxide film in a trench for isolation.
The OS transistors are electrically isolated from each other.

According to the HCMOS device of the present embodiment, similarly to the first embodiment, in the NMOS transistor, the SiGeC layer 34n which is lattice-matched to the Si layer and serves as a quantum well region is formed.
A channel for electrons to travel is formed in the GeC layer 34n. Also in the PMOS transistor, a SiGe layer 36p serving as a quantum well region is formed, and a channel for holes to travel is formed in the SiGe layer 36p. Therefore, an NM having a high switching speed utilizing a quantum well structure having a high carrier confinement efficiency
By integrating the OS transistor and the PMOS transistor, a high-performance HCMOS can be realized.

However, in this embodiment, the HCMOS device may be used for a circuit requiring element speed, and a CMOS device formed on a normal Si substrate may be manufactured for other circuits. Also, integration with a MOS field effect transistor formed directly on a Si substrate is possible.

Note that both the channels of the NMOS transistor and the PMOS transistor do not necessarily have to be quantum well regions.

Next, a method of manufacturing the HCMOS device according to the third embodiment will be described with reference to FIGS. 9A to 9F are cross-sectional views showing an example of a manufacturing process for realizing the structure of the HCMOS device shown in FIG.

First, the outline of the manufacturing process will be described.
When growing the GeC layer 34, the second Si layer 35, and the SiGe layer 36, the SiGeC layer 34 and the SiGe layer 36
Is 10 nm or less, for example, 3 nm so as to form a quantum well structure. Other parts are shown in FIGS.
It is formed in substantially the same process as the process shown in FIG.

First, in the step shown in FIG. 9A, a p-well 31 and an n-well 32 are formed in a Si substrate 30 by ion implantation.

Then, in the step shown in FIG. 9B, δ is formed on the p-well 31 and the n-well 32 by the UHV-CVD method.
A first Si layer 33 including a doped layer, and a SiGeC layer 34
(Ge: 36%, C: 4%), the second Si layer 35,
The SiGe layer 36 and the third Si layer 37 are sequentially grown.

Next, in the step shown in FIG.
In order to electrically isolate the transistor and the NMOS transistor, a trench isolation trench is formed, and then the trench is filled with a silicon oxide film to form a trench isolation 40.
By this processing, the first Si layer 33, the SiGeC layer 3
4. The second Si layer 35, the SiGe layer 36, the third Si layer 37, and the gate insulating film 39 are formed of the first Si layer 33n, the SiGeC layer 34n, and the second
Si layer 35n, SiGe layer 36n, third Si layer 37
n, the first Si layer 33p on the PMOS transistor side,
It is separated into a SiGeC layer 34p, a second Si layer 35p, a SiGe layer 36p, and a third Si layer 37p. afterwards,
The surfaces of the third Si layers 37n and 37p are oxidized to form gate insulating films 39n and 39p.

Thereafter, in the step shown in FIG. 9D, after forming the gate electrodes 38 and 38p, the source and the source electrodes are implanted into the NMOS transistor side by implanting phosphorus ions (P +).
A drain region 42n is formed, and a source / drain region 42p is formed on the PMOS transistor side by implanting boron ions (B +). The depth of the source / drain region 42n of the NMOS transistor is at least SiG
It is sufficient that the depth is deeper than the eC layer 34n, and the depth of the source / drain region 42p of the PMOS transistor is at least deeper than the SiGe layer 36p. This is SiG
This is because a channel is formed in the eC layer 34n and the SiGe layer 36p.

Thereafter, in the step shown in FIG. 9E, openings are formed in the gate insulating films 39n and 39p above the source / drain regions 42n and 42p, and in the step shown in FIG. The source / drain electrodes 41n and 41 are formed in the openings.
p is formed.

Through the above steps, the structure of the HCMOS device including the NMOS transistor and the PMOS transistor according to the third embodiment is realized.

According to the manufacturing method of this embodiment, the NMOS
The channel of the transistor is a SiGeC layer 34n of a quantum well structure using a heterojunction, and the channel of the PMOS transistor is an SGe of a quantum well structure using a heterojunction.
An HCMOS device having the iGe layer 36p is easily formed. Moreover, according to the manufacturing method of the present embodiment, NM
Although the OS transistor and the PMOS transistor need to form different channels, the crystal growth is NMO.
It can be commonly used for the S transistor and the PMOS transistor, and can be easily manufactured.

(Fourth Embodiment) FIG. 10 is a sectional view showing the structure of a field-effect transistor according to a fourth embodiment. This embodiment relates to a structure for providing a source / drain contact suitable for a hetero field effect transistor.

As shown in the figure, a SiGe buffer layer 52, a δ-doped layer 53, a spacer layer 54, and an n-channel layer 67 are formed on a well 51 made of a Si layer.
When, a i-Si layer 55, the i-Si _1-x Ge x layer 56,
An i-Si layer 57 and a gate insulating film 58 are formed. A gate electrode 65 is formed on the gate insulating film 58, on a region located on both sides of the gate electrode 65 of the i-Si _1-x Ge _x layer 56, the source-drain contact W layers 61 Al source / drain electrodes 63 are sequentially formed. Further, on both sides of the gate electrode 65, a part of the SiGe buffer layer 52, the δ-doped layer 5
3, spacer layer 54, n-channel layer 67, i-Si
Layer _{55, i-Si 1-x} Ge x layer 56 and the i-Si layer 57
The source / drain region 59 is formed in the region extending over the region. Further, the space between the gate electrode 65 and the Al source / drain electrode 63 is filled with a first-layer insulating film 66.

Here, the structure of each part of the field effect transistor will be described.

First, the composition ratio of Ge in the SiGe buffer layer 52 increases as going upward. The SiGe buffer layer 52 has a lattice constant larger than that of Si by forming the SiGe mixed crystal with a film thickness sufficient to relax the lattice of the SiGe mixed crystal. The formation is made possible. It should be noted that, without using such a lattice-relaxed SiGe buffer layer, S
When a heterojunction between the i layer and the SiGe layer is formed, a large discontinuous portion having a large step appears in the valence band, but almost no discontinuous portion appears in the conduction band. -It is difficult to form channels.

Here, G in the SiGe buffer layer 52
The composition ratio of e changes, for example, continuously from 0% to 30% or stepwise for each thin layer. At this time, lattice relaxation is caused in each layer so that the lattice constant in the substrate surface at the uppermost surface of the buffer layer is the same as that of bulk Si _0.7 Ge _0.3 . The reason why the composition ratio is changed in the vertical direction is to reduce the influence of crystal defects such as dislocations caused by lattice relaxation on the channel thereover. Note that the SiGe buffer layer 5
The overall film thickness of No. 2 needs to be approximately 1 μm.

On this SiGe buffer layer 52, a spacer layer 54 of Si _0.7 Ge _0.3 to which no impurity is added is arranged. This spacer layer 54 and the Si layer 55 thereon
A carrier accumulation layer is formed at a discontinuous portion of the conduction band existing at the hetero interface with the semiconductor layer, and this carrier accumulation layer is an n-channel 67 for two-dimensionally confining electrons.

The δ-doped layer 53 is a layer in which a group V element such as P or As is heavily doped to supply electrons as carriers to the n-channel 67. The spacer layer 54 on the δ-doped layer 53 is made of
It is composed of i _0.7 Ge _0.3 and has a role of spatially separating carrier electrons of the n-channel 67 and ions of the δ-doped layer 53, thereby reducing scattering of carrier electrons by ions and improving mobility. As the thickness of the spacer layer 54 is larger, the effect of scattering carriers due to ionized impurities can be reduced. However, the carrier density is reduced, so that the thickness is preferably about 3 nm.

[0100] i-Si _1-x Ge x layer 56 and the i-Si layer 5
7 forms a step in the valence band at the heterointerface and is used to form a p-channel 68. X is preferably set to about 0.7.

The gate insulating film 58 insulates between the gate electrode 65 and the semiconductor layer therebelow to reduce a gate leak current and enable low power consumption operation of the device. Since an oxide film formed by oxidizing the SiGe layer 56 is a water-soluble and unstable film, it is preferable to use a silicon oxide film as a gate insulating film also in a SiGe-based field-effect transistor. Therefore, Si-based hetero M
In an OS device, the semiconductor layer immediately below the gate insulating film is preferably a Si layer.

That is, in the field-effect transistor according to the present embodiment, the channel region composed of the above-mentioned laminated film, the source / drain region 59 shown by the broken line in FIG. And a gate electrode 65 for applying a voltage for controlling the current. Then, this field effect transistor is n-
When used as a channel field effect transistor, the gate electrode 65 is formed so that an n-channel 67 is formed.
When a p-channel field effect transistor is used, a voltage is applied to the gate electrode 65 so that a p-channel 68 is formed.

The feature of the invention according to the present embodiment is that
A first semiconductor layer containing _1-xy Ge _x C _y layer (0 ≦ x ≦ 1,0 ≦ y ≦ 1), and a second semiconductor layer having a different band gap from the first semiconductor layer, The above first and second
A channel region having a carrier storage layer formed in a region near an interface between the semiconductor layers, a third semiconductor layer,
A source / drain region having a fourth semiconductor layer having a band gap larger than that of the third semiconductor layer, and a source / drain contact comprising a low-resistance conductor film formed immediately above the third semiconductor layer And a layer.

When the field-effect transistor of this embodiment is used as an n-channel field-effect transistor, the i-Si layer 55 is formed of a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1,0 ≦ y ≦ 1) (x = y = 0), the SiGe buffer layer 52 is a second semiconductor layer, and the i-Si _1-x Ge _x layer 56 is a third semiconductor layer. I-Si layer 57 is an i-Si _1-x Ge _x layer 5
6 a fourth semiconductor layer greater in band gap than the source-drain contact W layers 61 directly above the third i-Si _1-x Ge _x layer 56 is a semiconductor layer is formed.

On the other hand, when the field-effect transistor of this embodiment is used as a p-channel field-effect transistor, the i-Si _1-x Ge _x layer 56 is made of Si _1-xy Ge
a first semiconductor layer including _x C _y layer (0 ≦ x ≦ 1,0 ≦ y ≦ 1) with (y = 0) is the third semiconductor layer,
The i-Si layer 57 is a second semiconductor layer and a fourth semiconductor layer having a larger band gap than the third semiconductor layer. The i-Si layer 57 is an i-Si _1-x Ge _x layer which is a third semiconductor layer. A source / drain contact W layer 61 is formed immediately above 56.

As described above, in this embodiment, the region on the substrate side for making contact with the Al source / drain electrode 63 is provided in a layer having a small band gap among the semiconductor layers for channel formation. In this embodiment,
Si layer 57 for forming p-channel and i-Si _1-x Ge _x
Of the hetero interface of layer 56, it has a structure providing a source-drain contact W layers 61 directly above the small i-Si _1-x Ge _x layer 56 bandgap. As a result, the contact resistance becomes smaller than when a contact is provided immediately above the i-Si layer 57 which is the uppermost semiconductor layer,
Low power consumption and high-speed operation of the device are made possible.

It is to be noted that a contact having a very low resistance can be obtained by depositing a metal (in this case, Al) after growing W on the Si _0.7 Ge _0.3 layer on the Si layer. The contact using this SiGe film is a conventional C
A contact that has an order of magnitude lower resistance than a low-resistance contact using silicide technology commonly used as a low-resistance contact in MOS devices can be obtained (IEEE Ele)
ctron Device Letters vol.17, No.7, 1996 pp36
0).

In this paper, the SiGe layer is grown only for forming the source / drain electrode contacts. However, as in this embodiment, the SiGe layer for forming the channel is used.
If a structure in which a layer is contacted is used, it is not necessary to grow a new SiGe crystal as will be described later in a transistor manufacturing method, and the productivity is improved.

However, in this embodiment, the HCMOS device is used where the device speed is required, and otherwise, the C CMOS formed on a normal Si substrate is used.
A MOS device may be manufactured, and integration with a MOS type field effect transistor formed directly on a Si substrate is also possible.

Next, a method for manufacturing the field-effect transistor according to this embodiment will be described. FIG.
12 (e) and FIGS. 12 (a) to 12 (e) are cross-sectional views showing an example of a manufacturing process for realizing the structure of the field-effect transistor shown in FIG.

First, in the step shown in FIG. 11A, prior to the epitaxial growth for channel formation, ions are implanted into the Si substrate 50 to form p-wells 51n and n-wells 51p which are the bases of the NMOS and PMOS transistors. I do.

Next, in the step shown in FIG. 11B, before epitaxial growth is performed on the substrate, the substrate is subjected to cleaning using an RCA cleaning method or the like to remove impurities on the surface.
Thereafter, the oxide film on the surface is removed, the substrate is inserted into an epitaxial growth apparatus, and heating is performed in a vacuum state to obtain a clean surface. Then, epitaxial growth of a semiconductor layer for forming a channel region is performed on the clean surface.
This semiconductor layer includes a SiGe buffer layer 52, a δ-doped layer 53, a spacer layer 54, an n-channel layer 67, an i-
Si layer _{55, i-Si 1-x} Ge x layer 56, include p- channel layer 68, i-Si layer 57 and the like. However, in order to make it easier to see, the δ-doped layer 53, the spacer layer 54, n
The illustration of the -channel layer 67 and the p-channel layer 68 is omitted. Hereinafter, a procedure for forming each layer in the semiconductor layer will be described.

The semiconductor layer can be grown by MBE using a solid source or UHV-C using a gas source.
A VD method or the like can be used. In the case of the UHV-CVD method, the atmosphere in the apparatus is first set to an ultra-high vacuum (about 10 ^-10 Torr), a source necessary for crystal growth is introduced into a vacuum vessel, and then about 10 ^-5 to 10 ^-6 Torr. The crystal is grown in a state where the degree of vacuum has been reached.

Therefore, also in this embodiment, after a clean surface is formed on the substrate by the above-described processing, when the degree of vacuum in the vacuum vessel becomes sufficiently high, the substrate temperature is raised to 500-70.
The temperature is set at about 0 ° C., and each semiconductor crystal layer is grown. Note that changing the substrate temperature affects the crystal quality such as a change in the composition ratio within a single semiconductor crystal layer.
Basically, the substrate temperature is not changed while growing a single layer. At a high temperature such as 800 ° C. or more, Ge
And Si are interdiffused, thereby deteriorating the steepness of the hetero interface or degrading the strain and deteriorating the channel characteristics. Therefore, the growth temperature is set to 700 ° C. or less as described above. deep.

The crystal growth is performed by introducing a source gas necessary for crystal growth into a vacuum vessel in an ultra-high vacuum state. As a source gas used for crystal growth, disilane is used for growing a Si layer. In growing the SiGe layer, germane is used as a Ge source gas in addition to a source gas for growing a Si layer such as disilane. At this time, by adjusting the partial pressure ratio of each source gas, Si
The composition ratio of Si and Ge in the Ge layer can be controlled. The gas flow rate is adjusted so that the degree of vacuum is about 10 ^-5 to 10 ^-6 Torr.

First, the SiGe buffer layer 52 is formed by stacking a number of SiGe layers whose composition ratios are changed stepwise and whose lattice is relaxed. At this time, in order to change the composition ratio stepwise, as described above, the ratio between the partial pressure of the Si source gas and the partial pressure of the Ge source gas is changed stepwise.

Next, to form the δ-doped layer 53, a dopant gas such as arsine or phosphine is introduced into a vacuum vessel together with disilane and germane.

Here, if the impurities introduced into the δ-doped layer 53 are mixed with the spacer layer 54, the transistor characteristics are deteriorated. After the degree of vacuum is sufficiently improved, a gas for growing the spacer layer 54 is introduced to grow the spacer layer 54. Spacer layer 5
The composition of No. 4 is uniformly made of Si _0.7 Ge _0.3 and the growth is performed while fixing the flow rates of disilane and germane.

After the growth of the spacer layer 54, the supply of the source gas is temporarily stopped, and after the degree of vacuum is improved, only disilane is introduced into the growth chamber, and the i-Si layer 5 not doped with impurities is doped.
Grow 5.

After the growth of the i-Si layer 55, disilane and germane are introduced again into the growth chamber, and the i-Si _1-x Ge _x layer 56 is formed.
Grow. The composition ratio of Ge is 70%. i-Si
After the growth of _1-x Ge _x layer 56, after stopping once the supply of the source gas, only disilane from the improved vacuum was introduced into the growth chamber, growing a i-Si layer 57.

By the above processing, the step of epitaxially growing the semiconductor layer forming the channel region is completed.

Next, in the step shown in FIG. 11C, the substrate is taken out of the UHV-CVD apparatus, introduced into a thermal oxidation furnace, and the surface of the uppermost i-Si layer 57 is oxidized to form a silicon oxide film. A gate insulating film 58 is formed.

Next, a gate electrode 65 is formed on the gate insulating film 58 in the step shown in FIG. The method of forming the gate electrode is the same as the conventional CMOS device process. That is, a polysilicon film is deposited, impurities are ion-implanted, and then the polysilicon film is patterned by dry etching to form gate electrodes 65n and 65p.
As the impurity ions, boron fluoride ions (BF2 +) can be used. At the stage when the polysilicon film for the gate electrode is deposited, no source / drain regions are formed.

Next, in the step shown in FIG. 11E, using the gate electrodes 65n and 65p as a mask, impurity ions serving as dopants are implanted into the substrate to form source / drain regions 59n and 59p. In order to make contact, etching is performed to remove the oxide film exposed on the substrate. At the time of ion implantation, the acceleration voltage of the ions is selected so that the peak of the impurity distribution is in the layer where the source / drain electrode contacts are provided. As impurity ions to be implanted, arsenic ions (As +) or phosphorus ions (P +), which are n-type impurities, are used in the NMOS transistor region, and boron ions (B +), which are p-type impurities, are used in the PMOS transistor region. I do. Therefore, the source / drain region 5 of the NMOS transistor
The ion implantation for forming 9n and the ion implantation for forming the source / drain region 59p of the PMOS transistor need to be performed using separate masks.

Immediately after ion implantation, annealing for activating impurities is performed. However, due to the annealing heat treatment, the interdiffusion of Si and Ge at the hetero interface and the Si / S
It is preferable to perform RTA (rapid thermal annealing) at a temperature of about 1000 ° C. for a short time (30 seconds) so as to prevent generation of crystal defects in the process of relaxing strain existing in the iGe system.

Next, in a step shown in FIG. 12A, a photoresist mask (not shown) is formed again on the substrate, and an NMOS transistor forming region is formed by dry etching.
A region between the PMOS transistor formation regions is dug deeper than at least the channel region to form a trench 71 for element isolation.

Next, in the step shown in FIG.
A first-layer insulating film 72 is deposited over the entire surface of the substrate including. In order to avoid a high-temperature process, it is preferable to use a TEOS film formed by a plasma CVD method at 500 ° C. or lower as a material for forming the insulating film. At this time, a trench isolation 73 is formed by the insulating film embedded in the groove 71.

Next, a source / drain contact which is a feature of this embodiment is formed by the following procedure. However, the steps for realizing the structure shown in FIG. 10 are not limited to the following procedures.

In order to maximize the effects of the present embodiment, it is necessary that an extremely thin specific semiconductor layer finally serving as a base of the contact exists. For this purpose, in the present embodiment, i-Si
_1-x Ge _x layer 56n, select _{56p, i-Si 1-x} G
e _x layer 56n, etched until 56p are exposed. The i-Si _1-x Ge _x layer 56n, it is preferable to use a high selectivity by wet etching etching when exposing the 56p. However, since wet etching has poor anisotropy and is not suitable for fine processing, first, a region where a source / drain electrode is to be formed in the first insulating film 72 is selectively removed by dry etching. It is preferable to perform wet etching after forming contact holes and exposing the gate insulating films 58n and 58p. Examples of such processing include, for example, the following processing.

First, the uppermost oxide film (gate insulating film 58)
For removal of n, 58p), a hydrofluoric acid-based solution is used as is well known. Then, the i-Si layers 57n, 5
When 7p is exposed, since hydrofluoric acid hardly removes silicon, the etchant is changed to an etchant that can remove the i-Si layer 57. Here, in the present embodiment, i
I-Si _1-x Ge _x layer 5 under Si layers 57 n and 57 p
6n, 56p, so that i-Si
_1-x Ge x layer 56n, without much etch 56p, i-
An etchant (etchant) capable of selectively etching the Si layers 57n and 57p is selected. Then, using this etchant, the i-Si layers 57n and 57p are removed,
i-Si _1-x Ge x layer 56n, thereby exposing the 56p. In this _{case, i-Si 1-x Ge} x layer 56n, a part of the 56p may be removed by overetching. As mentioned earlier, the i-Si _1-x Ge x layer 56n, 56p is
This is epitaxially grown to form an n-channel in the channel region of the NMOS transistor. Therefore, according to the present embodiment, in order to form a low-resistance contact using a SiGe layer, a new i-Si
_1-x Ge _x layer 56n, the process for growing the 56p is unnecessary.

[0131] Next, in order to form the contact, the exposed i-Si _1-x Ge x layer 56n, depositing a low-resistance metal film on 56p. If tungsten (W) is used as a metal material for forming the metal film as described above, a contact having a very low resistance value can be formed. Therefore, in the present embodiment, a gas obtained by diluting WF6 with hydrogen by LPCVD is used as a source gas, the temperature condition is set to 400 ° C., and the source / drain contacts W are formed on the i-Si _1-x Ge _x layers 56n and 56p. Layer 6
1n and 61p are selectively grown.

Next, in the step shown in FIG. 12E, sputtering is performed to deposit an Al alloy film on the entire surface of the substrate, followed by patterning to form an Al source / drain electrode 6.
3n and 63p are formed. Through the above steps, a low-resistance contact can be formed on the source / drain region.

As described above, in the Si-based hetero MOS device, since the silicon oxide film is used as the gate insulating film, the semiconductor uppermost layer is preferably a Si layer having a large band gap. The technique of forming a contact metal layer after removing such a semiconductor layer is a technique particularly suitable for forming a Si-based hetero MOS device.

(Fifth Embodiment) In the above embodiment, a channel structure using a heterojunction made of Si and SiGe is taken as a representative example. However, a low-resistance contact is provided in the source / drain region of the HCMOS device. The invention to be formed is not limited to such an embodiment, and Si and SiGe of this embodiment are formed.
Of a heteroepitaxial layered film having a configuration other than the layered structure of, for example, Si and Si _1-xy Ge _x C
_A channel may be formed between _y (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) and a mixed crystal semiconductor. Since the formation of a channel by a hetero interface always requires the junction of two types of semiconductors having different band gaps, the formation of such a low-resistance contact layer is effective.

FIG. 13 shows an HCMO according to a fifth embodiment in which a low-resistance contact metal layer is formed on the structure shown in FIG.
It is sectional drawing of an S device.

As shown in the figure, the HC according to this embodiment is
In a MOS device, the SiGe layers 15n, 15p
On the source / drain contact W layers 25n, 25
p is formed.

The features of the present invention according to the present embodiment are as follows.
In addition to the features of the embodiment, as in the fourth _{embodiment, Si 1-xy Ge x C} y layer (0 ≦ x ≦ 1,0 ≦ y ≦
1) a first semiconductor layer, a second semiconductor layer having a band gap different from that of the first semiconductor layer, and a region formed near an interface between the first and second semiconductor layers. A source / drain region having a channel region having a carrier accumulation layer, a third semiconductor layer, and a fourth semiconductor layer having a band gap larger than that of the third semiconductor layer; And a source / drain contact layer formed of a low-resistance conductor film formed immediately above the layer.

In the NMOS transistor of this embodiment, the SiGeC layer 14n is formed of Si _1-xy Ge _x
The first semiconductor layer includes a C _y layer (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), the Si layer 13n is a second semiconductor layer,
The Ge layer 15n is a third semiconductor layer, the Si layer 17n is a fourth semiconductor layer having a larger band gap than the SiGe layer 15n, and the SiGe layer 1 is a third semiconductor layer.
A source / drain contact W layer 25n is formed immediately above 5n.

[0139] On the other hand, in the PMOS transistor of the present embodiment, SiGe layer 15p is Si _1-xy Ge _x C _y
The first semiconductor layer (y = 0) including the layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) is the third semiconductor layer, and the Si layer 17p is the second semiconductor layer. A source / drain contact W layer 25p is formed on the fourth semiconductor layer having a larger band gap than the third semiconductor layer, and directly above the SiGe layer 15p which is the third semiconductor layer.

As described above, in the present embodiment, the region on the substrate side (the source / drain contact W layer 25) which makes contact with the Al source / drain electrodes 21n and 21p.
n, 25p) is provided immediately above a layer having a small band gap in each semiconductor layer for forming a channel.
The contact resistance is smaller than when a contact is provided directly above the Si layers 17n and 17p, which are the uppermost semiconductor layers, and low power consumption and high-speed operation of the element can be achieved.

In particular, since the source / drain contact W layers 25n and 25p made of tungsten (W) are provided so as to be in contact with the SiGe layers 15n and 15p, a very low contact resistance can be obtained.

That is, in the present embodiment, it is possible to reduce the contact resistance while exhibiting the effect of the first embodiment.

Sixth Embodiment FIG. 14 is a sectional view of an HCMOS device according to a sixth embodiment in which a low-resistance contact metal layer is formed on the structure shown in FIG.

As shown in the figure, the HC according to this embodiment is
In a MOS device, source / drain contact W layers 45n and 45p are formed on SiGe layers 36n and 36p serving as quantum well regions.

The feature of the invention according to the present embodiment is that
In addition to the features of the embodiment, as in the fourth _{embodiment, Si 1-xy Ge x C} y layer (0 ≦ x ≦ 1,0 ≦ y ≦
1) a first semiconductor layer, a second semiconductor layer having a band gap different from that of the first semiconductor layer, and a region formed near an interface between the first and second semiconductor layers. A source / drain region having a channel region having a carrier accumulation layer, a third semiconductor layer, and a fourth semiconductor layer having a band gap larger than that of the third semiconductor layer; And a source / drain contact layer formed of a low-resistance conductor film formed immediately above the layer.

In the NMOS transistor of this embodiment, the SiGeC layer 34n serving as the quantum well region
Is a Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 ≦ y ≦ 1)
The first Si layer 33n is a second semiconductor layer, and the SiGe layer 3 is a quantum well region.
6n is a third semiconductor layer, and the third Si layer 37n is
a fourth semiconductor layer having a larger band gap than the iGe layer 36n,
A source / drain contact W layer 45n is formed immediately above n.

[0147] On the other hand, in the PMOS transistor of the present embodiment, SiGe layer 36p is Si _1-xy Ge _x C _y
The first semiconductor layer (y = 0) including the layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) is the third semiconductor layer, and the third Si layer 37p is the second semiconductor layer. In addition, a source / drain contact W layer 45p is formed on the fourth semiconductor layer having a larger band gap than the third semiconductor layer and directly on the SiGe layer 36p as the third semiconductor layer.

As described above, in the present embodiment, the region on the substrate side (the source / drain contact W layer 45) which makes contact with the Al source / drain electrodes 41n and 41p.
n, 45p) is provided immediately above a layer having a small band gap in each semiconductor layer for forming a channel.
The contact resistance is lower than when a contact is provided directly above the Si layers 37n and 37p, which are the uppermost semiconductor layers, and low power consumption and high-speed operation of the device can be achieved.

Particularly, since the source / drain contact W layers 45n and 45p made of tungsten (W) are provided so as to be in contact with the SiGe layers 36n and 36p, a very low contact resistance can be obtained.

That is, in the present embodiment, it is possible to reduce the contact resistance while exhibiting the effect of the third embodiment.

(Other Modifications) In the first to sixth embodiments, the description has been given of the MOS field-effect transistor in which the gate insulating film is provided below the gate electrode. However, the present invention is limited to such an embodiment. Not something. In particular, hetero MOS with an insulating film on the top layer
If the field effect transistor uses a heterointerface instead of a structure, the device can be implemented even with a device using a Schottky junction without using an insulating film, and it is possible to obtain an effect of reducing resistance, thereby achieving low power consumption and high speed operation of the device. It is more advantageous.

In the first to sixth embodiments, the δ-doped layer is formed. However, the present invention is not limited to such an embodiment, and the effects of the present invention can be exhibited without providing the δ-doped layer. It is possible to do. Further, even when the δ-doped layer is formed, the spacer layer is not always necessary.

Instead of the SiGe layers in the first, second, third, fifth, and sixth embodiments, S containing a small amount of C was added.
An iGeC layer may be provided.

In addition, the first, second, third, fifth, sixth
In the embodiment, the vertical relationship between the SiGeC layer and the SiGe layer may be reversed. In that case, in the fifth and sixth embodiments, the source / drain contact W is located directly above the SiGeC layer in the source / drain region.
A layer may be formed.

[0155]

According to the semiconductor device of the present invention, in a semiconductor device having a field effect transistor, the first S
i layer - first Si _1-xy Ge _x C _y layer, second Si layer - electrons and holes by utilizing the band discontinuity at the interface of the second Si _1-xy Ge _x C _y layers Is formed two-dimensionally, and a field-effect transistor having this accumulation layer as a channel is provided, so that the n-channel has a channel with high carrier confinement efficiency, a high operating speed, and a high reliability. And a semiconductor device that functions as an HCMOS device having a p-channel field-effect transistor.

The structure of the semiconductor device can be easily realized by the method of manufacturing a semiconductor device according to the present invention .

[Brief description of the drawings]

FIG. 1 shows a SiGeC-based HCMOS according to a first embodiment.
It is sectional drawing which shows the structure of a device.

FIG. 2 is a diagram showing the dependence of the lattice distortion of a SiGeC layer in an HCMOS device on the Ge composition ratio and the C composition ratio.

FIG. 3 shows SiGeC of a SiGeC-based HCMOS device.
FIG. 4 is a diagram showing a relationship between the composition ratio of Si, Ge, and C that causes lattice matching or tensile strain between a layer and a Si layer.

FIG. 4 is a diagram showing a relationship between a C composition ratio of an SiGeC layer and an energy gap value.

FIG. 5 is a cross-sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment.

FIG. 6 is a diagram showing the relationship between the composition of a SiGeC layer and strain due to lattice mismatch in the second embodiment.

FIG. 7 shows a lattice-matched SiGeC— according to the second embodiment.
It is a figure which shows the band lineup of HCMOS device.

FIG. 8 is a cross-sectional view illustrating a structure of an HCMOS device having a channel having a quantum well structure according to a third embodiment.

FIG. 9 is a sectional view illustrating a manufacturing process of the semiconductor device according to the third embodiment;

FIG. 10 is a sectional view showing a structure of an HCMOS device according to a fourth embodiment.

FIG. 11 is a cross-sectional view showing a first half of a manufacturing process of an HCMOS device according to a fourth embodiment.

FIG. 12 is a cross-sectional view showing the latter half of the manufacturing process of the HCMOS device according to the fourth embodiment.

FIG. 13 is a sectional view showing a structure of an HCMOS device according to a fifth embodiment.

FIG. 14 is a cross-sectional view illustrating a structure of an HCMOS device according to a sixth embodiment.

FIG. 15 is a cross-sectional view showing a structure of a conventional HCMOS device.

FIG. 16 is a diagram showing defects such as dislocations due to lattice mismatch distortion introduced into a hetero interface of a conventional HCMOS device.

[Explanation of symbols]

 Reference Signs List 10 Si substrate 11 p well 12 n well 13 Si layer 14 SiGeC layer 15 SiGe layer 16 source / drain region 17 Si layer 18 gate electrode 19 gate insulating film 21 source / drain electrode 25 source / drain contact W layer 30 Si substrate 31 p Well 32 n-well 33 first Si layer 34 SiGeC layer 35 second Si layer 36 SiGe layer 37 third Si layer 38 gate electrode 39 gate insulating film 41 source / drain electrode 42 source / drain region 45 source / drain contact W layer 50 Si substrate 51 n p-well 51 pn-well 52 SiGe buffer layer 53 δ-doped layer 54 spacer layer 55 i-Si layer 56 i-Si1-xGex layer 57 i-Si layer 58 gate insulating film 59 source / drain region 61 Source Drain contact W layer 63 Al source / drain electrode 65 Gate electrode 66 First insulating film 67 n-channel 68 p-channel

──────────────────────────────────────────────────続 き Continuing on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/778 29/78 29/812 (72) Inventor Yu Ueno 1006 Odakadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Yasuhito Kubuchi 1006 Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-6-140435 (JP, A) JP-A-5-114708 (JP, A) JP-A-5-218096 (JP, A) International Electron Devices Meeting. Technical Digest 1996, USA, December 8, 1996, P 261-264 (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/092 H01L 21/8238 H01L 29/78 H01L 21/336 H01L 29/812 H01L 21/338 H01L 21/06 H01L 21/8232

Claims (11)

(57) [Claims] A field effect transistor formed on a portion of a semiconductor substrate and having a gate electrode, a source / drain region, and a channel region between the source / drain region; A first Si _1-xy Ge _x formed in contact with the Si layer
A C _y layer (0 ≦ x ≦ 1, 0 <y ≦ 1), a second Si layer, and the first Si layer formed in contact with the second Si layer.
_1-xy Ge _x C _y layer second Si _1-xy Ge _x C _y layer having a different band gap and (0 ≦ x ≦ 1,0 ≦ y ≦
1), wherein the first Si _1-xy Ge _x C _y layer has the first
A region close to the Si layer of the second Si _1-xy Ge
The a region proximate to the second Si layer in _x C _y layer, wherein the first and second carrier accumulation layer for confining different conductive carrier to each other are formed Semiconductor device. 2. The semiconductor device according to claim 1 , wherein a composition ratio y of C in said second Si _1-xy Ge _x C _y layer is zero. 3. The semiconductor device according to claim 1 , further comprising a MOS transistor formed on said semiconductor substrate and having a semiconductor layer of a single composition as a channel region. 4. The semiconductor device according to claim 1 , wherein a composition ratio y of C in the first Si _1-xy Ge _x C _y layer is 0.01 to 0.03. Semiconductor device. The semiconductor device according to 5. The method of claim 1, the composition ratio of each element of the first Si _1-xy Ge _x C _y layer, the first Si _1-xy Ge _x C _y Layer and the first S
A semiconductor device characterized in that the composition ratio is adjusted to lattice-match with an i-layer. 6. The semiconductor device according to claim 1 , wherein said first Si _1-xy Ge _x C _y layer is formed of said first Si
A semiconductor device having a lattice constant smaller than a lattice constant of a layer and a film thickness that does not cause lattice relaxation. The semiconductor device according to any one of 7. The method of claim 6, carriers stored in said first carrier accumulation layer are negative carrier, to the second carrier accumulation layer A semiconductor device, wherein the accumulated carriers are positive carriers. The semiconductor device according to any one of claim 8 according to claim 7, said the of the first Si layer within the first Si _1-xy Ge
The area adjacent to the _x C _y layer, wherein a carrier supply layer for supplying carriers to said first carrier accumulation layer is further formed. 9. The semiconductor device according to claim 1, said first and second Si _1-xy Ge _x C _y layer at least one of Si _1-xy Ge _x C _y layer is a quantum well of A semiconductor device, which is an area. The semiconductor device according to any one of 10. The system of claim 1 to 9, Si _1-xy formed above one of the first and second Si _1-xy Ge _x C _y layer A semiconductor device, further comprising a source / drain contact layer formed of a low-resistance conductor film formed directly on a Ge _x C _y layer. 11. A method for manufacturing a semiconductor device having an n-channel field-effect transistor and a p-channel field-effect transistor, comprising: a first Si layer on a semiconductor substrate; And a first Si _1-xy Ge _x so that a first carrier storage layer serving as a channel of the n-channel field effect transistor is provided in a region adjacent to the first Si layer.
A first step of forming a C _y layer (0 ≦ x ≦ 1, 0 <y ≦ 1); a second Si layer on the semiconductor substrate; It has a band gap different from the first Si _1-xy Ge _x C _y layer, a second carrier accumulation layer serving as a channel of the second Si the p- channel field effect in the region close to the layer transistor A second step of forming a second Si _1-xy Ge _x C _y layer (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), and the first and second Si _1-xy Ge _x C Si _1-xy Ge _x C after depositing a conductive film on the _y layer, the patterning the conductor film n- channel field effect transistors and p- channel field effect transistor located above of the _y layer A third step of forming the respective gate electrodes, and a mask using the gate electrodes of the respective transistors as masks. Then, the n-channel field-effect transistor forming region is doped with at least an n-type impurity to a depth reaching the first carrier accumulation layer, and the p-channel field-effect transistor forming region is formed with at least the second carrier. A fourth step of introducing p-type impurities to a depth reaching the storage layer to form source / drain regions of the n-channel field-effect transistor and the p-channel field-effect transistor, respectively. A method for manufacturing a semiconductor device, comprising: