JP3239422B2 - Method for forming connection structure and method for forming electronic material using the method for forming connection structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a connection structure and a method for forming an electronic material using the method for forming a connection structure, and more particularly to a method for forming a connection between a plurality of protrusions of a substrate having a plurality of protrusions. And a method for forming a connection structure. The present invention can be used, for example, as a method for forming a connection structure in a miniaturized and integrated semiconductor device and a method for manufacturing a semiconductor device having such a connection structure.

[0002]

2. Description of the Related Art Heretofore, a so-called self-aligned contact forming method has been known as a method of forming a connection between convex portions of a base having a plurality of convex portions. This technique is used, for example, when forming a connection between gate structures of a semiconductor device.

A conventional technique will be described with reference to FIG. FIG. 2A shows a structure in which a semiconductor substrate is used as a base 1 and a pair of gate electrodes including a gate oxide film 21, a gate material 22, and an offset insulating portion 23 are formed thereon. It is assumed that a contact is made between the two gate electrodes having such a structure. This gate electrode forms a plurality of projections 2 on the base 1. As a typical structure, a gate oxide film 2 made of silicon dioxide is formed on a Si substrate.
1 is formed, polysilicon is used as a gate material 22, and an offset portion 23 is formed by offset SiO ₂ . The gate material 22 may have a so-called polycide structure made of polysilicon and silicon oxide such as tungsten silicide.

As described above, a plurality of projections 2 on the base 1
In order to form a connection structure (contact) between the projections 2, the following self-aligned contact formation technology has been conventionally used. As shown in FIG.
Next, an LDD region is formed, and then, as shown in FIG. 2B, an insulating film 3 is formed on the entire surface by CVD SiO ₂ or the like. The entire surface is etched back to form a sidewall 31 on the side wall of the gate forming the convex portion 2. Performed more source drain formation ion implantation <br/>, impurity diffusion regions 41
To 43 are formed to obtain the structure shown in FIG.

Next, an interlayer film 5 of SiO ₂ or the like is formed by CVD or the like to obtain a structure shown in FIG. Further, a resist pattern is formed, and a resist pattern having a structure in which a region (region on the impurity diffusion region 42) between the protrusions 2 to be connected is opened as shown in FIG. 6 is formed.

Using this resist pattern 6 as a mask, R
Etching is performed by IE or the like, and as shown in FIG.
A structure is obtained in which the base 1 is exposed at the portion 11 where the connection is to be formed.

The structure shown in FIG. 2G is obtained by removing the resist 6.

Next, an electrode material such as polysilicon (or aluminum, an aluminum alloy, or another wiring material in some cases) is formed thereon and patterned to form a required electrode pattern 7. As a result, FIG.
(H) The wiring structure (electrode structure) is obtained.

In the above prior art, a contact can be formed at a required portion (exposed portion 11) of the substrate 1 in a self-aligned manner, but an interlayer film from the shoulder portion on the side opposite to the connection portion of the convex portion 2 to the side wall is formed. 5 has a steep rising as shown by reference numeral 51 in FIG. Therefore, after the electrode material is formed and patterned, the electrode material may not be completely removed from the steep side wall 51 of the interlayer film 5, and in this case, the electrode material residue 71 is generated. This causes a short circuit and causes a defect.

As described above, the self-aligned contact is effective in reducing the size of electronic materials such as semiconductor devices, and is particularly effective in reducing the cell size of a memory when applied to a memory element semiconductor. As described above, since the steep side wall is used, the conductive material remains in unnecessary portions when processing an electrode (or wiring or the like), causing a short circuit failure.

[0011]

An object of the present invention is to solve the above-mentioned problems and to form a connection structure in which a connection structure can be formed in a self-aligned manner, and furthermore, it is possible to prevent a material shortage at an unnecessary portion and to prevent a wiring short circuit or the like from occurring. With the purpose of providing
Another object of the present invention is to provide a method for manufacturing an electronic material having such a connection structure.

[0012]

Means for Solving the Problems The invention of claim 1 of the present application achieves the above object by adopting the following constitution.

[0013] That is, the invention of claim 1 of the present application is a method for forming a connection structure for forming a connection between the convex portions of a substrate having a plurality of convex portions, wherein an etching protective film is formed on the substrate. after, the forming the planarization insulating film etching protective film, to correspond to the connecting portion of the base body of the planarization insulating film
After forming an opening by removing a portion of the substrate, an interlayer insulating film is formed on the entire surface, and then a connected portion of the base is exposed by etching, and a conductive material is formed on the exposed portion to form a connection structure. A method of forming a connection structure, which achieves the above object.

The invention of claim 2 of the present application achieves the above object by adopting the following constitution.

That is, the invention of claim 2 of the present application relates to a method of manufacturing a semiconductor device having a connection structure having a connection between the projections of the substrate having a plurality of projections, wherein the substrate has an <br/> after forming the etching protective film, said forming a <br/> planarization insulating film etching protective film, the substrate of the planarization insulating film
After removing the part corresponding to the connected part to form an opening,
It is formed on the entire surface of the interlayer insulating film, thereafter etched by exposing the connected part of the base, a method of manufacturing a semiconductor device characterized by comprising the step of forming a connecting structure by forming a conductive material on the exposed portion Accordingly, the above object is achieved.

[0016]

According to the inventions of the present application, the steep inclination of the side wall is reduced as a result of forming the planarizing insulating film. Therefore, even if a conductive material such as an electrode material is formed thereon and patterned, no remaining material is generated, and occurrence of a short circuit or the like is prevented.

[0017]

Embodiments of the present invention will be described below. However, needless to say, the present invention is not limited by the embodiments.

Embodiment 1 In this embodiment, the present invention is applied to the formation of a miniaturized and integrated semiconductor memory device. In particular, it is possible to reduce the memory self-size and reduce short-circuit failure and the like. This is to prevent the occurrence of defects.

In this embodiment, as shown in FIG. 1, the structure shown in FIG.
This is an example of forming a connection structure by forming an electrode at a portion indicated by reference numeral 11 in (a). As shown in FIG. 1D, after forming an etching protection film 8, a flattening insulating film 9 is formed. And
Thereafter, the connected portion 11 of the base 1 is exposed by etching (FIG. 1H), and a conductive material is formed to form a connection structure.

More specifically, in this embodiment, a poly-Si film (gate material) 22 is formed on a substrate 1 (Si substrate) on which a gate oxide film 21 (SiO ₂ or the like) is formed, and a poly-Si film (gate material) is formed thereon. An offset oxide film 23 is formed of SiO ₂ or the like, and a gate is formed by patterning. The structure is such that an offset oxide film 23 is formed on a gate material 22 made of poly-Si. The structure of FIG. 1A in which a region (shown by a broken line) is formed is obtained.

Next, an insulating film 3 for forming an LDD structure is formed.
(CVD SiO ₂ etc.) is formed on the entire surface of the substrate 1 and FIG.
The structure shown in FIG.

Then, the insulating film 3 is etched back to leave the insulating film 3 only on both side walls of the convex portion 2 to form a sidewall 31.
Ion implantation is performed using the protrusions 2 and the side walls 31 as a mask to form source / drain regions 41 having an LDD structure.
To 43 are formed. Thus, the structure shown in FIG. 1C is obtained.

Next, the etching protection film 8 is made of Si ₃ N ₄
And the like. Further, a flattening film 9 is formed thereon. The flattening film 9 may be a film formed of a material capable of alleviating the step, and may be a reflow film such as BPSG, AsSG, PSG, or the like, or an SiO ₂ film formed by O ₃ TEOS. Thus, the structure shown in FIG. In addition, about a reflow film, reflow is performed. As a result, a smooth flat surface is formed on the substrate surface.

Next, a resist pattern 61 is formed.
The portion other than the portion corresponding to the connected portion 11 of the base 1 is covered. This is the structure shown in FIG.

Next, etching is performed using the resist pattern 61 as a mask. Here, solution etching was performed to remove the planarizing film 9 in the same direction. A buffered hydrofluoric acid solution was used as an etching solution. Alternatively, Si ₃ N
Dry etching with a ₄ / SiO ₂ selectivity may be used. As a result, the structure shown in FIG. 1F in which the planarization film 9 on the connection portion 11 of the base 1 is removed and the etching protection film 8 is etched.

Next, an interlayer film 51 is formed. In this example, a CVD SiO ₂ film was formed to form an interlayer film 51. Thus, the structure shown in FIG. Note that this step may be performed after the etching protection film 8 is removed.

Next, etch back is performed. Thereby, the interlayer nitride film 51 and the silicon nitride serving as the etching protection film 8 are removed, and the structure shown in FIG. 1H in which the connected portion 11 on the surface of the substrate 1 is exposed is obtained.

Finally, a wiring material 7 such as polysilicon is formed and patterned to obtain a wiring structure having electrodes formed thereon as shown in FIG. 1 (i).

According to this embodiment, as a result of the formation of the flattening film 9, there is no steep step, and no electrode material remains. Therefore, short circuit due to material residue does not occur,
A self-aligned contact can be formed.

[0030]

According to the present invention, it is possible to provide a method of forming a connection structure in which a connection structure can be formed in a self-aligned manner, and furthermore, it is possible to prevent the occurrence of a material short-circuit in an unnecessary portion and to prevent the occurrence of a wiring short circuit. Further, a method for manufacturing an electronic material having such a connection structure can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing the steps of Example 1 in order.

FIG. 2 is a sectional view showing steps of a conventional example in order.

[Description of sign]

1 substrate (Si substrate) 2 protrusions (gate) 31 side wall 8 etching protection film (Si ₃ N ₄ film) 9 planarization film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28 H01L 21/3065 H01L 21/768

Claims (2)

(57) [Claims] 1. A method of forming a connection structure to form a connection between the convex portions of the substrate having a plurality of convex portions, after forming an etching protection layer on the substrate, the flat on the etching protective film A portion corresponding to a portion to be connected to a substrate in the planarized insulating film
After removing the opening to form an opening , an interlayer insulating film is formed on the entire surface , then the connected portion of the base is exposed by etching, and a conductive material is formed on the exposed portion to form a connection structure. Method of forming a connection structure. 2. A method for producing a plurality of semiconductor devices having a connection structure having a connection between the convex portions of the substrate having a convex portion, after forming an etching protection layer on the substrate, the etching protection A planarizing insulating film is formed on the film, and a portion of the planarizing insulating film corresponding to a portion to be connected to the substrate;
After forming the opening is removed, the entire surface to form an interlayer insulating film, then etching by exposing the connected part of the base body, comprising the step of forming a connecting structure by forming a conductive material on the exposed portion A method for manufacturing a semiconductor device, comprising: