JP3207254B2 - Semiconductor nonvolatile memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory, and more particularly, to an electrically erasable-programmable read only memory.
Memory, it relates to the page writing look method when simultaneously written multiple bits of hereinafter referred EEPROM).

[0002]

2. Description of the Related Art Conventionally, techniques relating to an EEPROM are described in, for example, Japanese Patent Application Laid-Open No. 62-266797 (Document 1) and Japanese Patent Application Laid-Open No. 2-263005 (Document 2). In the EEPROM, as described in Document 1, the storage capacity of the memory increases with the increase in the degree of integration of semiconductors, and the time required for rewriting one bit or one byte at a time increases,
There are many inconveniences in use. For this reason, a page writing method for shortening the rewriting time by simultaneously rewriting all bits of one row corresponding to several bytes in the row direction in a memory cell matrix in which memory cells are arranged in a matrix has been provided. FIG. 2 shows an example of the configuration. FIG.
FIG. 1 is a schematic block diagram showing an example of a configuration of a conventional EEPROM described in Document 1. This EEPROM is
A memory cell matrix 10 for storing data is provided. The memory cell matrix 10 includes a plurality of word lines WL
₁ has to WL _m and a plurality of bit lines BL ₁ to BL _n,
The electrically rewritable nonvolatile memory cells 11 _{11 to} 11 _mn are connected to the respective intersections, and they are arranged in a matrix. Each memory cell 11 ₁₁ to
11 _mn is a select transistor and a floating gate transistor, respectively.

[0003] Word lines WL ₁ to WL The _m, row address AD ₁ decodes them word lines WL ₁ to WL _m
Are connected to each other. The bit lines BL _{1 to} BL _n are connected to switch means 21 _{1 to} 21.
_The sense amplifier 23 is connected via _n . Switch means 21 ₁ through 21 _n, said switching means 21 ₂₁ to the column decoder 22 for decoding the column address AD ₂
One of 1 _n is selected. The output side of the sense amplifier 23 is connected to an input / output terminal 25 via an output buffer 24 activated by a read signal RD.
Is connected. Further, the input side of the input buffer 26 activated by the write signal WR is connected to the input / output terminal 25, and its output side is connected to the switch means 27 ₁ to 27 ₁ .
It is connected to the temporary storage means 28 ₁ ~ 28 _n via the 27 _n. The switch means 27 _{1 to} 27 _n are one of them.
One is turned on by the output of the column decoder 22. Temporary storage means 28 _{1 ~} 28 _n are turned on by signal STO, through the switch means 29 ₁ ~ 29 _n to OFF operation, are connected to the bit lines BL ₁ to BL _n. When writing a page in this type of EEPROM,
The data input from the input / output terminal 25 is driven by the input buffer 26, and is sequentially written to the temporary storage unit _28j via the switch unit _27j selected by the column decoder 22. After the data writing (input) is finished to the temporary storage unit 28 _j, the write to the memory cell 11 _i1 to 11 _in, the temporary storage means 28 _j is connected to the word line WL _i selected by the row decoder 20 in accordance with the data that was, simultaneously through the switch means 29 _j (during the first write cycle)
Write to.

[0004]

However, in the EEPROM having the above-described structure, writing is performed by biasing the memory cells 11 _{i1 to} 11 _in with a high potential. A high potential difference occurs, causing the following problem. (A) Between adjacent bit lines, and the gate of the word line WL _i, drain a certain bit line BL _j, the bit line B
There is a parasitic field transistor whose source is the bit line BL _{j + 1} or BL _j-1 adjacent to L _j . In a conventional page write operation, a high potential difference occurs between adjacent bit lines depending on write data, the field transistor existing between adjacent bit lines is turned on, and a high voltage for writing turns on the field transistor. Leaks through. Therefore, there is a problem that the potential does not reach a desired potential and writing is insufficient, or current consumption at the time of writing increases. (B) To prevent the field transistor from being adversely affected, the gate length of the field transistor must be
That or wider bit line spacing, but it may be thicker field oxide film, the memory cell 11 _11-1 thereby
It hinders miniaturization and miniaturization of 1 _mn . (C) In order to solve the above-mentioned problems (a) and (b), it is conceivable to use the technique of the memory cell test method described in Document 2 above. In the technique of Document 2, writing of a data pattern for inspecting cell interference, bit line failure, or the like, which is one of the test methods of a memory cell, is performed.
This is a technique in which one word line and one bit line are both placed, and at the same time, the selected / non-selected state is set so that all adjacent memory cells are written so as to have data opposite to that of the memory cell.

However, in this technique, all bit lines selected at the same time are in the same state (high voltage). A plurality of word lines are selected every other word line. This is a special function (test mode) for the purpose of easily writing a certain special data pattern, and cannot write arbitrary data. As described above, since the page writing method of the present invention is significantly different from the page writing method, even if the technique of Document 2 is used, depending on the write data in actual use, a problematic field transistor is formed between adjacent bit lines. However, there is a problem that high voltage leakage cannot be prevented, and it has been difficult to provide an EEPROM which is technically satisfactory. An object of the present invention is to reduce the write voltage and increase the current consumption due to a parasitic field transistor existing between adjacent bit lines, and also to reduce the size of a memory cell by preventing the write voltage from lowering. It is to provide an EEPROM that solves the problem that the conversion is hindered.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor non-volatile memory electrically connected to each of intersections of a plurality of word lines and bit lines. Memory cells in which memory cells are arranged in a matrix, a plurality of temporary storage means for temporarily storing data for writing to the memory cells via the bit lines during a data input cycle, and a nonvolatile memory following the data input cycle. One word line and a plurality of bit lines are selected in accordance with an address in a memory storage cycle, and the plurality of bit lines are divided into a plurality of groups. Page writing means for simultaneously writing the data stored in the memory. The page writing means includes a plurality of switch means connected for each bit line, for connecting / disconnecting between the bit line and the temporary storage means, and a switch means connected for each of the plurality of bit lines. A page selector is provided which controls switching to a connection state at least every other one to form a plurality of groups. In the second invention, the temporary storage means of the first invention is provided for each bit line. Further, in the third invention, the temporary storage means of the first invention is provided for every two adjacent bit lines.

[0007]

According to the first and second aspects of the present invention, E
Since the EPROM is configured, in a page write operation in one nonvolatile storage cycle, one word line and a plurality of bit lines are selected, and a plurality of memory cells connected to their intersection are stored in a temporary storage unit. The stored data is written at the same time. At this time, the combination of the bit lines selected simultaneously by the page selector and the switch means controlled by the page selector operates so that the bit line adjacent to any selected bit line is not selected. That is, at least every other bit line is selected in one page by the page selector and the switch means, and no matter which page is selected, the adjacent bit lines of all the selected bit lines are in a floating state, and the Of the high voltage due to the parasitic field transistor existing in the semiconductor device is practically eliminated. As described above, at the time of page write, the bit line adjacent to the write bit line is in a floating state, so that the adverse effect of the field transistor is substantially eliminated and the size of the memory cell can be reduced. Third
According to the invention, each temporary storage means temporarily stores write data for every two bit lines, and has a function of reducing the circuit scale. Therefore, the above problem can be solved.

[0008]

EXAMPLES First Embodiment FIG. 1 is a block diagram schematic of EEPROM illustrating a first embodiment of the present invention. This EEPROM includes a memory cell matrix 30 for storing data. The memory cell matrix 30 includes a plurality of word lines WL _{1 to} W ₁
Comprising a L _m and a plurality of bit lines BL ₁ to BL _n, they each intersection of connected electrically rewritable nonvolatile memory cells 31 ₁₁ to 31 _mn, respectively, those memory cells 31 _{11-31 mn} are arranged in a matrix.
Each memory cell 31 ₁₁ to 31 _mn are two transistors of the select transistor and the floating gate transistor if example embodiment, is constituted respectively.

[0009] Word lines WL ₁ to WL _m is the row decoder 4
Connected to 0. The row decoder 40 has a row address A
Decodes the D ₁ is a circuit for selecting one of the plurality of word lines WL ₁ to WL _m. Each bit line BL ₁ ~BL
_n is the switch means 41 ₁ to 41
Commonly connected to the sense amplifier 43 via 41 _n . The switch means 41 _{1 to} 41 _n are connected to the column address AD ₂
Are turned on and off by the output of the column decoder 42 which decodes The sense amplifier 43 includes a switch 41
A circuit for amplifying read data from _{1 to} 41 _n ;
An input / output terminal 45 is connected to the output side via an output buffer 44 activated by the read signal RD.

Further, an input side of an input buffer 46 activated by the write signal WR is connected to the input / output terminal 45, and a switch means 47 ₁ to 47 composed of a transistor is connected to the output side. 47 _n via the temporary storage means 4
8 _{1 to} 48 _n are connected. Switch means 47 ₁ ~
47 _n are turned on and off by the output of the column decoder 42. Temporary storage means 48 ₁ to 48 _n is for temporarily storing write data, is composed of a latch circuit or the like, to their respective output sides of, through the switch means 50 ₁ to 50 _n, which is a transistor, Bit lines BL _{1 to} BL
_n are connected respectively. Temporary storage means 48 ₁ to 4
8 _n and a switch for connecting bit lines BL _{1 to} BL _n
Stage 50 ₁ to 50 _n are turned on by the output of the page selector 60 is turned off controlled. The page selector 60 simultaneously controls on / off of every other _{one of the} plurality of switch means 50 ₁ to 50 _n based on the signal STO, and
The L ₁ to BL _n has a function of simultaneously selected every other. Therefore, the memory cells 31 _ij forming one page
Is n / 2. Next, a write operation (1)
The read operation (2) will be described.

[0011] (1) In the case of a read operation the read operation, the output buffer 44 by the read signal RD is activated, the row address AD ₁ is decoded by row decoder 40, a plurality of word lines WL ₁ to W-
One WL _i of L _m is selected. Further, the column address AD ₂ is decoded by the column decoder 42, one bit line BL _j 1 single 41 _j is turned on among the plurality of switch means 41 ₁ to 41 _n is selected. The data stored in the memory cell 31 _ij connected to the selected word line WL _i and bit line BL _j is stored in the bit line BL _j
And the signal is sent to the sense amplifier 43 via the switch means _41j , and is amplified to a logic level by the sense amplifier 43.
Driven by the output buffer 44 and output to the input / output terminal 45.

[0012] (2) write operation The write operation is composed of a data input cycle for inputting data to the temporary storage unit 48 ₁ to 48 _n, write actual data into the memory cell 31 and the nonvolatile memory cycle You. In the data input cycle, the input buffer 46 is activated by the write signal WR, the write data input from the input / output terminal 45 is driven by the input buffer 46, and the switch means 47 turned on by the output of the column decoder 42. through _j, it is sequentially input to the temporary storage unit 48 _j corresponding to the column address AD ₂ input.
In the nonvolatile memory cycle following the data input cycle, two switch means groups 50 ₁ , 50 ₃ ,..., 50 _n−1 and 50 ₂ , 50 ₄ ,. of _n, it is one of the switch means a group in order to select the page corresponding to the column address AD ₂ input is selected, the temporary storage unit 48 _j
And the bit line BL _j are connected. Thus, according to the data stored in the temporary storage means 48 _j, a high voltage is biased to the bit line BL _j. Then, output by selecting one word line WL _i row decoder 40, to the word lines WL _i and the bit line BL _j and the memory cell 31 _ij connected to the intersection of the data writing is performed. In this embodiment, if the write data input to the temporary storage means 48 _j is even data such that all of the bit lines BL ₁ to BL _n to the high voltage, the page selector 60 and switch means 50 ₁ by to 50 _n, 1 because the page is configured to select the one every other bit line BL _j, in a first nonvolatile memory cycle, any bit line BL _j, the adjacent bit line BL j _{+ 1} Alternatively, BL _j-1 is in a floating state, and the parasitic field transistor does not enter a state in which high voltage leakage occurs. Therefore, the leakage current of the high voltage due to parasitic fields Doto La <br/> Njisuta formed between adjacent bit lines during the conventional such page write, can virtually eliminate. In addition, since the field oxide film does not need to be thicker than necessary, it is suitable for miniaturization.

Second Embodiment FIG. 3 is a schematic block diagram of an EEPROM showing a second embodiment of the present invention. The elements common to the elements in FIG. 1 showing the first embodiment are shown in FIG. Common symbols are assigned. In this EEPROM, the temporary storage means 48 _{1 to} 48 shown in FIG.
Instead of _n , temporary storage means 48 ₁₂ , 4 having a different configuration
_{8 34, ..., 48 n-} 1, n are provided one for every two bit lines adjacent having different page. That is, the bit lines BL ₁ and BL ₂ are connected to the switch means 50 ₁ and 50, respectively.
It is connected to the temporary storage 48 ₁₂ through _2. Similarly, the bit lines BL ₃ and BL ₄ are connected to the switch means 50 ₃ and 5
0 ₄ in the temporary storage 48 ₃₄ through the bit line B
L _n-1 and BL _n are connected to temporary storage means 48 _{n-1 and n} via switch means 50 _n-1 and 50 _n , respectively. Each of the temporary storage means 48 ₁₂ , 48 ₃₄ ,.
_{n-1 and n} are configured, for example, similarly to the temporary storage means 48 _n of the first embodiment. In this EEPROM, data reading and writing are performed in the same manner as in the first embodiment. Therefore, in addition to having substantially the same advantages as those of the first embodiment, the number of the temporary storage means 4 is half that of the first embodiment.
With 8 _{j−1, j} , the same effect as in the first embodiment can be realized.
Note that the present invention is not limited to the above-described embodiment.
The writing means and reading means PROM, or constituted by circuits other than FIGS. 1 and 3, or the switch means 50 ₁ to 50 _n that are controlled by the page selector 60, a temporary storage unit 48 ₁ to 48 _n, 48 ₁₂ ~ 48 _{n-1, n} , etc., and various modifications are possible.

[0014]

As described above in detail, according to the first and second aspects, a plurality of memory cells connected to an intersection of a selected one word line and a plurality of bit lines are provided. At the time of a page write operation for simultaneously writing data, at least every other bit line is selected for one page. Therefore, at the time of page write, a parasitic field transistor formed between adjacent bit lines causes a high level. Voltage leakage current can be virtually eliminated. further,
Since the field oxide film does not need to be thicker than necessary,
The degree of integration can be improved by miniaturizing the memory cell. According to the third aspect, the temporary storage means is provided for every two adjacent bit lines. Therefore, the same effect as in the first and second aspects can be obtained with half the number of temporary storage means of the second aspect. It can be realized and the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration block diagram of an EEPROM showing a first embodiment of the present invention.

FIG. 2 is a schematic block diagram of a conventional EEPROM.

FIG. 3 is a schematic block diagram of an EEPROM showing a second embodiment of the present invention.

[Explanation of symbols]

30
Memory cell matrix 31 _{11 to} 31 _mn
Memory cell 40
Row decoders 41 _{1 to} 41 _n , 47 _{1 to} 47 _n , 50 ₁ to 50 _n
Switch means 43
Sense amplifier 44
Output buffer 45
I / O terminal 46
Input buffer 42
Column decoders 48 _{1 to} 48 _n
Temporary storage means 60
Page selector BL ₁ ~BL _n
Bit lines WL _{1 to} WL _m
Word line

Claims (3)

(57) [Claims] A memory cell matrix in which electrically rewritable nonvolatile memory cells connected to respective intersections of a plurality of word lines and bit lines are arranged in a matrix; A plurality of temporary storage means for temporarily storing data to be written into a memory cell during a data input cycle; and selecting the one word line and the plurality of bit lines according to an address in a nonvolatile storage cycle following the data input cycle. And the plurality of bit lines are connected to a plurality of glues.
Divided into up to a simultaneous writing page writing unit stored data in the temporary storage means to a plurality of memory cells connected to the divided groups, the
Page write means, connected to said each bit line, and a plurality of switch means for connecting / blocking between said temporary storage means and said bit line, the connected switch means for each of the plurality of bit lines Switching control to a connection state at least every other one ,
A page selector constituting a plurality of groups respectively, semiconductor nonvolatile memory and having. 2. A memory cell matrix in which electrically rewritable nonvolatile memory cells connected to respective intersections of a plurality of word lines and bit lines are arranged in a matrix. A plurality of temporary storage means for temporarily storing data to be written into a memory cell during a data input cycle; and selecting the one word line and the plurality of bit lines according to an address in a nonvolatile storage cycle following the data input cycle. And the plurality of bit lines are connected to a plurality of glues.
Divided into up to a simultaneous writing page writing unit stored data in the temporary storage means to a plurality of memory cells connected to the divided groups, the
Page write means, connected to said each bit line, and a plurality of switch means for connecting / blocking between said temporary storage means and said bit line, the connected switch means for each of the plurality of bit lines Switching control to a connection state at least every other one ,
A semiconductor nonvolatile memory, comprising: a page selector configuring each of a plurality of groups ; wherein the temporary storage unit is provided for each of the bit lines. 3. A memory cell matrix in which electrically rewritable nonvolatile memory cells connected to respective intersections of a plurality of word lines and bit lines are arranged in a matrix. A plurality of temporary storage means for temporarily storing data to be written into a memory cell during a data input cycle; and selecting the one word line and the plurality of bit lines according to an address in a nonvolatile storage cycle following the data input cycle. And the plurality of bit lines are connected to a plurality of glues.
Divided into up to a simultaneous writing page writing unit stored data in the temporary storage means to a plurality of memory cells connected to the divided groups, the
Page write means, connected to said each bit line, and a plurality of switch means for connecting / blocking between said temporary storage means and said bit line, the connected switch means for each of the plurality of bit lines Switching control to a connection state at least every other one ,
A non-volatile semiconductor memory, comprising: a page selector respectively configuring a plurality of groups ; wherein the temporary storage unit is provided for each of the two adjacent bit lines.