JP3196756B2 - Semiconductor integrated circuit measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit measuring device applied as a function testing device for a logic LSI or the like.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit measuring device is applied, for example, as a function test device for a logic LSI or the like. Note that a test system to which the above-described function test apparatus is related is constructed especially for a logic verification test of a logic LSI composed of CMOS and BICMOS.

As measures against noise at the time of measuring such an LSI, generally, the capacitance of a bypass capacitor is optimized, the inductance of a power supply / GND line is reduced, and a clamp circuit is connected near an LSI tester driver and a comparator. For example, a method of suppressing the fluctuation of the output waveform of the device under test is performed.

[0004] As a conventional example similar to the present invention in the technical field, there is a "tester diagnostic correction apparatus" disclosed in Japanese Patent Application Laid-Open No. Sho 61-225671. This conventional example is provided with a tester diagnostic device that detects a timing shift and a voltage level of an input / output signal in an input / output unit of a device under test and determines the magnitude and level of the shift. The timing and the voltage level are adjusted on the tester side based on the judgment data by the tester diagnostic device.

This conventional example relates to correction and calibration of a measuring instrument. Therefore, the configuration is basically different from the present invention in which the tester driver level is corrected in real time at the time of measurement.

[0006]

SUMMARY OF THE INVENTION However, LSI
Increasing the scale and power of electricity are moving in the direction of expansion,
The performance as a test device is not sufficient with only the above-mentioned conventional method. In particular, in the measurement on the wafer, it is not easy to reduce the inductance and the capacitance parasitic on the test circuit due to the structure of the tester jig.

The disadvantage of the above conventional method is that the LS
In a situation where an I-device is used, the power supplies, particularly GND, between devices that transmit and receive signals are closer to each other than when testing with an LSI tester. These requirements are not sufficiently considered to be sensitive to each other. Therefore, for example, even if the threshold potential to the device at the input stage fluctuates due to the fluctuation of the potential of the GND line, the level of the input signal to the device under test is constant. As a result, an unexpected signal was input in a pseudo manner, which caused the device to malfunction,
There is a problem that a good product is erroneously determined as a defective product in the test.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit measuring device which is closer to the actual use condition and is resistant to noise.

[0009]

In order to achieve the above object, a semiconductor integrated circuit measuring apparatus according to the present invention comprises a tester driver for driving a device to be measured and a monitor which captures the potential of a power supply sense line on a power supply line in real time. In addition, the power supply side potential correction circuit whose output terminal is connected to the signal line, and the signal of the GND sense line on the GND line near the device are captured and monitored in real time, and the output terminal is connected to the signal line. A potential correction circuit on the GND side, wherein when the potential of the monitored power supply or GND exceeds and / or falls below a predetermined reference potential, the output potential of the tester driver is corrected. I have.

Further, the above-mentioned semiconductor integrated circuit measuring device is
The power supply unit may further include a power supply unit for driving the device under test, and the power supply sense line and the GND sense line may be a power supply sense line and a GND sense line for supplying power from the power supply unit to the device under test.

Further, the power-supply-side potential correction circuit has, as input signal terminals, an IO signal, a DRV signal, a power-supply-side detection reference line, and a power-supply-side correction reference line, in addition to the power supply sense line. The GND side potential correction circuit includes an IO signal, a DRV signal, and a GND signal in addition to the GND sense line.
It is preferable to have a side detection reference line and a GND side correction reference line as input signal terminals.

Note that the above-mentioned GND side potential correction circuit includes a G
A comparator having an ND sense line and a GND side detection reference line as input signals, a logic circuit having an input of the output of the comparator, an IO signal and a DRV signal, and a diode bridge; Two constant current sources connected to two opposing points of the diode bridge, the other opposing first to the GND-side correction reference line, and the second to the signal line via a predetermined switch. It is good to be configured.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a semiconductor integrated circuit measuring apparatus according to the present invention will be described in detail with reference to the accompanying drawings. 1 to 5, there is shown a diagram for explaining a configuration of an embodiment of a semiconductor integrated circuit measuring device of the present invention.

FIG. 1 conceptually shows the configuration of a semiconductor integrated circuit measuring apparatus according to the present invention. Particularly, a device interface portion of an LSI logic test system as one embodiment is shown. The interface unit includes a tester driver 1, a comparator 2, a power supply unit 3, a signal line 4 for connecting a device under test, a power supply line 5, a GND force line 6, a power supply sense line 7, a GND sense line 8, a bypass capacitor 9, Is configured.

In this configuration, the second power supply sense line 10 provided according to the present invention is
Is applied to the power supply side potential correction circuit 12 in real time. The power supply-side potential correction circuit 12 has, as input terminals other than the second power supply sense line 10, an IO signal 14, a DRV signal 15, a power supply-side detection reference line 16, and a power supply-side correction reference line 17. , Its output terminal is connected to the signal line 4.

Similarly, the second GND sense line 11
, The signal on the GND sense line 8 in real time,
It is applied to the ND side potential correction circuit 13. The GND-side potential correction circuit 13 includes, as input terminals other than the second GND sense line 11, an IO signal 14, a DRV signal 15, a GND-side detection reference line 18, and a GND-side correction reference line 1.
9, the output terminal of which is connected to the signal line 4.

Here, the IO signal 14 and the DRV signal 15 are
This is a signal for controlling the tester driver 1, and is a digital signal generated inside the tester. The IO signal 14 is at "0" level when the tester driver enable is off, and is at "1" level when it is on.
The DRV signal 15 is at the “0” level when the drive potential of the tester driver 1 is at the “0” level, and is “1”.
In the case of the level, it is the “1” level.

Here, the configuration of the GND side potential correction circuit 13 will be described in detail. Power supply side potential correction circuit 12
Is an equivalent circuit configuration.

FIG. 2 is a circuit diagram showing the GND potential correction circuit 13 shown in FIG.
3 shows an example of the detailed configuration. 2, the GND-side potential correction circuit 13 includes a second GND sense line 11,
Comparator 20 having ND side detection reference line 18 as input
And the output signal of the comparator 20, the IO signal 14, the DRV
A NAND 21 having a signal 15 as an input, and a diode bridge 22 including four diodes a, b, c, and d
, Two constant current sources 23 and 24 connected diagonally to the diode bridge 22, and G connected to the other diagonal.
An ND-side correction reference line 19 and a switch 25 are provided. The other end of switch 25 is signal line 4
The on / off control signal of the switch 25 is the output of the NAND 21 described above. The logic of the switch 25 is on at the control signal “1” level and off at the “0” level.

Here, the potential of the GND side detection reference line 18 is set lower than the GND potential. The comparator 20 compares the potential of the second GND sense line 11 with the potential of the GND side detection reference line 18, while the potential of the second GND sense line 11 is lower than the potential of the GND side detection reference line 18. The output becomes "0" level.

On the other hand, in the diode bridge 22,
The two constant current sources 23 and 24 are set to the same current value, and the current value is larger than the current supply capability of the tester driver 1. Diode bridge 22
The potential at the point A between the switch and the switch 25 is maintained at the same potential as the GND-side correction reference line 19. The current supplied from the constant current source 23 has a path flowing from the diode a to the diode c and a path flowing from the diode b to the diode d, and all flows into the constant current source 24. G
The potential of the ND-side correction reference line 19 is set lower than the output LOW potential of the tester driver 1.

A point on the GND line near the device is a G_GND point, and a point on the power supply line is D_VDD.
A point on the GND line of the entire LSI test system is defined as an S_GND point.

(Operation Example) Here, an operation example when the GND side potential correction circuit is applied to the bidirectional terminal will be described with reference to the timing chart of FIG. If a plurality of signal pins of the circuit under test simultaneously change to the LOW level during the function test of the LSI, the supply of current from the GND line cannot keep up with the potential, and the potential D_GND of GND near the device under test
Causes large fluctuations. It is assumed that a large change occurs in D_GND at time t1 of cycle 1. In this case, the tester driver outputs the “0” level in cycle 1.

When the potential at the point D_GND fluctuates and falls below the potential of the GND side detection reference line 18 at time t2, the output of the comparator 20 becomes "0" level. In cycle 1,
IO signal 14 is at "0" level, DRV signal 15 is at "0"
Level. Therefore, the output of the NAND 21 at this time becomes "1" level. As a result, the switch 25 is turned on.
Then, the output potential of the tester driver 1 driving the signal line to the “0” level is higher than the potential of the GND-side correction reference line 19. For this reason, the diode b becomes o
ff, and the diode d, which has been receiving the current supply from the diode b, starts drawing current from the signal line 4.

This state is continued until the potential of the signal line 4 reaches the potential of the GND-side correction reference line 19, and the potential of the signal line 4 changes linearly to the potential of the GND-side correction reference line 19. Even if the signal line 4 reaches the same potential as the GND-side correction reference line 19, D_GND is lower than the potential of the GND-side detection reference line 18. Therefore, the output of the NAND 21 is at the “1” level, and the switch remains on. Thereafter, the diode b turns on again, and the potential of the signal line 4 becomes G
The potential of the ND-side correction reference line 19 is maintained. Then, at time t3, the potential of D_GND becomes higher than the potential of the GND-side detection reference line 18. Therefore, the output of the comparator 20 becomes “1” level, the output of the NAND 21 becomes “1” level, and the switch is turned off. Thus, the potential of the signal line 4 changes to the output potential of the tester driver 1.

At time t4, the potential of D_GND again falls below the potential of the GND side detection reference line 18. Therefore, the switch is turned on, and the potential of the signal line 4 approaches the potential of the GND-side correction reference line 19. However, before the potential reaches the potential of the GND side correction reference line 19, the potential of D_GND becomes higher than the potential of the GND side detection reference line at time t5. Therefore, the switch 25 is turned off. Thus, the potential of the signal line 4 changes to the output potential of the tester driver 1.

Next, at time t6 of cycle 2, D
The operation when a large fluctuation occurs in _GND will be described. In cycle 2, the tester driver 1 outputs the “1” level. When the potential of D_GND fluctuates and falls below the potential of the GND-side detection reference line 18 at times t7 to t8 and t9 to t10, the output of the comparator 20 goes to the “0” level. However, in cycle 2, the IO signal 14 is at "0" level and the DRV signal 15 is at "1" level.
Therefore, the output of the NAND 21 goes to the “0” level regardless of the output of the comparator 20. Thereby, the switch 2
5 remains off, and the GND side potential correction circuit 13 does not affect the output of the tester driver 1.

Next, at time t11 of cycle 3, D
The operation when a large fluctuation occurs in _GND will be described. In cycle 3, tester driver 1 is in a high impedance state, and it is expected that the device is outputting some level of voltage. When the potential of D_GND fluctuates and falls below the potential of the GND-side detection reference line 18 at times t12 to t13 and t14 to t15, the output of the comparator 20 becomes “0” level. However, in cycle 3, I
The O signal 14 is at the “1” level, the DRV signal 15 is at the “1” or “0” level, and the output of the NAND 21 is at the “0” level regardless of the output of the comparator 20. As a result, the switch 25 remains off, and the GND side potential correction circuit 13 does not affect the output level of the device.

As described above, the tester driver 1 drives the “0” level and the GN near the device
Only when the D potential drops by a certain amount or more, the tester driver 1
Can be corrected, and there is no effect at the time of device output or "1" level drive.

The power supply side potential correction circuit 12 also has a GN
It operates in the same manner as the D-side potential correction circuit 13, and only when the tester driver 1 drives the “1” level and the power supply potential near the device rises by a certain amount or more,
Can be corrected, and has no effect at the time of device output or driving at the “0” level.

FIG. 4 is a potential waveform diagram for explaining an operation example. FIG. 4 shows the relationship between the ground potential, the reference signal potential, the input stage threshold potential, and the corrected signal wiring potential.

As shown in FIG. 4, when a plurality of signal pins of the circuit under test simultaneously change to the LOW level at the time t1 during the function test of the LSI, the current supply from the GND line cannot keep up and the device under test The potential D_GND of the nearby GND causes a large fluctuation. With the change in the potential of GND, the threshold potential VthL of the input stage of the device under test decreases. At this time, when the tester driver inputs a “0” level signal, its potential is constant regardless of the potential of D_GND. For this reason,
If the threshold potential is “0” of the tester driver
When the potential falls below the level, this is equivalent to the input of the signal of the “1” level, and a situation in which a malfunction is likely to occur occurs.

Here, as the GND level in the vicinity of the device decreases, the potential of the driver outputting the "0" level is lowered, so that the LSI under measurement hardly malfunctions, and a measurement system which is resistant to noise is provided. Can be realized. Similarly, the potential D_VDD of the power supply near the device to be measured increases, and the threshold potential VthH
Is increased, the potential of the driver is increased.
This makes it difficult for the LSI under measurement to malfunction, thereby realizing a measurement system resistant to noise.

According to the above embodiment, in a test system constituted by an LSI logic tester used for a logical function test of a semiconductor integrated circuit and a tester jig for connecting the LSI logic tester and a device to be measured, The tester jig and the LSI logic tester have a signal line for monitoring the power supply or GND potential near the device to be measured, and correct the driver signal level from the tester to the device to be measured in real time according to the monitored potential. Function is provided.

FIG. 5 shows a device interface portion of an LSI test system according to the present invention, showing a connection portion between an LSI tester, a tester jig and a device to be measured. According to FIG. 5, the present invention is applied to a configuration including an LSI tester driver 1, a comparator 2, a power supply unit 3, signal wiring for connecting them to a device under test, power supply wiring, GND wiring, and a bypass capacitor. , The second power supply sense line 10 and the second GND sense line 8 connected to the power supply or the GND sense line.
And a power-supply-side potential correction circuit 12 and a GND-side potential correction circuit 13. With this configuration, the power supply or the GND potential near the device to be measured is monitored, and the level of the driver is corrected in synchronization therewith.

The potential correction circuits 12 and 13 perform an operation of correcting the output potential of the tester driver 1 when the potential of the power supply or GND monitored by the sense line exceeds or falls below a certain reference potential. Execute.

Therefore, when the threshold voltage of the device input stage fluctuates due to fluctuations of the power supply or the GND potential during device measurement, a logical malfunction is prevented by temporarily correcting the output level of the tester driver 1. The effect is obtained.

The above embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this.
Various modifications can be made without departing from the spirit of the present invention.

[0039]

As is apparent from the above description, the semiconductor integrated circuit measuring apparatus of the present invention provides a tester driver when the potential of the monitored power supply or GND exceeds and / or falls below a predetermined reference potential. Is corrected. This correction makes it possible to prevent a logical malfunction when the threshold potential of the device input stage fluctuates due to fluctuations in the power supply or GND potential during device measurement. As a result, occurrence of erroneous measurement and erroneous determination can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit measuring apparatus according to the present invention.

FIG. 2 is a circuit diagram illustrating a detailed configuration example of a GND-side potential correction circuit in FIG. 1;

FIG. 3 is a timing chart for explaining an operation example.

FIG. 4 is a potential waveform diagram for explaining an operation example.

FIG. 5 is a diagram showing a device interface portion of an LSI test system to which the semiconductor integrated circuit measuring device according to the embodiment is applied.

[Explanation of symbols]

 Reference Signs List 1 (LSI) tester driver 2 Comparator 3 Power supply unit 4 Signal line 5 Power supply line 6 GND force line 7 Power supply sense line 8 GND sense line 9 Bypass capacitor 10 Second power supply sense line 11 Second GND sense line 12 Power supply side potential correction circuit DESCRIPTION OF SYMBOLS 13 GND side electric potential correction circuit 14 IO signal 15 DRV signal 16 Power supply side detection reference line 17 Power supply side correction reference line 18 GND side detection reference line 19 GND side correction reference line 20 Comparator 21 NAND (logic circuit) 22 Diode bridge 23, 24 Constant current source 25 Switch

Claims (6)

(57) [Claims] 1. A tester driver for driving a device under test, a power supply-side potential correction circuit for capturing and monitoring the potential of a power supply sense line on a power supply line in real time, and having an output terminal connected to a signal line; A GND-side potential correction circuit whose output terminal is connected to the signal line and which monitors and captures a signal of a GND sense line on a nearby GND line in real time; A semiconductor integrated circuit measuring device for correcting the output potential of the tester driver when the potential of the tester driver exceeds and / or falls below a predetermined reference potential. 2. The semiconductor integrated circuit measuring apparatus further includes a power supply unit for driving the device under test, wherein the power supply sense line and the GND sense line are connected to a power supply supplied from the power supply unit to the device under test. 2. The semiconductor integrated circuit measuring device according to claim 1, wherein the device is a power supply sense line and a GND sense line. 3. The power-supply-side potential correction circuit has an IO signal, a DRV signal, a power-supply-side detection reference line, and a power-supply-correction reference line as input signal terminals in addition to the power supply sense line. 3. The semiconductor integrated circuit measuring device according to claim 1, wherein: 4. The GND-side potential correction circuit includes:
In addition to the D sense line, an IO signal, a DRV signal,
The semiconductor integrated circuit measuring device according to claim 1, further comprising an ND-side detection reference line and a GND-side correction reference line as input signal terminals. 5. The GND-side potential correction circuit includes:
A comparator using the D sense line and the GND side detection reference line as input signals, and an output of the comparator and the I
5. The semiconductor integrated circuit measurement device according to claim 4, further comprising a logic circuit that receives the O signal and the DRV signal as input signals. 6. The GND-side potential correction circuit includes: a diode bridge; two constant current sources connected to two opposing points of the diode bridge; and a first opposing GND-side correction circuit. 6. The semiconductor integrated circuit measuring device according to claim 5, wherein a reference line is connected, and a second is connected to the signal line via a predetermined switch.