JP3191733B2 - Feedback delay control type GTL bus driver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a GTL driver, and more particularly, to a high-speed bus driver circuit.

[0002]

2. Description of the Related Art For high-speed signal transmission, it is necessary to adjust a slew rate. For example, JP-A-7-1
Japanese Patent No. 22992 proposes a configuration of a bus driver that allows a signal slew rate to be adjusted in multiple stages from an external pin by using a delay circuit capable of adjusting the delay time in multiple stages.

However, driving a low-impedance load requires a driver having a high driving capability. As the driving capability increases, power consumption increases, and noise (such as ground bounce) generated during a transition increases. was there.

As one of the bus drivers for solving this problem, for example, Japanese Patent Laid-Open Publication No. Hei 4-225275 discloses a GTL (Gunning Tranceiver Logi) as shown in FIG.
c) A bus driver has been proposed. Referring to FIG. 3, the bus driver includes an N-channel transistor 25 having an open drain buffer output, and a feedback circuit 51 formed by N-channel transistors 52 and 53.

When the input 29 is changed from Low (0) to High
When switching to (1), that is, when the N-channel transistor 25 in the output stage changes from low to high,
The feedback formed by the transistors 52 and 53 prevents the level of the drain voltage of the transistor 25 from reaching the final voltage (termination voltage) for a certain period of time, and suppresses the discharge current during the transient of the driver, thereby preventing overshoot and overshoot. After suppressing the ground bounce and finally delaying the buffer formed by the inverters 56 and 57, the gate voltage of the feedback transistor 53 becomes low.
(0) turns off the transistor 53
(Inactive), the output of the driver becomes the final voltage value (1.2 V). Incidentally, in FIG.
Is a transmission line, 21 and 22 are termination resistors, 41 and 44 are inductances, and 42, 43, 45, 46 and 48 are capacitances.

As described above, in the GTL driver, the noise is reduced, and the use of the open drain buffer makes it possible to reduce the power consumption when the output is High (1). Suitable for driving high-speed buses.

[0007]

However, the above-mentioned conventional GTL circuit has a problem that the feedback delay time cannot be adjusted.

The reason is that the GTL circuit is provided with a feedback circuit for the purpose of preventing overshoot at the time of rising, and realizes a high-speed bus by setting the feedback amount and time to appropriate values. This is because the feedback time differs depending on the length, and if the design is not changed so as to obtain the optimum feedback time according to the applied device, the waveform distortion increases.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to make it possible to adjust the delay time of feedback from the outside so that high-speed signals can be transmitted on buses having various physical configurations. An object of the present invention is to provide a bus driver circuit that enables transmission.

[0010]

To achieve the above object, the present invention provides an output transformer for a GTL bus driver circuit .
The output transistor is inserted between the input and output of the
Signal obtained by delaying the input signal input to the
And the input signal input to the output transistor
On and off controlled by complementary signals
Feedback circuit including at least two switch elements
Wherein the delay circuit is the delay time, the delay circuit
Ru Tei is a structure <br/> formed to be variably set by the value of the control signal supplied to the.

[0011]

Embodiments of the present invention will be described. In a preferred embodiment of the GTL bus driver of the present invention, an open-drain output transistor (1 in FIG. 1) having an inverted signal of an input signal as a gate input
2) and a switching element (transistors 10 and 11 in FIG. 1) inserted between the drain and gate of the output transistor
And a delay element whose delay time is variably set by a combination of a logic state of a control signal to be input and a delay output that constitutes the feedback circuit. The delay circuit (11 in FIG. 1) input to the control terminal (FIG. 1)
6) and inputting the input signal to a control terminal of another switch element (10 in FIG. 1) constituting the feedback circuit.

In a preferred embodiment of the GTL bus driver of the present invention, the feedback time can be controlled from the outside, so that the design is not changed every time the device is developed, and the optimal feedback time is adjusted according to the physical configuration. Can be set.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, this embodiment includes an input terminal 1
, An inverter 9, a feedback circuit 5, a delay circuit 6 for controlling the feedback time, an N-channel transistor (output transistor) 12, and an output terminal 1.
3, a transmission line load 14 to be driven, and a pull-up resistor 15
Vt is an output termination voltage. The feedback circuit 5 includes N-channel transistors 10 and 11, and the N-channel transistor 1
The output of the delay circuit 6 is connected to one gate.

The delay circuit 6 delays the signal input to the terminal 7 by a delay amount selected by the external control terminals S1 and S2 by using a known delay control method / method. Is transmitted to

Here, the operation of the delay circuit 6 will be described in detail. The delay amount can be controlled in four stages by a combination of the logic states of the control terminals S1 and S2. When Sl and S2 are Low and Low, the delay circuit output 8 is Δt minutes from the input 7 When S1 and S2 are Low and High, the signal is delayed by 2 × Δt (double the delay amount when Low and Low) with respect to the input 7, and when S1 and S2 are High and When the signal is Low, the input 7 is delayed by 3 × Δt, and when S1 and S2 are High, the signal is delayed by 4 × Δt.

Next, the operation of this embodiment will be described.

The signal input from the input terminal 1 is Low.
At (0), the output N-channel transistor 12 is connected via the inverter 9, so that the gate voltage is Hi.
gh, it becomes active (conductive state), and the output terminal 13 is set to Low (0). At this time, since the N-channel transistor 11 of the feedback circuit 5 is also connected via the inverter 9, the gate voltage becomes Hi.
gh (1) and becomes active (conductive state).

The N-channel transistor 10 is inactive (non-conductive) because the gate voltage is Low (0).

Next, when the voltage input from the input terminal 1 is H
When switching to high (1), N
The gate voltage of the channel transistor 12 is set to Low (0)
Try to lower it.

However, since the resistance between the source and the drain of the inverter 9 is larger than that of the other transistors, the N-channel transistor 10 becomes active, and most of the discharge current of the gate capacitance of the transistor 12 is reduced by the feedback loop. , 11,
It flows between the drain and the source of the transistor 12.

When the gate voltage of the transistor 12 decreases, the potential of the output terminal 13 increases.
Due to the feedback loop created by 0 and 11, the output terminal 13 does not become the final voltage Vt but the initial voltage Va (FIG. 2).
See also).

When the N-channel transistor 11 becomes inactive (non-conducting state), the feedback loop breaks, and the voltage at the output terminal 13 becomes the final voltage value Vt.

Since the time ΔT during which the feedback loop is cut off can be controlled by the external terminals S1 and S2, if the initial delay value (the propagation delay of the inverter 9) Δt0, then S1 = L, S2 = L: ΔTl = ΔtO + Δt, S1 = H, S2 = L: ΔT2 = ΔtO + 2 × Δt, S1 = L, S2 = H: ΔT3 = ΔtO + 3 × Δt, S1 = H, S2 = H: ΔT4 = ΔtO + 4 × Δt, As shown in FIG. 2, the output waveform obtained is a rising waveform in which the feedback time is varied in four stages.

[0024]

As described above, according to the present invention,
There is an effect that high-speed signal transmission can be performed according to buses having various physical configurations. The reason is that in the present invention, the feedback time can be controlled by providing a delay circuit that can be controlled from the outside.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a GTL bus driver according to one embodiment of the present invention.

FIG. 2 is a diagram showing signal waveforms of a GTL bus driver circuit according to one embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a conventional GTL bus driver circuit.

[Explanation of symbols]

1, 2, 9 input terminal 2, 3 external control terminal 5, 51 feedback circuit 6 delay circuit 7 delay circuit signal input terminal 8 delay circuit signal output terminal 9, 55, 56, 57 inverter 10, 11, 12, 25, 52 , 53, 62 N-channel transistor 13 Output terminal 14 Transmission line 15, 21, 22 Termination resistance 41, 44 Inductance 42, 43, 45, 46, 68 Capacitance 61 P-channel transistor Vt Termination voltage

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (2)

(57) [Claims] 1. An output transistor of a GTL bus driver circuit .
The output transistor is inserted between the input and output of the
A signal obtained by delaying an input signal input to the
Complementary to the input signal input to the output transistor
On and off are controlled by the signal of
Both with feedback circuit including two switching elements, wherein the delay circuit is the delay time, the supply of the delay circuit
Formed by a structure which is variably set by the value of the control signal, GTL bus driver circuit, characterized in that. 2. An open-drain output transistor having an inverted input signal as a gate input, a feedback circuit inserted between a drain and a gate of the output transistor and including a switch element, and an inverted signal of the input signal. An input, a delay circuit in which a delay time is variably set by a combination of logic states of control signals to be input, wherein a delay output is input to a control terminal of a switch element constituting the feedback circuit, and the input signal is the input signal. A feedback delay control type GTL bus driver, which is inputted to a control terminal of another switch element constituting a feedback circuit.