JP3185909B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (phase locked loop) circuit for converting a clock from a VCO (Voltage Controlled Oscillator) to a required frequency by a clock generator. The present invention relates to a device that is positioned at the center of the lock range and prevents the lock from being released.

[0002]

2. Description of the Related Art For example, a PLL circuit used for digital processing of a video signal or the like is configured as shown in FIG. This circuit applies a reference signal, for example, a horizontal synchronizing signal from a terminal 1 to a phase comparator 2 and a frequency divider 7
The comparison signal is compared with the phase to output a difference signal voltage corresponding to the phase difference. The difference signal voltage is input to an LPF (low-pass filter) 3 to filter unnecessary frequency components, and is applied to a VCO 4. The oscillation frequency is controlled, the output of the VCO 4 is input to the clock generator 5, converted into a required frequency based on the signal from the control unit 22, generated as a system clock, output from the terminal 6, and at the same time, this clock is A PLL is configured to be input to the frequency divider 7, divided so as to have the frequency of the signal from the terminal 1, and fed back to the phase comparator 2.

[0003] The control unit 22 receives data indicating the lock state from the lock detection unit 21 (for example, lock state: "0, 0",
The clock generator 5 is controlled such that "lock loss due to phase advance:" 1, 1 "and lock loss due to phase delay:" 0, 1 ") always indicate a locked state. That is, the control unit 22 reads a parameter table as shown in FIG. 2 from the lookup table 10, selects a parameter corresponding to the signal from the lock detection unit 21, and sends it to the clock generator 5. 0 to 130, the parameter Q is 0 to 129, P and Q are combined for each table value, the clock from the VCO 4 is multiplied by the parameter P, and the result is divided by the parameter Q, so that the output frequency of the clock generator 5 is approximately 0.1%. Is controlled to change.
However, for example, in FIG.
Despite the fact that a PLL which is desirably locked at 9 MHz is set, it may be locked and may become unstable due to a slight change in the frequency of the input signal. This is because the frequency variable range of the VCO is, for example, ± 0.2%, so that the center frequency of T = 6 (): 15.09 (MHz) The lower limit frequency: 15.0598 (MHz) The center frequency of T = 2 (): 15.03 (MHz) This is because the upper limit frequency is 15.060 (MHz), and locking may occur. This is because the lock detection unit 21 outputs data indicating the lock state even when the lock is at the end of the lock range.

[0004]

SUMMARY OF THE INVENTION In view of the foregoing, the present invention determines a phase state by a control voltage applied to a VCO, selects an appropriate parameter, and controls a clock generator. In order to obtain a stable PLL by locking at the center of the frequency variable width.

[0005]

According to the present invention, there is provided a phase comparator for comparing the phases of an external reference signal and an internal comparison signal and outputting a phase difference signal.
A low pass filter for filtering the input unnecessary frequency component signals from the phase comparator, a voltage controlled oscillator for oscillating a clock of a frequency corresponding to the voltage of the signal from the low pass filter, the voltage controlled oscillator a clock generator for converting the more clocks required frequency output, a frequency divider fed back to the phase comparator to compare the signal by dividing the clock from the clock <br/> click generator, the low pass filter
A / D conversion unit that converts the signal from
And the lock upper limit voltage of the PLL and the lock lower limit of the PLL.
Voltage, PLL upper lock limit and PLL lock lower limit
A storage unit for storing a voltage obtained by dividing a plurality of
Data read from A / D conversion unit from storage unit
A discriminator for discriminating based on the clock generator;
Lookup that stores parameters for output frequency conversion of data
On the basis of the signal from the
Read the corresponding parameter data from the backup table
And the parameter data from the lookup table
A control unit that inputs and controls the clock generator.
And a PLL circuit for controlling a clock generator so as to change an oscillation frequency from a voltage-controlled oscillation circuit based on data from the A / D conversion unit. Further, the clock generator is
It consists of a multiplication parameter (P) and a division parameter (Q)
To convert the output frequency based on the parameters
It is intended to provide a controlled PLL circuit.

[0006]

With the above construction, the PL according to the present invention is provided.
In the L circuit, the control voltage of the VCO is taken out, converted into digital data, and this data is read out from the storage unit and set to the voltage of the lock upper limit and the voltage of the lock lower limit, and between the lock upper limit and the lock lower limit. Compared to voltage , locked at the center or locked at the end
Is determined or not, and based on this determination, an appropriate parameter is selected in a table read from the look-up table and sent to a clock generator to vary the frequency converted by the clock from the VCO. I do.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the PLL circuit according to the present invention will be described below in detail. FIG. 1 is a block diagram of a main part of an embodiment of a PLL circuit according to the present invention. In the figure, reference numeral 1 denotes an input terminal for inputting a horizontal synchronizing signal or the like. Reference numeral 2 denotes a phase comparator which compares the phase of the horizontal synchronizing signal from the input terminal 1 with the phase of the comparison signal from the frequency divider 7 and outputs a difference voltage signal according to the phase difference. Reference numeral 3 denotes an LPF, which filters unnecessary frequency components of the difference voltage signal from the phase comparator 2. A VCO 4 oscillates, for example, a 28.636 MHz clock when the signal voltage from the LPF 3 has a central value. 5 is a clock generator, VC
The clock from O4 is used as the data (multiplication parameter) from the control unit 11.
The frequency is converted into a required frequency based on the meter (P) and the division parameter (Q), and output from the terminal 6. Reference numeral 7 denotes a frequency divider which divides the frequency of the clock from the clock generator 5 to the frequency of the horizontal synchronizing signal input from the input terminal 1 to provide a comparison signal, which is fed back to the phase comparator 2. Reference numeral 8 denotes an A / D converter, which converts the voltage of the difference signal from the LPF 3 into digital data. Reference numeral 9 denotes a storage unit, which is a voltage of a lock upper limit of the PLL,
Lock lower limit voltage of PLL and PLL lock upper limit
And a voltage divided into a plurality of portions between the lock lower limit of the PLL and the lock lower limit of the PLL . A discriminator 10 compares the data from the A / D converter 8 with the data read from the storage unit 9 and compares the data at the center.
Locked, locked at the end, or
Determine if it is out of place . The control unit 11 reads a parameter (multiplication parameter) corresponding to the signal from the determination unit 10 in the parameter table read from the lookup table 12.
(P) and a division parameter (Q)) and sends them to the clock generator 5.

Next, the operation of the PLL circuit according to the present invention will be described. The phase comparator 2 compares the phase of the horizontal synchronization signal from the input terminal 1 with the phase of the comparison signal from the frequency divider 7 and outputs a difference voltage signal according to the phase difference. This difference voltage signal is LPF
3 is input to the VCO 4 to filter out unnecessary frequency components. The VCO 4 oscillates a clock having a frequency corresponding to this voltage and inputs the clock to the clock generator 5. The clock generator 5 outputs data (multiplication parameter) from the control unit 11.
The clock frequency is converted based on the meter (P) and the division parameter (Q), and output from the terminal 6. Said L
The difference voltage signal output from the PF 3 is input to the A / D converter 8.

The A / D converter 8 samples the differential voltage signal from the LPF 3 at the timing of the average value of the signal level, and converts it into digital data. This is for determining the level of the control voltage applied to the VCO 4 from the average value of the difference voltage signal from the LPF 3. For example, the level of the control voltage from the control unit 11 based on the horizontal synchronization signal from the input terminal 1 The difference voltage signal from the LPF 3 may be sampled at the center of the scanning period. The data from the A / D conversion unit 8 is input to the determination unit 10 via the control unit 11, and is compared with the data read from the storage unit 9 via the control unit 11. For example, V
The center of the control voltage of CO4 is 2.5 V, the maximum value is 5 V, the minimum value is 0 V, the lock upper limit voltage of the PLL is 2.8 V, the lock lower limit voltage is 2.2 V, and the data from the A / D converter 8 is In the case of 8 bits, the storage unit 9 stores the lock upper limit voltage data 143 and the lock lower limit voltage data 113. When the data from the A / D converter 8 falls within the range between the upper limit voltage and the lower limit voltage of the lock, the determiner 10 determines that the oscillation frequency of the VCO 4 is substantially at the center of the lock range. I do. Alternatively, the storage unit 9
In, so as to store the voltage obtained by dividing into a plurality between the voltage of the voltage and locking the lower limit of the lock limit, compared with determination unit 10, whether they be locked in the middle, to lock in the end
It may be determined whether or not the user is out of the office .

When the oscillation frequency of the VCO 4 is out of the center of the lock range, the control unit 11 uses a parameter table read from the look-up table 12 to set appropriate parameters (multiplication parameters) corresponding to the signal from the determination unit 10.
(P) and the division parameter (Q)) are again selected and sent to the clock generator 5. Lookup table
12 stores a parameter table as shown in FIG. 2. The control unit 11 reads this parameter table and outputs a signal from the determination unit 10 (corresponding to the control voltage of the VCO 4).
Parameters (multiplication parameter (P) and
And division parameter (Q)) . Crocje
In the Neerator 5, a multiplication parameter is added to the clock from the VCO 4.
Multiply by the meter (P) and then divide by the parameter (Q)
And outputs this to terminal 6 as the output frequency.
You. As a result, the PLL is always locked at substantially the center of the frequency variable range of the VCO 4, and the lock is not easily released even when the frequency of the horizontal synchronization signal from the input terminal 1 fluctuates greatly.

[0011]

As described above, according to the present invention, P
According to the LL circuit, the control voltage applied to the VCO is VC
When the control voltage applied to the VCO is not at the center of the variable frequency range of O, the parameter to be transmitted to the clock generator is switched so that the control voltage applied to the VCO becomes the center voltage. Unlocking does not occur even when the frequency of the signal fluctuates.

[Brief description of the drawings]

FIG. 1 is a main part block diagram of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is an example of a parameter table stored in a lookup table.

FIG. 3 is a main block diagram of an example of a conventional PLL circuit.

FIG. 4 is a diagram for explaining a relationship between a parameter and a lock range.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 Phase comparator 3 LPF 4 VCO 5 Clock generator 6 Output terminal 7 Divider 8 A / D conversion part 9 Storage part 10 Discrimination part 11 Control part 12 LUT (Lookup table)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ^7/ 06-7/199 H04N 5/06

Claims (5)

(57) [Claims] 1. A phase comparator for outputting a signal of phase difference by comparing the phase of the reference signal and the internal comparison signal from the outside, a low-pass filtering the unwanted frequency components enter the signal from the phase comparator a filter, a voltage control oscillator for oscillating a clock of a frequency corresponding to the voltage of the signal from the low pass filter, a clock generator for outputting by converting the clock than the voltage controlled oscillator to the required frequency, the click a frequency divider for the clock from <br/> lock generator by dividing the comparison signal fed back to the phase comparator, the low-frequency Fi
A / D converter that converts the signal from the
Switching part, PLL lock upper limit voltage, PLL lock under
Voltage limit, PLL lock upper limit and PLL lock
A storage unit for storing a voltage divided into a plurality of portions between the lower limit,
The data read from the A / D conversion unit from the storage unit
A discriminator for discriminating based on the clock generator;
To store the parameters for the converter output frequency conversion.
Based on the backup table and a signal from the determination unit.
The corresponding parameter data from the lookup table
Read, parameter data from the same lookup table
Control by inputting a clock to the clock generator
Consists of a part, PLL circuit so as to control the clock generator to vary the oscillation frequency of the voltage controlled oscillation circuit based on the data from the A / D converter. 2. The clock generator according to claim 1, wherein
The parameter consisting of a meter (P) and a division parameter (Q)
Controlled to convert the output frequency based on the meter
2. The PLL circuit according to claim 1, wherein: Wherein the A / D conversion unit, P according to claim 1 or claim 2, wherein was set to convert the signal from the low pass filter at the center of the horizontal scanning period into digital data
LL circuit. Wherein said A / D conversion unit, wherein the signal a signal level of from low pass filter has to be converted into digital data at timing when the average value of the horizontal scanning period
The PLL circuit according to claim 1 or 2 . 5. The A / D converter converts a signal from the low-pass filter into digital data by using a signal output from a controller based on a reference signal from the outside and representing a center of a horizontal scanning period. Claim 1 or Claim to be made
2. The PLL circuit according to 2 .