JP3164576B2 - Display control device and display control method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a display control device and a display control method,
More specifically, for example, a display control device and a display for a display device having a display element that can maintain a display state updated by applying an electric field, using a ferroelectric liquid crystal as an operation medium for changing a display, and the like. It relates to a control method.

[Related Art] Generally, a display device is connected to an information processing system or the like as information display means that performs a visual display function of information. A CRT is widely used as such a display device, and FIG. 10 shows an example of a display control device for a CRT connected to such an information processing device.

In the figure, 1 is an address bus driver, 2 is a control bus driver, 3 is a data bus driver,
Each of them is connected to a system bus 4 for signal connection between devices constituting the information processing system. 5 is a video memory for storing display data transferred via the data bus driver 3, 6 is a driver for transferring data between the display control device and the CRT, and 7 is a CRT.

The video memory 5 is configured by a dual-port DRAM (dynamic RAM), and display data is directly written. The display data written in the video memory 5 is sequentially read out by a CRTC (CRT controller) 8 and displayed on a CRT 7.

That is, when writing the display data, the CPU of the information processing system (not shown) accesses the address of the video memory 5 corresponding to the display area of the CRT 7. First, the access request signal is given to the memory controller 9 via the control bus driver 2, and this signal is sent to the CR.
It receives arbitration with a data transfer request signal or refresh request signal provided from TC8. Accordingly, when the CPU accesses the memory, an address selection signal is supplied from the memory controller 9 to the address selector 10, and an access address for writing data from the CPU is transferred to the video memory 5 via the address driver 1 and the address selector 10. Given to. Accordingly, a DRAM control signal from the memory controller 9 and display data via the data bus driver 3 are given to the video memory 5. Thus, the display data is written to the video memory 5.

On the other hand, the indication on the CRT 7 is that the CRTC 8 supplies a synchronization signal to the driver 6, and in accordance with the synchronization signal, the CRTC 8 supplies a data transfer request signal to the memory controller 9 and a data transfer address to the address selector 10. Is executed by

First, when a data transfer request signal is arbitrated by the memory controller 9 and an address selection signal is provided from the memory controller 9 to the address selector 10 in response to the arbitration, the data transfer address from the CRTC 8 is transmitted to the video via the address selector 10. It is provided to the memory 5. The video memory 5 is supplied with a DRAM control signal from the memory controller 9 to execute a data transfer cycle.
The data transfer cycle is to transfer data in units of lines (corresponding to a raster of a display screen) of the video memory 5 to a shift register in the video memory 5. Line data can be transferred to the shift register.

Then, the display data transferred to the shift register is
In accordance with the serial port control signal from the CRTC 8 applied to the video memory 5, the data is sequentially read from the shift register, output to the CRT 7, and displayed. The reading of display data from the video memory 5 and the accompanying display are performed line by line from the upper part to the lower part corresponding to the display area, and in one line, in a certain order from the left end to the right end. This is performed by a so-called full refresh operation.

As described above, in the case of the CRT display control, the CPU write operation to the video memory 5 and the CRT controller 8
The operation of reading and displaying the display data from the video memory 5 is independently executed.

In the case of the display control device for a CRT as described above, the writing of display data to the video memory 5 for changing display information and the like, and the operation of reading the display data from the video memory 5 and displaying the data are independent. Therefore, the program of the information processing system does not need to consider display timing and the like at all, and has an advantage that desired display data can be written at an arbitrary timing.

On the other hand, a CRT, in particular, requires a certain length of the display screen in the thickness direction, and therefore has a large overall volume, making it difficult to reduce the size of the entire display device. This also impairs the degree of freedom in using the information processing system using such a CRT as a display, that is, the degree of freedom in installation location, portability, and the like.

As a supplement to this point, a liquid crystal display (hereinafter, referred to as LCD) can be used. That is, according to the LCD,
The whole display device can be reduced in size (especially thinner). Among such LCDs, there is a display (hereinafter, referred to as FLCD: FLC display) using a liquid crystal cell of the above-described ferroelectric liquid crystal (hereinafter, referred to as FLC: Ferroelectric Liquid Crystal). The problem is that the liquid crystal cell has a display state preserving property with respect to application of an electric field. Therefore, when driving an FLCD, unlike a CRT or other liquid crystal display, there is time margin in the cycle of continuous refresh driving of the display screen, and apart from the continuous refresh driving, Partial rewrite driving that updates the display state of only the part corresponding to the change on the display screen becomes possible. Therefore, such an FLCD can be a large-screen display as compared with other liquid crystal displays.

Here, the FLCD has a sufficiently thin liquid crystal cell, and the molecules of the elongated FLC in the liquid crystal cell are oriented in a first stable state or a second stable state depending on the direction of application of the electric field, and the electric field is reduced. Even if it is cut, each alignment state is maintained. The FLCD has a memory property due to the bistability of the molecule of the FLC. Details of such FLC and FLCD are described in, for example, Japanese Patent Application
2-76357.

[Problem to be Solved by the Invention] However, the FLCD having the above advantages is replaced with the above-mentioned CR.
When used as a display device of an information processing system with the same display control as T, the time required for the display update operation of the FLC is relatively slow. For example, if the display is not immediately rewritten by cursor, character input, scrolling, etc. In some cases, it is not possible to follow a change in display information that cannot be achieved.

On the other hand, in order to perform this processing by utilizing the fact that partial rewriting, which is one of the features of FLCD, is possible, the information processing system must provide information for identifying this processing. Although there is a configuration for performing the above, in order to realize the above-described partial rewriting drive on the display screen, a significant change in the control program in the information processing system has been required.

The present invention has been made based on the above viewpoints,
Without drastically changing the software of the information processing system,
It is an object of the present invention to provide a display control device such as an FLCD compatible with a CRT.

It is another object of the present invention to provide a display control device capable of realizing optimal image quality by effectively utilizing the preservability of a display state in an FLCD or the like.

[Means for Solving the Problems] The display control device of the present invention is a display control device of a display device capable of partially changing a display state of a pixel, wherein an image storage means for storing an image to be displayed on the display device; Supply means for supplying an image to be stored at a position designated by the address together with an address of the image storage means; address count means for sequentially updating a count value at predetermined intervals; and an address supplied from the supply means. , An address number counting means for counting the number of addresses stored in the address storage means, and scanning lines constituting the display device are sequentially scanned based on the count of the address counting means. The display device is configured based on refresh scanning means and an address stored in the address storage means. Partial scanning means for designating a scanning line to be scanned, switching means for switching between the refresh scanning means and the partial scanning means in accordance with a count value of the number of addresses counted by the address number counting means, The switching unit stops counting by the address counting unit when switching from scanning by the refresh scanning unit to scanning by the partial scanning unit, and switching from scanning by the partial scanning unit to scanning by the refresh scanning unit. And control means for restarting the counting by the address counting means.

According to a display control method of the present invention, in the display control method of a display device capable of partially changing the display state of a pixel, the display control method is specified by the address together with an address of an image storage unit that stores an image to be displayed on the display device. An image to be stored at a position is supplied, the supplied address is stored in an address storage means, the number of addresses stored in the address storage means is counted by an address number counting means, and a scan constituting the display device is provided. A refresh scan for sequentially scanning a line based on a count value of an address count means for sequentially updating a count value at a predetermined interval, and a scan line constituting the display device are designated based on an address stored in the address storage means. Counting the number of addresses counted by the address number counting means. Switching is performed by switching means in accordance with the value.When the switching means switches from the refresh scanning to the partial scanning, the counting by the address counting means is stopped, and when switching is performed from the partial scanning to the refresh scanning, The counting by the address counting means is restarted.

[Operation] According to the present invention, the address at the time of writing an image in the image storage means is stored in the address storage means, and the number of the stored addresses is counted by the address number counting means. Is switched between partial scanning for partial rewriting based on the address stored in the memory and refresh scanning for full rewriting based on the count value of the address counting means for sequentially updating the count value. Further, when the former partial scan is being performed, the count of the address count means for the latter refresh scan is stopped, so that each of the address for the partial scan and the count value of the refresh scan are qualified. To perform partial rewriting and full rewriting reliably.

Examples Hereinafter, the present invention will be described in detail with reference to the drawings.

First Embodiment FIG. 1 is a block diagram of an entire information processing system incorporating a display control device according to an embodiment of the present invention.

In the figure, reference numeral 11 denotes a CP that controls the entire information processing system.
U and 12 are system buses consisting of an address bus, control bus, and data bus, and 13 is for storing programs,
The main memory 14 is used as a work area. A direct memory access controller (DMA) 14 transfers data between the memory and I / O devices without the intervention of the CPU 11.
AC), 15 is L for Ethernet (by XEROX)
LAN interface with AN (local network) 16, I / O device 17 for connecting I / O devices consisting of ROM, SRAM, RS232C interface, etc., 18 hard disk device, 19 floppy disk device, 20 Is a disk interface for a hard disk device 18 or a floppy disk device 19, 21 is a laser beam printer,
A high-resolution printer such as an ink-jet printer; 22, a printer interface for the printer 21; 23, a keyboard for inputting characters such as characters and numerals; and 24, a mouse as a pointing device;
Is an interface for keyboard 23 and mouse 24,
Reference numeral 26 denotes an FLCD (FLC display) which can be configured using a display disclosed by the present applicant in, for example, JP-A-63-243993, and 27 denotes an FLCD interface for the FLCD 26.

FIG. 2 shows an FLCD as an embodiment of the display control device of the present invention.
6 is a block diagram illustrating a configuration example of an interface 27. FIG.

In the figure, 31 is an address bus driver, 32 is a control bus driver, and 33, 43, and 44 are data bus drivers. Address data from the CPU 11 is supplied from the address bus driver 31 to one of the input units of the memory controller 40 and the address selector 35, and is selectively supplied to the FIFO memory 36 or 37 by switching the first switch S1. Stored. That is, these memories 36 and 37 (hereinafter referred to as FIFO (A) and
The FIFO (B) is a FIFO (First In First Out) memory for reading data in the order of writing, and the address data written in these memories 36 and 37 is selected by switching the second switch S2. Is read out.

The address data read from these memories 36 or 37 and the address data from an address counter 38 described later are selectively supplied to the other input section of the address selector 35 by switching a third switch S3. The address counter 38 generates address data for refreshing the entire screen line by line.
The generation timing of the address data is determined by the synchronization control circuit 39.
Is controlled by The synchronization control circuit 39 also generates a switching control signal for the switches S1, S2, and S3 and a data transfer request signal to the memory controller 40 described later.

The control signal from the CPU 11 is given from the control bus driver 32 to the memory controller 40, and the memory controller 40 includes a sampling counter 34,
A control signal for the address selector 35 and a control signal for the video memory 41 described later are generated. Sampling counter
The 34 performs a counting operation based on the step signal from the memory controller 40, and generates a control signal of the synchronization control circuit 39. The sampling counter 34 constitutes address number counting means for counting the number of addresses stored in the FIFO (A) 36 and the FIFO (B) 37 as address storage means. The address selector 35 selects one of the two address data supplied to the input section of the address selector 35 based on a control signal from the memory controller 40 and supplies the selected address data to the video memory 41.

The video memory 41 stores display data,
It is composed of a dual-port DRAM (dynamic RAM), and writes and reads out display data via the data bus driver 33. The display data written to the video memory 41 is transmitted to the FLCD via the driver receiver 42.
Transferred to 26 and displayed. In addition, the driver receiver 42 supplies a synchronization signal from the FLCD 26 to the synchronization control circuit 39. The FLCD 26 incorporates a temperature sensor 26a that detects the temperature of the FLC.

Further, setting data described later from the CPU 11 is provided to the synchronization control circuit 39 via the data bus driver 43. Further, the output signal of the temperature sensor 26a is
Is transferred to the CPU 11 via.

In the above configuration, when the CPU 11 changes the display, the video memory 41 corresponding to the rewriting of the desired data is used.
Is given to the memory controller 40 via the address bus driver 31, and arbitration is performed between the memory access request signal of the CPU 11 and the data transfer request signal from the synchronization control circuit 39. When the CPU access side obtains the right, the memory controller 40
Switches the address selector 35 to select the address accessed by the CPU as the address to be given to the memory 41. At the same time, a control signal for the video memory 41 is generated from the memory controller 40, and data is read and written via the data bus driver 33. At this time, CP
The data is stored in the FIFO (A) 36 or the FIFO (B) 37 via the U access address switch S1, and is used for transferring display data described later. As described above, the access method of the display data as viewed from the CPU 11 is not different at all from the case of the above-described CRT.

When data is read from the video memory 41 and transferred to the FLCD 26, the synchronization control circuit 39 sends the data to the memory controller.
Data transfer request to 40, video memory
Address counter 38 or FI as address for 41
The FO side address is selected by the address selector 35, and a control signal for data transfer is generated from the memory controller 40, so that the data of the corresponding address is transferred from the memory cell to the shift register, and the control signal of the serial port is used. Output to the driver 42.

In the synchronization control circuit 39, the horizontal synchronization signal HSYN
Based on C, a timing is generated to alternately generate a cycle in which the screen is entirely refreshed line by line in units of a plurality of lines and a partial rewrite cycle in which the line accessed by the CPU 11 is rewritten. here,
The full refresh cycle is to sequentially rewrite downward from the top line (top line) on the display screen, and to the bottom line, return to the top line again and repeat rewriting. Things. The access line rewrite cycle is for rewriting a line accessed by the CPU 11 within a predetermined time immediately before the cycle.

As described above, in this example, basically, the operation of sequentially rewriting the entire screen of the FLC display 26 and the operation of rewriting the line accessed by the CPU 11 in order to change the display content are performed in a time sharing manner. Alternately, the repetitive synchronization of these operations and the time ratio of those operations within one cycle can be set, and the operation period of line rewriting (partial rewriting) is controlled by the number of lines accessed by the CPU 11 and the like. Adjust accordingly.

First, a basic operation of the present example in which the refresh operation and the line rewrite operation are alternately performed in a time-division manner will be described with reference to FIG. Here, an example is shown in which a refresh cycle is performed in units of four lines and a rewrite cycle of an access line is performed in units of three lines.

In FIG. 3, REE / ▲ ▼ is a timing at which a full refresh cycle and an access line rewrite cycle are alternately generated. When “1”, the full refresh cycle is performed, and when “0”, the access line is rewritten. Indicates a rewrite cycle. Further, T _a time of the entire surface of the refresh cycle, T _b represents the time of rewriting cycles access lines. In this example, T _a : T _b
= 4: 3, but an optimal value can be selected depending on the required refresh rate and the like. That is, it is possible to increase the refresh rate by increasing the ratio of T _a, it is possible to improve the responsiveness of the partial changes by increasing the proportion of T _b. This aspect will be described later.

To explain the states of the FIFO (A) 36 and the FIFO (B) 37, when the switch S1 is connected to the FIFO (A) 36 side (state
A / = 1), the address of the line accessed by the CPU 11 is F
It is sampled and stored in the IFO (A) 36. On the other hand, when the switch S1 is connected to the FIFO (B) 37 side (A / =
0), line address accessed by CPU11 is FIFO
(B) Stored in 37. Switch S2 is FIFO (A)
When connected to the 36 side (A / = 1), the address stored in the FIFO (A) 36 is output, and the switch S2 switches the FIFO (B) 37
Side (A / = 0), the address stored in the FIFO (B) 37 is output.

When one refresh of the entire screen is completed and the FLCD 26 outputs the vertical synchronizing signal VSYNC or a carry occurs in the address counter 38, the address counter 38 is cleared, and the line output in the next full refresh cycle is Returning to line 0, “1”, “2”, and “2” are output for each horizontal synchronization signal HSYNC supplied from the FLCD 26 via the synchronization control circuit 39.
Counts up sequentially to “3”. During this period, when the addresses of the lines L1, L2, L3 are accessed by the CPU 11, the switch S1 is connected to the FIFO (A) 36, so that L1, L2, L3
Is stored here, and then switch S2 is set to FIFO
(A) At the time of connection to 36, the addresses of L1, L2, L3 are output from here, and L1, L2, L3 are selected as output lines.
Here, the switching signal of the switch S3 is given as RFF / ▲ ▼ from the synchronization control circuit 39, and in the line access cycle, FIFO (A) and FIFO (A) are used as output line addresses.
It is switched to (B) side.

At this time, since the switch S1 is connected to the FIFO (B) 37 side, the access address is stored in the FIFO (B) 37 side. When REF / ▲ ▼ becomes “1”, switch S3
Is switched to the address counter 38 side, and the refresh operation is performed from the line following the previous cycle. In FIG. 3, the lines "4", "5", "6", and "7", which are the continuation of the previous cycle, are output after the line L3 is output. In the same manner as above, the above operation is repeated, but the reason for preparing two FIFOs is to consistently and efficiently perform sampling of an address accessed by memory on one side and outputting the sampled address on the other side at the same time. To do that. That is, during the address sampling period, the other FI
From the start of the output of the FO access line to the end of the full refresh cycle.After the end of the full refresh cycle, the rewrite cycle of the access line that outputs the address sampled in the immediately preceding sampling period is started, and at the same time, the address of the other FIFO is read. The sampling period will be started.

As described above, in the basic operation of this example, the refresh cycle and the line rewriting cycle are alternately repeated, and in FIG. 3, the repetition cycle is set to 7 lines as one unit and T _a : T
_b = 4: has been described as 3, in this example further type of data being environmental conditions and displays such as temperature, or even T _a and the refresh rate or the like which is required according to the difference of the display device material FLCD T The ratio with _b can be changed.
That, T _a (corresponding to the line number M within one refresh cycle. That is T _a = M × (period of HSYNC)) ratio of can be improved refresh rate if the large, for example, low temperature or the like FLC device A good display state can be obtained even when the response is low or when displaying an image image. Conversely, corresponding to the line number N in the ratio (in one partial rewrite cycle T _b. That is T _b = N × (HSYN
If the period of C) is increased, the responsiveness of the partial display change can be increased, and it is possible to cope with a case where the refresh rate does not need to be high, such as at a high temperature or when displaying characters such as characters. Become.

Further, in the present embodiment, the number of lines in the repetition period can also be set, so that the refresh cycle and the rate of partial rewriting can be changed more finely, and more fine optimization can be achieved. For example, if it is necessary to give priority to the refresh rate, or if you want to give it priority, set the number of lines in the repetition cycle to 40.
If T _a : T _b = 4: 1, the entire surface can be refreshed for 32 lines and the access lines can be rewritten for 8 lines. If partial rewriting can be prioritized or prioritized, the number of lines in the repetition cycle is set to 10 and T _a : T _b
Assuming that 3: 2, the access line can be rewritten four times by performing a full refresh for six lines.

Furthermore, in the present embodiment, within the range of the number of partial rewrite lines set as described above, according to the number of lines accessed by the CPU 11 and the line access state,
The actual number P of partial rewrite lines performed between refresh cycles is adjusted. In other words, by adjusting the dynamic T _b time according to the number of lines that CPU 11 accesses, for example, eliminating waste line rewriting cycle when the infrequently accessed from CPU 11, so as to improve the refresh rate. This makes it possible to dynamically optimize the relationship between the operation followability and the refresh rate.

This can be performed, for example, according to the rules shown in the following table.

In Table 1 exemplified, T _b varies with time by the number of access lines of 10 lines from 0 lines. T _b
Decreases, the refresh rate increases and T _b
If the ratio of becomes large, the refresh rate goes down,
Since the limit value is provided as shown in 10 lines (the number of lines set according to the temperature and the like as described above) in Table 1 as an example, a refresh rate equal to or higher than the set value can be maintained. Ie, T the number of the accessed line _a: for changing the ratio of T _b, it is possible to adjust the timing of dynamically optimal partial rewrite, so that further improved the refresh rate.

FIG. 4 shows a signal REF / ▲ which determines the refresh cycle and the partial rewrite cycle by performing the above setting and adjustment.
An example of the internal configuration of the synchronization control circuit 39 for outputting ▼ is shown.

Here, C is a count value of the sampling counter 34, M is a signal indicating a value corresponding to the number of lines in one refresh cycle set via the data bus controller 43 by the CPU 11 according to conditions such as temperature, and N Is a signal indicating a value corresponding to the number of lines in one partial rewrite cycle.

390 is a group of tables storing P values as shown in Table 1 corresponding to the given N values (N1,..., Nn) (the maximum P value in each table is N1,..., Nn, respectively) ), And can be configured using, for example, a ROM. Reference numeral 391 denotes a reference table switching unit for providing the count value input from the sampling counter 34 to a table corresponding to the N value at that time. Then, the value selected from the memory 390 is input to the counter 393 as the transfer line number P. Then, counter 393 counts synchronization signal HSYNC in accordance with the given M value and P value, and outputs signal REF / ▲ ▼.

By the way, in this example, even if the same line is accessed one or more times in one sampling period,
Count as times. That is, if an address given in one sampling period is included in the same line as an address already given in that period, the sampling counter 34 is prevented from being incremented, Only count the number of lines.

FIG. 5 shows an example of a configuration for controlling the counting operation of the sampling counter, for example, a memory controller.
40 can be provided. Here, 401 is an address latch unit that latches an address input during one sampling period, and 403 is a comparison circuit that compares the input address with the address latched in the address latch unit, and the input address is latched. Only when it is not on the same line as any of the addresses, it outputs the step signal of the sampling counter 34.

In the above, the contents of the address latch unit 401 and the sampling counter 34 may be reset at the end of one sampling period. 5 may be performed when the CPU 11 writes data to the video memory 41.

If counting is performed each time the address of the same line is accessed a plurality of times, the configuration shown in FIG. 5 is unnecessary, and if the write signal to the video memory 41 or the number of lines is simply counted. Good.

Next, an example of adjustment of the operation period of the partial rewrite will be described with reference to FIG.

Similarly to FIG. 3, when one refresh of the entire screen is completed and the FLCD 26 outputs a vertical synchronizing signal or a carry occurs in the address counter 38, the address counter 38 is cleared and the next full refresh is performed. The line output in the cycle returns to “0” and counts up sequentially to “1”, “2”, “3” for each horizontal synchronization signal HSYNC. During this time, when the addresses of L1, L2, L3, L4, and L5 are accessed by the CPU 11, the switch S1 is connected to the FIFO (A) 36 side, so the addresses of L1, L2, L3, L4, and L5 are changed to FIFO. (A) Stored in 36. The value of the sampling counter 34 indicates “5”. When the table corresponding to Table 1 is referred to,
When the sampling counter value is "5", the output is P = 4 lines, so when the switch S2 is connected to the FIFO (A) 36, the first four lines L1, L2, L3, L4 are FIFO.
(A) Output from 36, L1, L2, L3, L4 as output lines
Is selected. Here, the switching signal of the switch S3 is REF / AC
Since this is given by S, the address on the FIFO side is selected as the output line address at this time.

At this time, since the switch S1 (A /) is "0", the access address is stored in the FIFO (B) 37 side. When REF / ▲ becomes “1”, the switch S3 switches to the address counter side and continues the previous cycle of the refresh line. In FIG. 6, lines 4, 5, 6, and 7, which are the continuation of the previous cycle, are output after the line L4 is output.

Here, during the access address sampling period of the FIFO (B) 37, the same L6 is accessed only three times.
Since the sampling counter value is "1", in the case of the table corresponding to Table 1, the period of the access address rewriting cycle is "0", and the entire refresh cycle is continuous. Next, the access address sampling period of the FIFO (A) 36 is only during the entire refresh cycle, and two out of three lines sampled during this period.
The line is transferred in the next access address rewrite cycle. Hereinafter, the same operation is repeated, but the lines (for example, L5, L6, and L9) that have not been partially rewritten here are eventually rewritten in the refresh cycle.

Next, operations performed by the above-described units according to the present example apparatus will be described.

FIG. 7 shows an example of the operation procedure.
And lead CPU11 detected value of the temperature sensor 26a at 00A, optimal M value according to step S200B (1 what a number of lines in a refresh cycle defining a T _a)
A set N value (a number of lines in one partial rewrite cycle defines the maximum T _b) to the synchronization control circuit 39.

Next, in step S201, the initial state of the switches S1 and S2 is set. Here, the switch S1 is set to the FIFO (A) 36 side, and the switch S2 is set to the FIFO (B) 37 side. In step S202, the address counter 38 is cleared, and the refresh address is set to an initial value, for example, “0”. Next, in step S203, REF / ▲ is set to “1” so that the entire refresh cycle is performed. Also, a counter for counting the number of transfer lines in one refresh or partial rewrite cycle (here, one refresh cycle) is cleared, and the counter value LN is set to "0".

Next, in step S205, it is determined whether or not the period up to the last line is completed and a carry is generated in the address counter (return period). If the period is during the period, the process returns to step S200A. If it is not during the period, wait for HSYNC to come in step S206. When HSYNC comes, the data of the line indicated by the refresh line address is FL
Transfer to CD26. In step S208, it is determined whether or not the number M of lines to be transferred in one full refresh cycle has been completed. If LN is smaller than M, the process proceeds to step S209, and the address counter 38 is counted up. Is incremented by +1 and the process returns to step S206. This is repeated until the M lines are transferred. Since M = 4 in the alternative shown in FIG. 6, steps S206 to S210 are performed.
Is repeated four times.

When the transfer of the M lines is completed, the number of transfer lines P in the access line rewrite cycle obtained from the set N value and the count value C of the sampling counter 34 in the access line rewrite cycle is referred to in step S219. The rewrite cycle is omitted, and the process proceeds to step S203 to perform the entire refresh cycle again. On the other hand, if P is not "0" in step S219, the process proceeds to step S211 for executing the access line rewriting cycle.

In step S211, REF / ▲ ▼ is set to “0” so that the access line rewrite cycle is performed. Further, the connection states of the switch S1 and the switch S2 are reversed, and the roles of FIFO address sampling and line address output are reversed. Next, in step S212, the counter value LN is set to "0" again in order to count the number of transfer lines during the access line rewrite cycle. Step S2
In step 13, the sampled address is read from either the FIFO (A) 36 or the FIFO (B) 37.

In step S215, the process waits for the HSYNC to be received. If the HSYNC is received, the data of the line at the address read out earlier is transferred to the FLCD 26 in step S216. Next, in step S217, it is determined whether the transfer of the line has been completed for P lines. That is, if LN is smaller than P, the process proceeds to step S218, where LN is incremented by +1 and returns to step S213, and this process is repeated until the end of P lines. If P = 4, the loop of steps S213 to S218 is repeated four times. When the P line is completed, the process returns to step S203 to execute the full refresh cycle again.

As described above, the contents of the video memory 41 are displayed by repeating the full refresh cycle from step S203 to S208 and the access line rewriting cycle from step S211 to S217, and a carry occurs in the address counter 38. This is performed by returning the line of the entire refresh cycle to the head and initializing the signal.
On the other hand, the CPU 11 may read and write data from the video memory 41 independently of the display operation in order to obtain the displayed content.

As described above, reading data from the video memory 41 and transferring it to the FLCD 26 does not require command interpretation. Not only can it be configured with a relatively simple circuit, but also a graphic processor can be provided to interpret commands. This can be realized at lower cost than performing display control, and the performance can be improved while reducing the cost of the entire system.

(Second Embodiment) In FIG. 2, the FIFO is used as the storage means of the sampling address. However, as shown in FIG. 8, address control is performed by using an SRAM or the like as the storage means of the sampling address. As shown in FIG. 9, the oldest address among the sampled addresses can be discarded so that the latest address can be transferred.

Here, only the parts that are changed in FIGS. 8 and 9 with respect to FIGS. 2 and 6 will be described.

In FIG. 8, in this example, FIFO (A) 36, FIFO (B) 3
Instead of 7, an SRAM (A) 145 and an SRAM (B) 146 that can be accessed randomly are provided, and an address controller 147 for controlling the address of the SRAM is provided. Then, according to the output value C from the sampling counter 34, addressing is performed so as to output, for example, the number of transfer lines obtained from Table 1. For example, the write address of the sampling address is changed from “0” → “1” → “2” → “3” → “4” → “5”
And the number of transfer lines is 4,
The read address from the SRAM starts from “2” and changes, for example, from “2” → “3” → “4” → “5”. At this time, at the start of the next address sampling period, the write address is returned to "0" and old address information is discarded, so that the SRAM can store the minimum necessary information within one cycle. All you have to do is prepare an SRAM with a large capacity.

In the example of FIG. 9, the latest four lines are selected from among L1, L2, L3, L4, and L5 whose addresses are sampled in the SRAM (A) 145.
L2, L3, L4, L5 are transferred in the access line rewrite cycle. Also, of the L7, L8, and L9 sampled during the address sampling period of the next SRAM (A) 145, the latest 2
Lines L8 and L9 are transferred in the access line rewrite cycle.

In the case of FIFO, reading is performed in the order in which data is written, and there is no need to perform address control from the outside.Therefore, the configuration can be made compact.However, when reading the latest information as shown in this example, a dummy reading operation must be performed. Must be performed, and it is easier to control using an SRAM. Also, by properly controlling the address of the SRAM, it can be operated like a FIFO,
Further, for example, in the above, reading can be performed in the reverse direction such as “5” → “4” → “3” → “2”, so that the degree of freedom of the output address with respect to the sampled address is large. In other words, whether the old address of the accessed address is significant or the new address is significant will vary from case to case, and it is not always possible to say which is appropriate.
Also, the reading order may be involved in making the hardware configuration advantageous, so that in the configuration using SRAM, it is possible to select what is deemed appropriate according to the situation.

(Others) Note that the present invention is not limited to the above-described embodiments, and it is needless to say that appropriate modifications can be made without departing from the spirit of the present invention.

For example, in the above example, the refresh cycle and the partial rewrite cycle are basically performed alternately, the repetition cycle (T _a + T _b ) of these cycles is made variable, and the ratio of both cycles can be set. Although the cycle of the partial rewrite is adjusted according to the number of address lines and the like, it is not necessary to perform all of them. Instead of performing these steps in a series of sequences, any mode may be appropriately selected and executed as desired.

Further, in the above example, a table group of P values with the set N values as the upper limit values is provided, but the relationship between the above setting and the adjustment with the setting can be appropriately determined. For example, a table group of P values in which the set N values are set to medium values may be provided. Also, the count value C
A table of the P value and a single as the, for example also possible to determine only the appropriate M value based on temperature, etc. In step S200A corresponds to the maximum of the P value thereof, the period of T _a + T _b and T the ratio between _a and T _b can be changed. Also, instead of providing a sampling counter to count the number of access lines, the FIFO memory normally has "full", "half",
The number of access lines may be known using a flag such as “empty”.

In addition, in the above example, the return period is based on only the temperature information.
Although the CPU 11 performs the above setting, the timing of the setting can be determined as appropriate, and the FLC interface 27 is provided with a means for performing such processing independently of the CPU 11 to operate (FIG. 7) In the process, M and P may be constantly rewritten. Further, not only such temperature information but also other environmental conditions may be considered. Alternatively, or together with this, the type of display data such as an image image or a character may be considered.

Further, one unit of access or display may be one line or a plurality of lines.

[Effects of the Invention] As described above, according to the present invention, the address at the time of writing an image in the image storage means is stored in the address storage means, and the number of stored addresses is counted by the address number counting means. Based on the value, partial scanning is switched between partial rewriting based on the address stored in the address storage unit, and refresh scanning is switched over based on the count value of the address counting unit that sequentially updates the count value. Further, when the former partial scan is being performed, the count of the address count means for the latter refresh scan is stopped, so that each of the address for the partial scan and the count value of the refresh scan are qualified. And partial rewriting and full rewriting can be reliably performed.

Further, it is not necessary to identify whether or not the data is to be partially written in response to a command or the like, a constant refresh rate can be maintained, and the rewritten data can be displayed immediately. Therefore, the screen display can be made to follow the movement of figures and cursors with high responsiveness without changing the specifications of the software of the system using the FLC display at all.
It is also possible to perform a good display that makes full use of the above characteristics. In addition, compatibility between CRT and FLC from the viewpoint of the system is maintained. In addition, since it is realized with a simple circuit configuration, it is possible to perform inexpensive and high-speed display control.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus incorporating a display control device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of an FLCD interface as an embodiment of the present invention. Is a timing chart for explaining the basic operation of the FLCD interface shown in FIG. 2, FIG. 4 is a block diagram showing an example of the internal configuration of the synchronization control circuit shown in FIG. 2, and FIG. 5 is a diagram shown in FIG. FIG. 6 is a block diagram showing a configuration example for performing a counting operation of a sampling counter to be performed, FIG. 6 is a timing chart illustrating an example of adjustment of a partial rewriting operation period of the FLCD interface shown in FIG. 2, and FIG. 8 is a flowchart showing an example of the operation procedure of the FLCD interface, FIG. 8 is a block diagram showing the configuration of the FLCD interface as another embodiment of the present invention, and FIG. 8 is a timing chart for explaining the operation of the FLCD interface shown in FIG. 8, and FIG. 10 is a block diagram showing the configuration of a conventional CRT interface. 11 ... CPU, 12 ... Address bus, 13 ... System bus, 14 ... DMA controller, 15 ... LAN interface, 16 ... LAN, 17 ... I / O device, 18 ... Hard disk device, 19 ... ... Floppy disk drive, 20 ... Disk interface, 21 ... Printer, 22 ... Printer interface, 23 ... Keyboard, 24 ... Mouse, 25 ... Key interface, 26 ... FLCD (FLCD display), 26a ... Temperature sensor, 27 FLCD interface, 31 Address driver, 32 Control bus driver, 33, 43, 44 Data bus driver, 34 Sampling counter, 35 Address selector, 36 FIFO A) Memory, 37: FIFO (B) memory, 38: Address counter, 39: Synchronous control circuit, 40: Memory controller, 41: Video memory, 42 ... Driver receiver, S1, S2, S3 ... switch, 390 ... memory, 391 ... lookup table switching unit, 393 ... counter, 401 ... address latch unit, 403 ... comparison circuit, 145 ... SRAM (A ), 146: SRAM (B), 147: Address controller.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor, Yoshitsugu Yamanashi 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Kenjiro 3-30-2 Shimomaruko, Ota-ku, Tokyo JP-A-61-149933 (JP, A) JP-A-2-101495 (JP, A) JP-A-2-246482 (JP, A) JP-A-2-235094 (JP) (A) JP-A-3-109524 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/20 G09G 3/36 G02F 1/133

Claims (4)

(57) [Claims] 1. A display control device for a display device capable of partially changing a display state of a pixel, comprising: an image storage device for storing an image to be displayed on the display device; Supply means for supplying an image to be stored at a designated position; address count means for sequentially updating count values at predetermined intervals; address storage means for storing addresses supplied from the supply means; and address storage means Address number counting means for counting the number of addresses stored in the memory; refresh scanning means for sequentially scanning the scanning lines constituting the display device based on the count of the address counting means; Based on the address
Switching between the refresh scanning unit and the partial scanning unit according to a partial scanning unit that specifies and scans a scanning line configuring the display device, and according to a count value of the number of addresses counted by the address number counting unit. Switching means, when the switching means switches from scanning by the refresh scanning means to scanning by the partial scanning means, stops counting by the address counting means, and switches from scanning by the partial scanning means to refreshing by the refresh scanning means. Control means for restarting counting by the address counting means when switching to scanning is performed. 2. The apparatus according to claim 1, further comprising a plurality of said address storage means, wherein writing of an address to said address storage means and reading of an address from said address means are alternately switched. Display control device. 3. A display control method for a display device capable of partially changing a display state of a pixel, comprising: storing an image to be displayed on the display device together with an address of the image storage means at a position designated by the address; The address to be supplied is stored in an address storage unit, the number of addresses stored in the address storage unit is counted by an address number counting unit, and a scan line constituting the display device is provided. Refresh scanning for sequentially scanning based on the count value of the address counting means for sequentially updating the count value at predetermined intervals, and scanning by designating the scanning lines constituting the display device based on the address stored in the address storage means The partial scanning is performed according to the address value counted by the address number counting means. The switching by the switching means stops the counting by the address counting means when the switching is performed from the refresh scanning to the partial scanning, and the address counting is performed when the switching is performed from the partial scanning to the refresh scanning. A display control method, wherein the counting by means is restarted. 4. The apparatus according to claim 3, further comprising a plurality of said address storage means, wherein writing of an address to said address storage means and reading of an address from said address means are alternately switched. Display control method.