JP3028635B2 - Memory transistor - Google Patents
Memory transistorInfo
- Publication number
- JP3028635B2 JP3028635B2 JP3113675A JP11367591A JP3028635B2 JP 3028635 B2 JP3028635 B2 JP 3028635B2 JP 3113675 A JP3113675 A JP 3113675A JP 11367591 A JP11367591 A JP 11367591A JP 3028635 B2 JP3028635 B2 JP 3028635B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- memory transistor
- oxide film
- tunnel oxide
- uto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 123
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 230000003647 oxidation Effects 0.000 description 20
- 238000007254 oxidation reaction Methods 0.000 description 20
- 150000004767 nitrides Chemical class 0.000 description 17
- 239000000758 substrate Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- UOCLXMDMGBRAIB-UHFFFAOYSA-N 1,1,1-trichloroethane Chemical compound CC(Cl)(Cl)Cl UOCLXMDMGBRAIB-UHFFFAOYSA-N 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000009257 reactivity Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000001698 pyrogenic effect Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明はメモリトランジスタに
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory transistor.
【０００２】[0002]
【従来の技術】例えばＭＮＯＳ(Metal Nitride Oxide S
emiconductor)型と称される不揮発性メモリトランジス
タでは、ゲート絶縁膜として物質の異なる２層を備え、
下層ゲート絶縁膜がＳｉＯ2膜（トンネル酸化膜）で上
層ゲート絶縁膜がＳｉ3Ｈ4膜（シリコン窒化膜）等のシ
リサイド膜からなり、シリサイド膜上に形成されたゲー
ト電極に＋ＶGSが印化されると、チャネルから電子がト
ンネル酸化膜を通過してシリサイド膜との界面に捕獲さ
れ、これによりしきい値電圧Ｖthが正のエンハンスメン
ト型トランジスタとなり、データが書込まれ、一方、ゲ
ート電極に−ＶGSが印加されると、チャネルから正孔が
トンネル酸化膜を通過してシリサイド膜中に捕獲され、
これによりしきい値電圧Ｖthが負のデプレッション型ト
ランジスタとなり、データが消去されるようになってい
る。2. Description of the Related Art For example, MNOS (Metal Nitride Oxide S)
A non-volatile memory transistor called an “emiconductor” type includes two layers of different materials as a gate insulating film.
The lower gate insulating film is a SiO 2 film (tunnel oxide film) and the upper gate insulating film is a silicide film such as a Si 3 H 4 film (silicon nitride film), and + V GS is imprinted on the gate electrode formed on the silicide film. Then, electrons from the channel pass through the tunnel oxide film and are captured at the interface with the silicide film, whereby the threshold voltage Vth becomes a positive enhancement type transistor, data is written, and data is written on the gate electrode. When −V GS is applied to the holes, holes are trapped in the silicide film through the tunnel oxide film from the channel,
As a result, the threshold voltage Vth becomes a negative depression type transistor, and data is erased.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
このようなメモリトランジスタでは、ＳｉＯ2膜からな
るトンネル酸化膜の膜厚を５０Å以下と極めて薄くする
必要がある関係から、トンネル酸化膜を形成する際、Ｈ
2とＯ2を用いた希釈酸化あるいは分圧酸化、Ｏ2を用い
たドライ酸化、ランプアニール酸化、ＨＣｌとＯ2を用
いた塩酸酸化、ＴＣＡ（トリクロロエタン）とＯ2を用
いたＴＣＡ酸化等の酸化法によって形成しているが、例
えば通常のＭＯＳ構造の薄膜トランジスタにおける同じ
くＳｉＯ2膜からなるゲート絶縁膜をパイロジェニック
スチーム酸化等の酸化法によって１０００〜３０００Å
程度と厚く形成した場合と比較して、５０Å以下の極薄
の酸化膜として最も重要な膜厚の制御性、均一性、再現
性が悪く、また界面準位密度が増加し、絶縁破壊特性が
劣化するという問題があった。しかしながら、パイロジ
ェニックスチーム酸化では、酸化膜を５０Å以下の極薄
には形成できない。この発明の目的は、トンネル酸化膜
の膜厚の制御性、均一性、再現性を良くすることがで
き、また界面準位密度を低減することのできるメモリト
ランジスタを提供することにある。However, in such a conventional memory transistor, a tunnel oxide film formed of a SiO 2 film must be formed as extremely thin as 50 ° or less, so that the tunnel oxide film is formed. When H
Such as dilution oxidation or partial pressure oxidation using 2 and O 2 , dry oxidation using O 2 , lamp annealing oxidation, hydrochloric acid oxidation using HCl and O 2 , and TCA oxidation using TCA (trichloroethane) and O 2 . For example, the gate insulating film of the same MOS 2 film in a thin film transistor having a normal MOS structure is formed by an oxidation method such as a pyrogenic steam oxidation method at 1000 to 3000 °.
Compared to the case where the oxide film is formed as thick as approximately, the controllability, uniformity and reproducibility of the most important film thickness as an ultra-thin oxide film of 50 ° or less are poor, the interface state density increases, and the There was a problem of deterioration. However, in pyrogenic steam oxidation, an oxide film cannot be formed as thin as 50 ° or less. An object of the present invention is to provide a memory transistor that can improve controllability, uniformity, and reproducibility of the thickness of a tunnel oxide film, and that can reduce interface state density.
【０００４】[0004]
【課題を解決するための手段】この発明は、半導体層と
ゲート電極との間にトンネル酸化膜と絶縁膜とを介在し
てなるメモリトランジスタにおいて、トンネル酸化膜を
Ｏ３ガスを用いて形成したオゾン酸化膜としたものであ
る。SUMMARY OF THE INVENTION The present invention, in the memory transistor formed by interposing a tunnel oxide film and an insulating film between the semiconductor layer and the gate electrode, forming a tunnel oxide film using O 3 gas It is an ozone oxide film.
【０００５】[0005]
【作用】この発明によれば、トンネル酸化膜をＯ3ガス
を用いて形成したオゾン酸化膜としているので、ＳｉＯ
2膜からなるトンネル酸化膜と比較して、Ｏ3がＯ2に比
べて反応性が高く、このため３５０℃程度の低温下であ
っても酸化膜の成長速度が速く、ひいては膜厚が１０〜
５０Å程度と極めて薄くても、膜厚の均一性を良くする
ことができ、またＯ3の流量、温度、圧力等の酸化処理
条件の設定が容易であり、このため膜厚の制御性および
再現性を良くすることができ、さらに界面準位密度が低
減し、絶縁破壊特性を良くすることができる。According to the present invention, the tunnel oxide film is an ozone oxide film formed by using O 3 gas.
O 3 has a higher reactivity than O 2 as compared with a tunnel oxide film composed of two films. Therefore, even at a low temperature of about 350 ° C., the growth rate of the oxide film is high, and the film thickness is 10 ~
Even when the thickness is as thin as about 50 °, the uniformity of the film thickness can be improved, and the oxidation treatment conditions such as the flow rate, temperature, and pressure of O 3 can be easily set. Properties can be improved, the interface state density can be reduced, and the dielectric breakdown characteristics can be improved.
【０００６】[0006]
【実施例】図１〜図６はそれぞれこの発明の一実施例に
おけるメモリトランジスタの各製造工程を示したもので
ある。そこで、これらの図を順に参照しながら、メモリ
トランジスタの構造についてその製造方法と併せ説明す
る。1 to 6 show respective steps of manufacturing a memory transistor according to an embodiment of the present invention. Therefore, the structure of the memory transistor will be described together with its manufacturing method with reference to these drawings in order.
【０００７】まず、図１に示すように、単結晶のｎ型Ｓ
ｉ基板（半導体層）１の上面側にボロンイオンの注入拡
散により形成されたｐ型領域２の上面の所定のメモリト
ランジスタ形成領域以外に、図示しないシリコン窒化膜
をマスクとして、ＬＯＣＯＳ法によりフィールド酸化膜
３を形成する。この場合、Ｓｉ基板の代わりに、ポリシ
リコン基板を用いるようにしてもよい。次に、マスクと
してのシリコン窒化膜をエッチングして除去し、この除
去した部分におけるＳｉ基板１の上面に、３５０℃程度
の温度下でＯ3（オゾン）ガスを用いた常圧熱酸化処理
を施すことにより、Ｏ3酸化膜からなる下層ＵＴＯ(Ultr
aThin Oxide)膜（トンネル酸化膜）４を１０〜５０Å程
度の厚さに形成する。Ｏ3酸化膜からなるトンネル酸化
膜は、ＳｉＯ2膜からなるトンネル酸化膜と比較して、
Ｏ3ガスはＯ2ガスに比べて反応性が高いので、３５０℃
程度の低温下であっても酸化膜の成長速度が速く、この
ため膜厚が１０〜５０Å程度と極めて薄くても、膜厚の
均一性を良くすることができ、またＯ3ガスは流量、温
度、圧力等の酸化処理条件の設定が容易であり、このた
め膜厚の制御性および再現性を良くすることができ、さ
らに界面準位密度が低減し、絶縁破壊特性を良くするこ
とができる。[0007] First, as shown in FIG.
Field oxidation by LOCOS using a silicon nitride film (not shown) as a mask other than a predetermined memory transistor formation region on the upper surface of p-type region 2 formed by implanting and diffusing boron ions on the upper surface side of i substrate (semiconductor layer) 1 The film 3 is formed. In this case, a polysilicon substrate may be used instead of the Si substrate. Next, the silicon nitride film as a mask is removed by etching, and the upper surface of the Si substrate 1 in the removed portion is subjected to a normal pressure thermal oxidation process using O 3 (ozone) gas at a temperature of about 350 ° C. by performing, lower UTO (Ultr consisting O 3 oxide film
a Thin Oxide) film (tunnel oxide film) 4 is formed to a thickness of about 10 to 50 °. The tunnel oxide film made of the O 3 oxide film is compared with the tunnel oxide film made of the SiO 2 film.
Since O 3 gas has higher reactivity than O 2 gas, 350 ° C.
Even at a low temperature of a degree higher growth rate of the oxide film, even if the the film thickness is extremely thin as about 10 to 50 Å, it is possible to improve the uniformity of the film thickness and the O 3 gas flow rate, Oxidation treatment conditions such as temperature and pressure can be easily set, so that the controllability and reproducibility of the film thickness can be improved, the interface state density can be reduced, and the dielectric breakdown characteristics can be improved. .
【０００８】次に、図２に示すように、９００〜１２０
０℃の高温下でＮＨ3ガスまたはＮＨ3を主成分とする混
合ガスを用いた熱処理を施し、下層ＵＴＯ膜４を介して
そのすぐ下側におけるＳｉ基板１の上面を窒化し、ＵＴ
Ｎ(Ultra Thin Nitride)膜５を１０〜３０Å程度の厚さ
に形成する。この場合、下層ＵＴＯ膜４の部分に対応す
る領域のＳｉ基板１の上面のみを窒化することができる
ので、ＵＴＮ膜５を形成した後に下層ＵＴＯ膜４を形成
する場合に比べて、製造工程数を減少することができ、
かつ膜質が良好となり、エネルギバンドを緩傾斜とする
ので、一層の低電圧駆動が可能となる。Next, as shown in FIG.
At a high temperature of 0 ° C., a heat treatment using NH 3 gas or a mixed gas containing NH 3 as a main component is performed, and the upper surface of the Si substrate 1 immediately below the lower UTO film 4 is nitrided through the lower UTO film 4.
An N (Ultra Thin Nitride) film 5 is formed to a thickness of about 10 to 30 °. In this case, since only the upper surface of the Si substrate 1 in a region corresponding to the portion of the lower UTO film 4 can be nitrided, the number of manufacturing steps is smaller than the case where the lower UTO film 4 is formed after the UTN film 5 is formed. Can be reduced,
In addition, since the film quality is improved and the energy band is gently inclined, further low voltage driving is possible.
【０００９】次に、図３に示すように、下層ＵＴＯ膜４
およびフィールド酸化膜３の上面に７００〜８００℃の
温度下でＳｉＨ2Ｃｌ2とＮＨ3の混合ガスを用いた減圧
ＣＶＤ法によりＳｉ3Ｎ4からなるＳｉ窒化膜（シリサイ
ド膜）６を１００Å以下の厚さに形成する。この場合、
ＮＨ3の流量比を大きくしてＳｉ／Ｎ比を０．８５〜
１．１５程度として、Ｓｉ窒化膜６をＵＴＮ膜５よりも
Ｓｉ過剰とすると、電荷捕獲特性を大きくすることがで
きる。Next, as shown in FIG. 3, the lower UTO film 4
And a Si nitride film (silicide film) 6 made of Si 3 N 4 on the upper surface of the field oxide film 3 at a temperature of 700 to 800 ° C. by a reduced pressure CVD method using a mixed gas of SiH 2 Cl 2 and NH 3 at a temperature of 100 ° or less. Formed to a thickness of in this case,
The NH 3 flow rate ratio was increased to increase the Si / N ratio from 0.85 to
When the Si nitride film 6 is set to about 1.15 and the Si nitride film 6 is made to have a Si excess relative to the UTN film 5, the charge trapping characteristics can be increased.
【００１０】次に、図４に示すように、Ｓｉ窒化膜６の
上面を直接酸化することにより、Ｓｉ窒化膜６の上面に
上層ＵＴＯ膜７を２０Å程度の厚さに形成する。この方
法として、９００〜１２００℃で熱酸化する高温処理で
もよいが、この場合にも３５０℃程度の温度下でＯ3ガ
スを用いた常圧熱酸化処理を施すことが望ましい。次
に、上層ＵＴＯ膜７の上面に６００℃程度の温度下でＳ
ｉＨ4ガスを用いた減圧ＣＶＤ法によりゲート電極用の
ポリシリコン膜８を２０００Å程度の厚さに形成する。Next, as shown in FIG. 4, an upper UTO film 7 having a thickness of about 20 ° is formed on the upper surface of the Si nitride film 6 by directly oxidizing the upper surface of the Si nitride film 6. As this method, high-temperature treatment in which thermal oxidation is performed at 900 to 1200 ° C. may be used, but in this case, it is preferable to perform normal-pressure thermal oxidation using O 3 gas at a temperature of about 350 ° C. Next, S is formed on the upper surface of the upper UTO film 7 at a temperature of about 600 ° C.
A polysilicon film 8 for a gate electrode is formed to a thickness of about 2000 ° by a low pressure CVD method using iH 4 gas.
【００１１】次に、図５に示すように、ポリシリコン膜
８の上面にフォトレジスト膜９をパターン形成し、ドラ
イエッチングにより幅が２μｍ以下のゲート形成領域１
０を形成する。次に、この状態でリンイオンを注入拡散
し、ゲート形成領域１０の両側におけるｐ型領域２内に
高濃度の２つのｎ型領域１１を形成するとともに、ポリ
シリコン膜からなるゲート電極８の抵抗値を所定の値に
減少させる。２つのｎ型領域１１はソース領域およびド
レイン領域を形成するためのものである。この後、フォ
トレジスト膜９をエッチングして除去する。Next, as shown in FIG. 5, a photoresist film 9 is formed on the upper surface of the polysilicon film 8 by patterning, and the gate forming region 1 having a width of 2 μm or less is formed by dry etching.
0 is formed. Next, in this state, phosphorus ions are implanted and diffused to form two high-concentration n-type regions 11 in the p-type region 2 on both sides of the gate formation region 10 and to reduce the resistance value of the gate electrode 8 made of a polysilicon film. Is reduced to a predetermined value. The two n-type regions 11 are for forming a source region and a drain region. Thereafter, the photoresist film 9 is removed by etching.
【００１２】次に、図６に示すように、全表面に熱酸化
法、常圧酸化法、スパッタ酸化法等により層間絶縁膜１
２を形成し、エッチングにより所定の部分の層間絶縁膜
１２を除去して２つのコンタクトホール１３を形成す
る。次に、層間絶縁膜１２の上面にＡｌからなるソース
・ドレイン電極１４をパターン形成して２つのｎ型領域
１１とそれぞれ接続させる。かくして、不揮発性メモリ
トランジスタが形成される。Next, as shown in FIG. 6, an interlayer insulating film 1 is formed on the entire surface by a thermal oxidation method, a normal pressure oxidation method, a sputter oxidation method, or the like.
2 are formed, and a predetermined portion of the interlayer insulating film 12 is removed by etching to form two contact holes 13. Next, source / drain electrodes 14 made of Al are formed in a pattern on the upper surface of the interlayer insulating film 12 and connected to the two n-type regions 11 respectively. Thus, a nonvolatile memory transistor is formed.
【００１３】次に、このメモリトランジスタの動作につ
いて説明するに、まずデータを書込む場合には、ゲート
電極８に＋ＶGSを印加すると、チャネル１５から電子が
ＵＴＮ膜５および下層ＵＴＯ膜４を通過してＳｉ窒化膜
６中に捕獲され、これによりしきい値電圧Ｖthが正のエ
ンハンスメント型トランジスタとなり、データが書込ま
れる。データを消去する場合には、ゲート電極８に−Ｖ
GSを印加すると、チャネル１５から正孔がＵＴＮ膜５お
よび下層ＵＴＯ膜４を通過してＳｉ窒化膜６中に捕獲さ
れ、これによりしきい値電圧Ｖthが負のデプレッション
型トランジスタとなり、データが消去される。Next, the operation of the memory transistor will be described. First, when writing data, when + V GS is applied to the gate electrode 8, electrons pass from the channel 15 through the UTN film 5 and the lower UTO film 4. As a result, the transistor is trapped in the Si nitride film 6, whereby the threshold voltage Vth becomes a positive enhancement type transistor, and data is written. When erasing data, the gate electrode 8 must have -V
When GS is applied, holes pass from the channel 15 through the UTN film 5 and the lower UTO film 4 and are captured in the Si nitride film 6, whereby the threshold voltage Vth becomes a negative depletion type transistor, and data is erased. Is done.
【００１４】ところで、このメモリトランジスタでは、
Ｓｉ窒化膜６を下層ＵＴＯ膜４と上層ＵＴＯ膜７との２
つの酸化膜によって包囲しているので、Ｓｉ窒化膜６を
周囲から絶縁することができ、このためＳｉ窒化膜６か
らゲート電極８へのリーク電流が生じることがなく、デ
ータ保持特性を改善することができる。また、Ｓｉ窒化
膜６を包囲している下層ＵＴＯ膜４および上層ＵＴＯ膜
７を高温の熱酸化により形成しているので、完全に良質
で安定な酸化膜とすることができ、耐久性を良くするこ
とができる。さらに、ＵＴＮ膜５、下層ＵＴＯ膜４およ
び上層ＵＴＯ膜７が極めて薄いので、動作電圧の低電圧
化を図ることもできる。なお、このメモリトランジスタ
では、従来のものがＭＮＯＳ型と称されているのに対
し、ＭＯＮＯＮＳ(Metal Oxide Nitride Oxide Nitride
Semiconductor)型と称することができる。しかしなが
ら、この発明は従来タイプのＭＮＯＳ型にも適用可能で
ある。By the way, in this memory transistor,
The Si nitride film 6 is formed of the lower UTO film 4 and the upper UTO film 7.
Since it is surrounded by the two oxide films, the Si nitride film 6 can be insulated from the surroundings, so that no leak current flows from the Si nitride film 6 to the gate electrode 8 and the data retention characteristics are improved. Can be. Further, since the lower UTO film 4 and the upper UTO film 7 surrounding the Si nitride film 6 are formed by high-temperature thermal oxidation, the oxide film can be a completely high-quality and stable oxide film, and the durability is improved. can do. Furthermore, since the UTN film 5, the lower UTO film 4, and the upper UTO film 7 are extremely thin, the operating voltage can be reduced. In this memory transistor, a conventional transistor is called an MNOS type, while a MONONS (Metal Oxide Nitride Oxide Nitride) is used.
Semiconductor) type. However, the present invention is also applicable to a conventional MNOS type.
【００１５】なお、この発明は、図７に示すように、Ｌ
ＤＤ(LightlyDoped Drain)構造と称されるものにも適用
することができる。この図において、図６と同一名称部
分には同一の符号を付し、その説明を適宜省略する。こ
のメモリトランジスタでは、ＵＴＮ膜５の両側がその上
側の下層ＵＴＯ膜４等の両側に突出され、この突出され
た部分に対応する領域のｎ型領域１１が不純物濃度の低
いソース・ドレイン領域１１ａとされ、それ以外の領域
のｎ型領域１１が不純物濃度の高いソース・ドレイン領
域１１ｂとされ、そして不純物濃度の低いソース・ドレ
イン領域１１ａによって高電界を緩和するための領域が
形成され、これにより通常のＭＯＳ構造のものと比較し
て、耐圧の向上等を図って高信頼性化したＬＤＤ構造と
なっている。また、このメモリトランジスタでは、３つ
のｎ型領域１１が備えられ、左側と中央の２つのｎ型領
域１１に対応する部分によってＬＤＤ構造のメモリトラ
ンジスタ２１が形成され、中央と右側の２つのｎ型領域
１１に対応する部分によってＬＤＤ構造の選択トランジ
スタ２２が形成された構造となっている。そして、選択
トランジスタ２２のゲート電極２３にＶONが印加される
と、メモリトランジスタ２１が消去状態のデプレッショ
ン型トランジスタとなっている場合には２つのソース・
ドレイン電極１４間に電流が流れることによりデータが
読出され、書込み状態のエンハンスメント型トランジス
タとなっている場合には２つのソース・ドレイン電極１
４間に電流が流れず、メモリトランジスタ２１の状態を
判定することができる。It should be noted that, as shown in FIG.
The present invention can be applied to a so-called DD (Lightly Doped Drain) structure. In this figure, the same parts as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In this memory transistor, both sides of the UTN film 5 are protruded on both sides of the lower UTO film 4 and the like on the upper side thereof, and the n-type region 11 in the region corresponding to the protruded portion is the source / drain region 11a having a low impurity concentration. The n-type region 11 in the other region is a source / drain region 11b having a high impurity concentration, and a region for relaxing a high electric field is formed by the source / drain region 11a having a low impurity concentration. The LDD structure has a higher reliability compared to the MOS structure having the above structure to improve the breakdown voltage and the like. Further, in this memory transistor, three n-type regions 11 are provided, and a memory transistor 21 having an LDD structure is formed by portions corresponding to the two n-type regions 11 on the left and the center, and two n-type regions on the center and the right are formed. A portion corresponding to the region 11 has a structure in which the select transistor 22 having the LDD structure is formed. When V ON is applied to the gate electrode 23 of the selection transistor 22, when the memory transistor 21 is a depletion type transistor in an erased state, two sources
When a current flows between the drain electrodes 14, data is read out. In the case of an enhancement-type transistor in a written state, two source-drain electrodes 1 are used.
No current flows between the four, and the state of the memory transistor 21 can be determined.
【００１６】上記実施例では、この発明を単結晶半導体
基板に適用した場合について説明したが、これに限定さ
れず、半導体薄膜を用いて実施することもできる。この
場合、コプラナ型のみならず、逆コプラナ型、スタガ
型、逆スタガ型等にも適用することができる。In the above embodiment, the case where the present invention is applied to a single crystal semiconductor substrate has been described. However, the present invention is not limited to this, and the present invention can be implemented using a semiconductor thin film. In this case, the present invention can be applied not only to the coplanar type but also to an inverted coplanar type, a staggered type, an inverted staggered type, and the like.
【００１７】[0017]
【発明の効果】以上説明したように、この発明によれ
ば、トンネル酸化膜をＯ3ガスを用いて形成したオゾン
酸化膜としているので、ＳｉＯ2膜からなるトンネル酸
化膜と比較して、Ｏ3ガスがＯ2ガスに比べて反応性が高
く、このため３５０℃程度の低温下であっても酸化膜の
成長速度が速く、ひいては膜厚が１０〜５０Å程度と極
めて薄くても、膜厚の均一性を良くすることができ、ま
たＯ3ガスは流量、温度、圧力等の酸化処理条件の設定
が容易であり、このため膜厚の制御性および再現性を良
くすることができ、さらに界面準位密度が低減し、絶縁
破壊特性を良くすることができる。As described in the foregoing, according to the present invention, since the ozone oxide film forming a tunnel oxide film using O 3 gas, as compared to the tunnel oxide film made of SiO 2 film, O The 3 gas has a higher reactivity than the O 2 gas, and therefore, even at a low temperature of about 350 ° C., the growth rate of the oxide film is high. Of O 3 gas, and it is easy to set the oxidation treatment conditions such as flow rate, temperature, pressure, etc., so that the controllability and reproducibility of the film thickness can be improved. The interface state density is reduced, and the dielectric breakdown characteristics can be improved.
【図１】この発明の一実施例におけるメモリトランジス
タの製造に際し、Ｓｉ基板上に下層ＵＴＯ膜を形成した
状態の断面図。FIG. 1 is a sectional view showing a state in which a lower UTO film is formed on a Si substrate in manufacturing a memory transistor according to an embodiment of the present invention.
【図２】このメモリトランジスタの製造に際し、下層Ｕ
ＴＯ膜下のＳｉ基板上にＵＴＮ膜を形成した状態の断面
図。FIG. 2 shows a lower layer U in the manufacture of this memory transistor.
Sectional drawing in the state where the UTN film was formed on the Si substrate under the TO film.
【図３】このメモリトランジスタの製造に際し、下層Ｕ
ＴＯ膜上にＳｉ窒化膜を形成した状態の断面図。FIG. 3 shows a method of manufacturing the memory transistor,
Sectional drawing in the state where Si nitride film was formed on TO film.
【図４】このメモリトランジスタの製造に際し、Ｓｉ窒
化膜上に上層ＵＴＯ膜を形成した状態の断面図。FIG. 4 is a cross-sectional view showing a state in which an upper UTO film is formed on a Si nitride film in manufacturing the memory transistor.
【図５】このメモリトランジスタの製造に際し、ゲート
形成領域を形成した状態の断面図。FIG. 5 is a cross-sectional view showing a state where a gate formation region is formed in manufacturing the memory transistor.
【図６】このメモリトランジスタの製造に際し、ソース
・ドレイン電極等を形成した状態の断面図。FIG. 6 is a sectional view showing a state where a source / drain electrode and the like are formed in manufacturing the memory transistor.
【図７】この発明の他の実施例におけるメモリトランジ
スタの要部の断面図。FIG. 7 is a sectional view of a main part of a memory transistor according to another embodiment of the present invention.
１ Ｓｉ基板（半導体層） ４ 下層ＵＴＯ膜（トンネル酸化膜） ５ ＵＴＮ膜 ６ Ｓｉ窒化膜（シリサイド膜） ７ 上層ＵＴＯ膜 ８ ゲート電極 Reference Signs List 1 Si substrate (semiconductor layer) 4 Lower UTO film (tunnel oxide film) 5 UTN film 6 Si nitride film (silicide film) 7 Upper UTO film 8 Gate electrode
フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792 Continuation of the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792
Claims (6)
酸化膜と絶縁膜とを介在してなるメモリトランジスタに
おいて、 前記トンネル酸化膜はＯ３ガスを用いて形成したオゾン
酸化膜からなることを特徴とするメモリトランジスタ。1. A memory transistor having a tunnel oxide film and an insulating film interposed between a semiconductor layer and a gate electrode, wherein the tunnel oxide film is formed of an ozone oxide film formed using O 3 gas. Characteristic memory transistor.
Å程度であることを特徴とする請求項１記載のメモリト
ランジスタ。2. The tunnel oxide film has a thickness of 10 to 50.
2. The memory transistor according to claim 1, wherein the value is approximately Å.
間にシリコン窒化薄膜を介在してなることを特徴とする
請求項１記載のメモリトランジスタ。3. The memory transistor according to claim 1, wherein a silicon nitride thin film is interposed between said semiconductor layer and said tunnel oxide film.
間にシリコン窒化薄膜を介在するとともに、前記絶縁膜
と前記ゲート電極との間にシリコン酸化薄膜を介在して
なることを特徴とする請求項１記載のメモリトランジス
タ。4. The method according to claim 1, wherein a silicon nitride thin film is interposed between the semiconductor layer and the tunnel oxide film, and a silicon oxide thin film is interposed between the insulating film and the gate electrode. Item 2. The memory transistor according to Item 1.
特徴とする請求項１記載のメモリトランジスタ。5. The memory transistor according to claim 1, wherein said semiconductor layer is made of silicon.
とを特徴とする請求項１記載のメモリトランジスタ。6. The memory transistor according to claim 1, wherein said semiconductor layer is made of polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3113675A JP3028635B2 (en) | 1991-04-19 | 1991-04-19 | Memory transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3113675A JP3028635B2 (en) | 1991-04-19 | 1991-04-19 | Memory transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04320378A JPH04320378A (en) | 1992-11-11 |
| JP3028635B2 true JP3028635B2 (en) | 2000-04-04 |
Family
ID=14618322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3113675A Expired - Lifetime JP3028635B2 (en) | 1991-04-19 | 1991-04-19 | Memory transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3028635B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4477422B2 (en) | 2004-06-07 | 2010-06-09 | 株式会社ルネサステクノロジ | Method for manufacturing nonvolatile semiconductor memory device |
| JP4468791B2 (en) * | 2004-11-18 | 2010-05-26 | 浜松ホトニクス株式会社 | Method for manufacturing photodetection element |
| JP2006147798A (en) * | 2004-11-18 | 2006-06-08 | Hamamatsu Photonics Kk | Photodetector |
| JP4580899B2 (en) * | 2006-06-08 | 2010-11-17 | 株式会社東芝 | Semiconductor memory device and manufacturing method thereof |
| US8330207B2 (en) | 2006-09-26 | 2012-12-11 | Samsung Electronics Co., Ltd. | Flash memory device including multilayer tunnel insulator and method of fabricating the same |
-
1991
- 1991-04-19 JP JP3113675A patent/JP3028635B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04320378A (en) | 1992-11-11 |
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