JP3019853B2 - ATM switch and control method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bandwidth control system and circuit for a virtual path or virtual connection in a packet switch of a fixed-length packet cross-connect device or a switching device, and more particularly to an asynchronous transfer mode (hereinafter referred to as ATM). ) And ATM switches.

[0002]

2. Description of the Related Art CCITT (International Telegraph and Telephone Consultative Committee) has been working on broadband and multimedia applications in the communication field.
In the ATM system agreed on in the above, transmission / exchange is performed using fixed-length packets called cells. Many switch systems for exchanging cells have been proposed.

[0003] Also, in a transmission device for connecting exchanges, the architecture of a line network is flexibly changed and the line management is simplified in units of virtual lines called virtual paths. At this time, a device for exchanging cells according to the virtual path is used.
This is called a TM cross connect device. The ATM cross-connect device is considered as a kind of ATM switch.

One of the ATM switch systems is a common buffer memory switch, which is described by Kozaki et al. (“Common buffer type ATM switch LSI configuration method”, IEICE, SSE8).
9-144, pp.49-54 (Heisei 2-02). ) Shows an example of the configuration method. This is shown in FIG.

Generally, various terminal devices connected to a subscriber line output so-called bursty traffic in which there is a period for continuously outputting data and a period for not outputting data. The amount of buffer required for an ATM switch is more than ten to several tens times larger when accommodating such bursty traffic than accommodating traffic that randomly emits cells. It is known. Therefore, in order to construct an ATM network economically using a cross-connect device with a small buffer amount,
It is necessary to eliminate burstiness in a device for accommodating a subscriber line. For this reason, a process for arranging cells belonging to the same virtual channel or virtual path as evenly as possible is required. This process is called band control.

[0006] The method of performing such band control includes:
Other documents (“ATM switching network line setting method”,
IEICE, SSE89-120, pp.31-36 (Heisei 2-01). ) Shows an example. That is, there is shown a method of performing band control by previously determining a time position of a cell belonging to a virtual path or a virtual channel in a frame at an outgoing line of an exchange or a cross-connect device. Also, an algorithm for dynamically determining a time position for each outgoing line is shown.

[0007]

In a switch configuration using a common buffer memory switch using the above-mentioned conventional technology, no bandwidth control is taken into consideration. Therefore, a line having a burst characteristic is exchanged / output while maintaining the burst characteristic. As a result, there has been a problem that a large amount of buffer memory is required in a cross-connect device or exchange connected to this output.

Further, even if the bandwidth control for each output line is performed according to the above-described conventional technique, it is necessary to change the time order in order to perform the bandwidth control. In this case, there is a problem that a waiting buffer is required, and a large amount of buffers of a device for performing band control are required. On the other hand, an algorithm for dynamically determining a time position, which is shown in the above-described prior art, It is also shown that the amount of memory can be reduced by using. However, a control device for executing this algorithm becomes complicated, and it is necessary to lengthen the cycle of arrangement determination in order to arrange the arrangement more evenly, so that there is a problem that the amount of memory increases.

Further, when the amount of memory increases, there is a problem that the time for cells to stay in the memory becomes longer and the delay in transmission and exchange increases.

An object of the present invention is to reduce the amount of memory required for bandwidth control. Another object of the invention is to provide
An object of the present invention is to realize bandwidth control without increasing the buffer capacity of the device by using a memory necessary for bandwidth control as a large amount of buffer originally provided in the switch.

Another object of the present invention is to provide a method and circuit capable of efficiently implementing band control with a simple configuration, and a switch provided with the method and circuit.

It is a further object of the present invention to reduce the amount of buffer required for separating into lower-speed transmission lines by using bandwidth control.

It is another object of the present invention to provide a band control method and circuit capable of easily changing a band, and a switch provided with the same.

[0014]

In a common buffer type memory switch, a single large buffer memory is prepared, a buffer memory is prepared, and a memory for connecting an address chain to the buffer memory is added. Further, a list structure using a chain is created in the buffer after the outgoing line. When a cell is input, the cell is first stored in the buffer memory. At the same time,
The outgoing line of the cell is determined, and the chain of the address of the buffer storing the cell is connected to the end of the list structure of the corresponding outgoing line. When outputting a cell, a list structure according to the output line to be output is selected, an address of a buffer in which a cell to be output is stored is taken out from the head of the list structure, and a cell output is obtained from the address. I do.

If these operations are periodically performed for all incoming lines and all outgoing lines, the input cells are classified according to the outgoing lines and added to the list structure, and the corresponding outgoing lines are read out. Is output by That is, the exchange operation can be realized. In addition, since the cells are connected in a list structure, the time order is not changed.

In the present invention, in order to achieve the above object, cells are not only added to the list structure for each outgoing line, but are further classified into virtual paths or virtual channels for each outgoing line, and each virtual path or virtual channel is classified. Connect to the list structure corresponding to the channel. When reading cells, a virtual path or a virtual channel to be output to each outgoing line is temporally designated, and cells are read from the head of the corresponding list structure.

Further, in the present invention, in order to achieve the other object, the following circuit configuration is employed. That is,
In order to classify input cells by virtual paths or virtual channels and connect them to the list structure, if a virtual path or virtual path identifier is given,
There is provided a table for providing an identifier for specifying a list structure for connecting cells, an address for storing cells, or an address of a chain for connection. If a virtual path to be output or a cell belonging to the virtual path is extracted from the list structure, if an identifier of the virtual path or the virtual path is given, an identifier specifying the list structure from which the cell is to be extracted, an address from which the cell is to be read, or an extraction from the cell It has a table giving the addresses of the chains. Furthermore, in order to designate a virtual path or a virtual path to be output in accordance with the read timing for each output line, a counter having a fixed period and a virtual path which is periodically referred to by the value of the counter and output at each timing Alternatively, it has a band designation table holding a virtual path.

[0018]

In the common buffer type memory switch according to the present invention, not only the outgoing line but also the virtual path to which the cell belongs or the virtual path is classified to form a list structure. Therefore, a cell can be output by designating a virtual path or a virtual path while preserving the order of cells belonging to the same virtual path or the virtual path. Therefore, by designating the virtual paths or the virtual paths to be arranged as evenly as possible, it is possible to arrange and output the cells arriving in a burst evenly.

In the band control circuit using the common buffer type memory switch according to the present invention, a virtual path or a list structure for each virtual path is created in a buffer in the switch. Therefore, it is possible to share a buffer for changing the order of the cells, which is necessary for the bandwidth control for each output line. That is, it is possible to eliminate an increase in the buffer amount.

Further, in general, a switch which performs an exchange operation with a single buffer has a much smaller memory capacity than a switch having a buffer for each output line. This is because, in a switch of the common buffer type, even if there are outgoing lines requiring many buffers, the buffers are dynamically allocated as needed, so that the total amount of buffers may be small. This is called a buffer reduction effect due to the commonality or a commonality effect.
Due to this common effect, the total number of buffers is smaller in the case of the present invention in which buffers are collectively provided in the switch than in the case where band control is performed for each output line. Further, in the present invention, since the switch and the band control function share the buffer, the buffer amount of the entire apparatus can be reduced by the common effect.

Further, the present invention has a counter and a table for designating a virtual path or a virtual channel to be output, and designates cell arrangement, that is, designates and controls a band according to the contents of the table. Therefore, if the contents of this table can be determined in advance so as to be optimal, band control can be performed efficiently. Also,
The number of cells stored in the buffer can be reduced, and the delay can be reduced. This is because, in general, it is possible to uniformly arrange cells when statically determining cell arrangements rather than dynamically determining cell arrangements.

In the present invention, since the band is specified using the table, the band can be changed very flexibly.

In the common buffer switch according to the present invention, in addition to connecting to a list structure by classifying by virtual path or virtual channel, a list structure can also be created by classifying by line number when separating into low-speed lines. it can. Furthermore, if a low-speed line number is specified in addition to the virtual path or virtual channel to be output, cells can be output so that the line number becomes periodic. Therefore, the buffer in the separation unit can be minimized by periodically allocating the cells to the low-speed line in the separation unit.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.
Perform according to. FIG. 1 is a block diagram of an embodiment of a common buffer switch for performing band control according to the present invention. Here, for the sake of explanation, the common buffer switch is configured as a 36 × 36 switch. This is because the ratio between the number of inputs and outputs and the cell length is a simple integer ratio of 2: 3 (= 36: 54), so that the logical configuration of multiplexing / demultiplexing when writing cells to the buffer can be simplified. To do that. Also,
It is assumed that the bandwidth control is performed on a virtual path basis. It is assumed that the virtual path is performed in virtual path units. The virtual path can be known by a virtual path identifier (VPI).

This switch comprises a buffer unit 1 and a buffer control unit 2. Cells arriving from each of the inputs 501-1 to 36 are multiplexed by the MUX 11 and stored in the buffer memory (BFM) 12 one by one. At this time, the address for storing the cell is an empty address buffer (IAB).
UF) 3 to a free address stored in the storage area.
At the same time, routing information (RT
G) is sent from the buffer unit 1 to the buffer control unit 2. RTG is a routing decoder (RT DEC)
21 and a chain write address table (WR CH Tabl) corresponding to the outgoing line of the arrived cell.
e) Specify 22-1 to 36. This WR CH Ta
ble22-1 to ble36 hold the address at which the cell was last stored for each VPI. Therefore, WR CH
When Tables 22-1 to 22-36 are referred to by the VPI of the arriving cell, the address at which the cell of the same VPI was written last is known, and the chain to the address at which the cell was written this time is written at that address, thereby obtaining the list structure. Can be formed. The chain write address registers (CH WA) 23-1 to 36-WR CH Tab
This is for temporarily holding the value read from le22-1 to le22-1 to 36. At the same time, for the next write, the address where the cell that has arrived this time has been written, ie, IA BUF3
WR CH Tabl
e22-1 to e22 are updated.

The reading of the cell is performed as follows. First, the output line (OUT CNT) 24 specifies the output line to be output next. The output of OUT CNT 24 is sent to an output line decoder (OUT DEC) 25, and a band counter (BW CNT) 26-1 that exists for each output line
Select one of ~ 36. BW CNT26-1 to 36
Is a counter for designating the output VPI set for each time slot. BW CNT26-1 to 3
6, the bandwidth table (BW Table) 27
With reference to -1 to 36, the VPI to be output this time is obtained. Next, using the VPI, the read address table (RD
ADR Table) 28-1 to 36. RD
The ADR Tables 28-1 to 28-36 hold the address of the buffer to be read next corresponding to the VPI, and use this address to store the buffer memory (BFM) 1
2 is fetched from the output cell 2 and demultiplexed by the DEMUX 13 and output. At the same time, a chain is read from the BFM 12, and the RD ADR Tables 28-1 to 28-36 are updated. Thereby, at the time of the next reading, the BFM 12
You can get the address inside. The address from which the cell of the BFM 12 has been read is no longer an empty address, and is stored in the empty address buffer (IA BUF) 3. Read address register (RA) 29-1
Numeral 36 is for temporarily holding values read from the RD ADR Tables 28-1 to 28-36.

The common buffer switch is configured as described above. With this switch, band control is performed as follows. That is, a bandwidth table (BW Table)
VPIs corresponding to the time slots are stored in 27-1 to 27-36 for each of the outgoing lines 502-1 to 36. For example,
The total amount of the outgoing lines 502-1 to 36 is 150 Mb / s,
When it is desired to set a virtual path having a bandwidth of 50 Mb / s, the BWTables 27-1 to 27-3
A VPI corresponding to this virtual path is set at a ratio of one address to one address. With this setting, only one cell out of every three cells having the set VPI is output from the set outgoing line, and the upper limit of the band is maintained. Also,
By setting the set addresses to the BW Tables 27-1 to 27-36 at equal intervals, the set output lines are not output at intervals shorter than the set intervals. As a result, cell inputs having a burst property can be output at equal intervals.

FIG. 3 is a conceptual diagram showing the configuration of each table in the buffer control unit. When writing a cell, VPI is applied to the chain write address registers (CH WR Table) 22-1 to 36 from the output line of the cell to be written, and the address to be accessed by the cell buffer 12 is obtained. When reading a cell, first, the line counter (OUT CNT) 24 uses the band counters (BW CNT) 26-1 to 26-36 and the band table (B).
W Table) 27-1 to 36, and read address table (RD ADR Table) 28-1 to 36
Is selected. Next, the selected BW CNT26-1
BW Tab according to the time slot specified by
The VPI to be output is obtained with reference to le27-1 to le27-1. Further, according to the VPI, the RD ADR Tab
With reference to le28-1 to le28-36, the address where the cell is stored is obtained, and the cell buffer 12 is accessed.

In this experimental example, the bandwidth tables 27-1 to 27-3 are used.
Although the example in which one is provided for each outgoing line is shown, two may be provided. In this case, when the contents of the two band tables 27-1 to 27-36 are different, the band can be instantaneously changed by switching the table to be used. In addition, by writing the bandwidth table to an unused table, the influence of rewriting on the bandwidth can be reduced. Needless to say, this switching can be performed for outgoing lines or can be performed at once. By providing two or more, it is possible to instantaneously switch a plurality of band designations.

Further, the VPI given to the table can be a part of the VPI of the cell instead of the whole. In this case, the unused bits are different VP
The cells of I are connected to the same list structure. That is, VPI
Can be grouped. As a result, the probability that the cell of the designated VPI group exists in the buffer increases, the chances of outputting the cell increase, and the capacity of the buffer can be reduced.

In the embodiment described above, an example is shown in which the band counters 26-1 to 26-36 are provided for outgoing lines. However, this can be performed by a single counter. In this case, the designation of the time slot for each outgoing line is synchronized.

Further, the cycle of the band counters 26-1 to 26-36 can be fixed and used as 256 cycles,
It can be used as a variable by setting. By making it variable, it is possible to make the minimum bandwidth of the virtual path that can be set variable.

In the above configuration, the bandwidth table 27
If no cell is connected to the list structure corresponding to the VPI specified by -1 to 36, the cell cannot be output. That is, no fluctuation is allowed for the designation of the virtual path. In order to enable the fluctuation, the VPI list structure for the preceding and succeeding time slots is also checked, and if a cell exists in the corresponding list structure, the cell is output, so that a certain degree of fluctuation is allowed. Also, in addition to the method of checking at the same time, it is also possible to store the VPI referred to in the past several slots and output it according to the presence or absence of a cell. Needless to say, multiple V
When the cell structure is output by checking the list structure corresponding to the PI, priority can be given during the cell output.

FIG. 4 is a conceptual diagram showing the configuration of each table of the buffer control unit in another embodiment. When writing a cell, a chain write address register (CH
WR Table) 22'-1 to 36 'are selected depending on the output line of the cell to be written. This CHWR Table
The lower two bits of the outgoing line designation RTG are given to 22'-1 to 36 'together with the VPI to obtain the address to be accessed by the cell buffer 12. When reading a cell,
First, the line counter (OUT CNT) 24 uses the band counters (BW CNT) 26-1 to 36, the band table (BW Table) 27'-1 to 36, and the read address table (RD ADR Table) 28 '.
-1 to 36 are selected. Next, the selected BW CN
B according to the time slot specified by T26-1 to T36
The VPI to be output is obtained with reference to W Table 27'-1 to 36. At the same time, the lower 2 bits of the designation RTG of the output line to be output are also obtained. According to the VPI and the designation of the output line, the cell buffer 12 is accessed by referring to the RD ARD Table 28'-1 to 36 to obtain the address where the cell is stored.

With such a configuration, the cell output can specify not only the VPI of the cell in the time slot but also the position of additional information such as an outgoing line when the line is separated into a low-speed line. In this case, by specifying the low-speed line number, the low-speed line number does not require a buffer for demultiplexing to a low-speed line.

In the above, an example has been shown in which the lower 2 bits of the outgoing line designation are given, but it goes without saying that other information may be given. For example, by giving information on a cell discard class, the position of a cell that can be discarded can be made periodic. That is, to refer to the table by giving the additional information means to form a list structure further classified by the additional information. Therefore, additional information can be specified and rearranged freely.

Needless to say, in the embodiment described above, instead of using the VPI, a VCI which is an identifier of a virtual channel is used, a part of the VCI is used, and a part of the VPI and one of the VCI are used. It is possible to adopt a configuration in which the sections are used at the same time.

In the above-described embodiment, the configuration in which a table is provided for outgoing lines is shown. However, it is also possible to provide one table and provide outgoing line information as additional information. That is, the exchange operation in the memory switch is equivalent to specifying the output phase of the cell, and a configuration using the same table as the specification of the output VPI can be used for specifying this phase. With such a configuration, the routing decoder (RT DE
C) 21, an output line counter (OUT CNT) 24, an output line decoder (OUT DEC) 25, and the like become unnecessary.

[0039]

According to the present invention, by using a common buffer type memory switch having a list structure for each VPI, a virtual path or a virtual path is designated while the order of cells belonging to the same virtual path or a virtual path is preserved. To output the cell. Therefore, by designating that virtual paths or virtual paths are arranged as evenly as possible, cells arriving in a burst can be evenly arranged and output, and band control can be performed.

Further, according to the band control circuit using the common buffer type memory switch according to the present invention, a virtual path or a list structure for each virtual path is created in a buffer in the switch. Therefore, a necessary buffer is not required in the band control for each output line. That is, it is possible to eliminate an increase in the buffer amount.

Furthermore, due to the common effect, the total number of buffers can be reduced in the case of the present invention in which the buffers are collectively provided in the switch, as compared with the case where the bandwidth control is performed for each output line. Furthermore, in the present invention, since the switch and the band control function share the buffer, the buffer amount of the entire apparatus can be reduced by the common effect.

In the present invention, since the band is specified and controlled by the counter and the table for specifying the virtual path or virtual channel to be output, the band can be controlled only by adding a circuit having a simple configuration to the buffer control. Switches can be configured. Also, if the contents of this table can be determined in advance so as to be optimal, band control can be performed efficiently.

Further, according to the present invention, since the band is specified using the table, the band can be changed very flexibly.
Also, by having a plurality of band tables, it is possible to change the band instantaneously.

In the common buffer switch according to the present invention, in addition to the virtual path or virtual channel, additional information can be used for classification and connection to the list structure. As a result, a cell output specifying the additional information becomes possible. For example, if a low-speed line number is also specified, it is possible to output cells so that the line number becomes periodic. This allows the separation unit for the low-speed line to periodically distribute cells to the low-speed line, thereby minimizing the buffer in the separation unit.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a configuration example of a common buffer switch according to the related art.

FIG. 3 is a conceptual diagram showing a configuration example of a table according to the embodiment of the present invention.

FIG. 4 is a conceptual diagram showing a configuration example of a table according to another embodiment of the present invention.

[Explanation of symbols]

1 ... buffer unit, 2 ... buffer control unit, 3 ...
Free address buffer (IA BUF), 11 ... MU
X, 12 ... cell buffer (BFM), 13
... DEMUX, 21 ... Routing decoder (RT DEC), 22 ... Chain write address table (CH WR Table), 23 ... Chain write address register (CH WA), 24 ... Out line counter (OUT CNT), 25 ... Out line decoder (OUT
DEC), 26 ... Band counter (BW CNT), 2
7 bandwidth table (BW Table), 28 read address table (RD ADR Table), 2
9: Read address register (RA), 501: incoming line, 502: outgoing line.

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shinobu Gobara 5030 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. Software Development Division, Hitachi, Ltd. (56) References JP-A-2-121549 (JP, A) JP-A-63-267041 (JP, A) JP-A-2-1669 (JP, A) IEICE Technical Report SSE 89-144 (February 14, 1990) (58) Fields investigated (Int. . ^7, DB name) H04L 12/28 H04L 12/56

Claims (2)

(57) [Claims] An ATM switch for switching fixed-length packets from a plurality of input lines to an arbitrary one of a plurality of output lines based on an identifier of the fixed-length packet, wherein the fixed-length packets from the plurality of input lines are exchanged. A first buffer memory for accumulating the fixed-length packet in the first buffer memory , storing a free address in the first buffer memory , and writing the fixed-length packet to the first buffer memory . An embedded address is stored for each virtual path identifier or virtual channel identifier corresponding to the destination of the fixed-length packet, and the fixed-length packet is stored in the first buffer memory for each identifier. A second buffer memory for forming a list of storage addresses, and fixing to the first buffer memory based on an output of the free address memory A write control circuit for controlling the accumulation and storage and the write address of the fixed length packet to said second buffer memory of packet, the second Baffame
The fixed-length packets stored in the first buffer memory are read using the contents of the list formed in the memory as a read address, and the fixed-length packets input from the plurality of input lines are read.
Includes a read control circuit for <br/> exchange packets with the identifier corresponding to the destination of the fixed-length packets, and a switch control circuit and a circuit for inputting the read address to the idle address memory, said plurality of input Supports fixed length packets from the line to the destination
Virtual path identifier or virtual channel
Output that is controlled for each identifier and becomes the destination of the fixed-length packet
An ATM switch characterized by switching to a line . 2. The output from the output line to the switch control circuit.
Comprising a scheduler for managing the bandwidth of fixed-length packets that force, to the scheduler below the virtual path identifier or bands set for each virtual channel identifier
The ATM switch according to claim 1, wherein fixed-length packets are exchanged.