JP3000130B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to an element isolation film for a semiconductor device having a flat surface and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a process for forming an element isolation film on a silicon substrate is one of the important steps in manufacturing a semiconductor integrated circuit. Generally, a semiconductor device includes an active region separated by an element isolation region. Therefore, the density of the semiconductor integrated circuit is limited by the size of the isolation region. This is even more remarkable in a semiconductor integrated circuit such as an EEPROM in which a high voltage region exists in a chip of the integrated circuit.

In recent years, the most widely used conventional method of forming an element isolation region is LOCOS (Local Oxi).
This process is described as follows.

An active region of a semiconductor substrate is masked as a silicon nitride film. Subsequently, after performing channel stop ion implantation into the element isolation regions between the active regions, using the silicon nitride film as a mask, only the element isolation regions of the semiconductor substrate are selectively oxidized to form a thick element isolation oxide film, that is, a thick element isolation oxide film. Then, a field oxide film is formed. At this time, the thickness of the field oxide film is formed to be 5000 ° or more. Due to the field oxide film thus formed,
Active regions on the silicon substrate will be separated.

[0005] However, the LOCOS process is not suitable for a device isolation method of a high-density semiconductor integrated circuit having sub-micro dimensions. The reason is,
During an oxide film process for forming a field oxide film, a lateral oxide film is formed below a silicon nitride film used as a masking layer.
This is because n) occurs and an oxide film is formed up to the active region, which results in a decrease in the active region. This is called the "bird's beak" phenomenon.

In the LOCOS process, a dopant implanted with channel stop ions is laterally diffused into an active region during a high-temperature heat treatment step in a field oxide film process, which makes it difficult to form a sub-micron device.

Another problem with the LOCOS process is that the thick field oxide creates a non-planar surface. This will act as a factor that has a very detrimental effect on the post-process. Due to the thick field oxide film, a step of 5000 ° or more occurs between the active region and the element isolation region adjacent thereto.

Another problem that occurs when the LOCOS process is applied to the element isolation process of a highly integrated semiconductor device is that the size of the active region and the element isolation region also decreases when the semiconductor device is highly integrated. I do. This limits the thickness of the field oxide film formed in the element isolation region between adjacent active regions. If the device isolation region is not sufficiently secured between the active regions, the electric field formed in the active region through the lower portion of the field oxide film of the device isolation region will affect the adjacent active region. May malfunction. In order to prevent this, a method of performing a so-called channel stop ion implantation, which increases the dose of channel stop ions implanted into the element isolation region before an oxidation process for forming a field oxide film, is used. The present invention utilizes a device that prevents an electric field generated in an active region by a channel stop ion implantation region formed in an element isolation region from being laterally diffused into the element isolation region. However, increasing the ion dose at the time of channel stop ion implantation results in more lateral diffusion of the implanted ions during the field oxidation process, and more penetration into the adjacent active region channel region. An adverse effect is caused, and as a result, the junction breakdown voltage (Junc
However, there is a problem that the tension voltage breakdown is reduced.

In order to solve the problems of the LOCOS process, various element isolation methods have been proposed. The method of isolating a semiconductor device disclosed in U.S. Pat. No. 5,229,315 will now be described with reference to FIGS.

First, as shown in FIG. 1, after a pad oxide film 2 and a nitride film 3 are sequentially formed on a semiconductor substrate 1, a part of the nitride film 3 in an element isolation region is formed by a photolithographic etching process. After selectively etching the pad oxide film 2 and the pad oxide film 2, a polysilicon layer 4 is formed to a predetermined thickness on a part of the exposed substrate and the entire surface of the nitride film 3, and field stop ion implantation is performed.

Subsequently, as shown in FIG. 2, after a planarizing insulating film 5 is formed on the entire surface of the polysilicon layer 4, the substrate surface is flattened by etching back until the polysilicon layer 4 is exposed. .

Next, as shown in FIG. 3, after the polysilicon layer 4 is etched using the planarizing insulating film 5 as a mask, the substrate exposed by this is etched to form a groove 7.

Subsequently, as shown in FIG. 4, after the planarizing insulating film 5 is removed, an oxide film 8 is formed on the entire surface of the substrate on which the groove 7 has been formed as described above.

Next, as shown in FIG. 5, the oxide film 8 is etched back so that the remaining polysilicon layer 4 is exposed.

Next, as shown in FIG. 6, by oxidizing the polysilicon layer 4 and removing the nitride film 3, a cylindrical element formed by being implanted into a groove 7 formed in the substrate is formed. A separation film 9 is formed.

According to the above technique, the effective channel length of the parasitic field transistor is increased, so that the element isolation characteristics are improved, and there is an advantage that a constant cylinder structure can be formed regardless of the pattern size. is there.

[0017]

However, in the above-mentioned prior art, the width of the silicon substrate at the time of etching, that is, the width of the cylindrical isolation film is reduced due to the process deviation due to the deposition and etching back of the planarization insulating film. Therefore, there is a problem that the surface of the separation film 9 is not flat due to oxidation of the polysilicon layer.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems. It is an object of the present invention to improve a process margin in an element isolation process of a highly integrated semiconductor device, and to provide a flattened element isolation film. An object of the present invention is to provide a semiconductor device which can be formed and a manufacturing method thereof.

[0019]

In order to achieve the above object, a semiconductor device according to the present invention comprises: a semiconductor substrate having an active region and an element isolation region; and a semiconductor substrate located in the element isolation region of the semiconductor substrate. A first region having a surface lower than the surface of the semiconductor substrate, a second region located on both side surfaces of the first region, having a smaller width and a deeper depth than the first region, and the first region And an element isolation film buried in the second region.

Further, in the method of manufacturing a semiconductor device according to the present invention for achieving the above object, there is provided a step of forming a multilayer insulating film on the semiconductor 11, and selectively etching the multilayer insulating film to form a multilayer insulating film. Forming a film pattern and etching a part of the semiconductor substrate exposed to a predetermined depth to form a primary recess region 17; and forming a sidewall insulating film 18 on a side surface of the laminated insulating film pattern. Forming, forming a first oxide film on the primary recess region, selectively removing the sidewall insulating film, and removing the sidewall insulating film to form a semiconductor substrate exposed by removing the sidewall insulating film. Forming a secondary recess region 20 by etching a part thereof to a predetermined depth;
Forming a second oxide film on the oxide film and the secondary recess region; and selectively removing the stacked insulating film pattern.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. 7 to 14 show a method of manufacturing a device isolation film of a semiconductor device according to the present invention in the order of steps.

First, as shown in FIG.
1 is heat-treated at a temperature of about 950 ° C. in an oxidizing atmosphere for about 15 minutes to form a pad oxide film 12 having a thickness of about 200 ° and then a low pressure CVD (LPCVD: Lo).
w Pressure Chemical Vapor
750 ° C. to 800 using the Deposition method.
A first nitride film 13 is formed on the pad oxide film 12 to a thickness of about 1500.degree. Subsequently, as an etching stopper for the nitride film on the first nitride film 13,
For example, an oxide film 14 is formed to a thickness of about 500 ° by a CVD method or a PECVD method, and then a CVD
The second nitride film 15 to 50
It is formed to a thickness of about 0 ° to 2500 °.

Next, as shown in FIG. 8, a photosensitive film is applied on the second nitride film 15 and then exposed and developed by a photolithographic etching process to form a photosensitive film pattern 16 on the active area of the substrate. Form. Next, the second nitride film 1 is formed using the photoresist pattern 16 as a mask.
5, the oxide film 14, the first nitride film 13, and the pad oxide film 12 are formed by RIE (Reactive Ion Etch).
ing) and the like, and the silicon substrate exposed by this is etched to about 500 ° to 1000 ° to form a primary recess region 17. At this time, as an etching gas at the time of the etching process, a gas containing CHF ₃ or CF ₄ is preferably used for the nitride film and the oxide film, and a gas containing HBr / Cl ₂ is preferably used for the silicon substrate.

Next, as shown in FIG. 9, after removing the photosensitive film pattern, the primary recess region 17 and the second
A third nitride film is formed on the entire surface of the nitride film 15 by CVD or PEC.
After vapor deposition to a thickness of about 1000 to 1500 degrees using the VD method, the side wall nitride film 18 is formed by etching back to a thickness equal to or greater than the vapor deposition thickness.

Next, as shown in FIG. 10, a lamination pattern of an insulating film composed of the pad oxide film 12, the first nitride film 13, the oxide film 14, and the second nitride film 15 and the side wall nitride film are formed. 18 and O ₂ at temperatures above 850 ° C. using as oxidation mask, or H ₂ + O heat treated at ₂ oxidizing atmosphere, the exposed silicon substrate surface, i.e., about 500Å~ primary recess region 17 1 with a thickness of about 1000 mm
Next, a field oxide film 19 is formed. At this time, the thickness of the primary field oxide film 19 is set so that the surface of the field oxide film is lower than the substrate surface in the element formation region or the active region.

Subsequently, as shown in FIG. 11, the side wall of the nitride film and the second nitride film are selectively removed by anisotropic dry etching or the like to expose a predetermined portion of the surface of the silicon substrate.

Subsequently, as shown in FIG. 12, a part of the exposed silicon substrate is placed on the laminated pattern 1 of the insulating film.
Using the masks 2, 13, and 14 and the primary field oxide film 19 as a mask, the secondary recess region 20 is formed by etching at about 1000 °. Next, B ⁺ or BF ₂ ions are implanted into the surface of the exposed substrate in the secondary recess region 20 at a concentration of 2-3 × 10 ¹³ / cm ² at an acceleration voltage of 40-80 KeV to thereby form the impurity diffusion layer 21. To form

Subsequently, as shown in FIG.
The first oxidation is performed at a temperature of 00 ° C. in an oxidizing atmosphere containing O ₂ and H ₂ for 50 to 150 minutes.
500 to 4000 in the next recess area and the second recess area
A secondary field oxide film 22 having a thickness of about Å is formed.
At this time, the thickest part of the secondary field oxide film 22 is about 1000 to 5000 degrees by adding the thickness of the formed primary field oxide film 19 and the secondary field oxide film 22. By doing so, the thickness is set so that the surface of the field oxide film region, that is, the surface of the element isolation region is not higher than the surface of the silicon substrate in the element region or the active region by 1000 ° or more.

On the other hand, as an embodiment of the present invention, the CV is formed without forming the secondary field oxide film by a thermal oxidation process.
After depositing an oxide film by D method or LPCVD method,
It is also possible to form a secondary field oxide film filling the recess region by etching back.

Next, as shown in FIG.
4. By sequentially etching and removing the nitride film 13 and the pad oxide film 12, a device isolation film 22 having a flattened surface is formed. In the etching of the oxide film 14, the nitride film 13, and the pad oxide film 12, a solution containing hydrofluoric acid (HF) is used for an oxide film, and phosphoric acid (H ₃ PO ₄ ) is used for a nitride film. This is performed by a wet etching process using a solution.

[0031]

As described above, according to the present invention, in forming an element isolation film embedded in a substrate, a silicon substrate can be etched to a constant width regardless of a pattern size. The process margin during substrate etching is improved, and the surface of the silicon substrate in the element region or active region and the surface of the element isolation region are flattened, ensuring focus merging in the subsequent photolithography etching process. Therefore, generation of an etching residue due to a step between the active region and the element isolation region can be suppressed.

[Brief description of the drawings]

FIG. 1 is a process flow chart showing a conventional element isolation method for a semiconductor device.

FIG. 2 is a process sequence diagram showing a conventional element isolation method of a semiconductor device.

FIG. 3 is a process flow chart showing a conventional element isolation method of a semiconductor device.

FIG. 4 is a process flow chart showing a conventional element isolation method of a semiconductor device.

FIG. 5 is a process flow chart showing a conventional element isolation method of a semiconductor device.

FIG. 6 is a process sequence diagram showing a conventional element isolation method for a semiconductor device.

FIG. 7 is a process flow chart showing a device isolation method of a semiconductor device according to the present invention.

FIG. 8 is a process flow chart showing a device isolation method of a semiconductor device according to the present invention.

FIG. 9 is a process flow chart showing a device isolation method of a semiconductor device according to the present invention.

FIG. 10 is a process sequence diagram showing a method for isolating a semiconductor device according to the present invention.

FIG. 11 is a process flow chart showing a device isolation method of a semiconductor device according to the present invention.

FIG. 12 is a process flow chart showing a device isolation method of a semiconductor device according to the present invention.

FIG. 13 is a process flow chart showing a device isolation method for a semiconductor device according to the present invention.

FIG. 14 is a process flow chart showing a device isolation method of a semiconductor device according to the present invention.

[Explanation of symbols]

11 semiconductor substrate, 12 pad oxide film, 13 first nitride film, 14 etching stopper, 15 second nitride film, 16 photosensitive film pattern, 17 primary recess region, 1
8 ... sidewall insulating film, 19 ... first oxide film, 20 ... secondary recess region, 21 ... impurity diffusion layer, 22 ... second oxide film.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-34556 (JP, A) JP-A-60-38832 (JP, A) JP-A-61-290737 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/76

Claims (1)

(57) [Claims] A step of forming a multilayer insulating film on the semiconductor; and selectively etching the multilayer insulating film to form a multilayer insulating film pattern. Is etched to a predetermined depth to form a primary recess region (1).
7) forming a sidewall nitride film on the side surface of the laminated insulating film pattern; and forming a first oxide film on the primary recess region below a height of the substrate lower than the height of the substrate. Forming a portion of the exposed semiconductor by etching to a predetermined depth by removing the sidewall nitride film; and forming a secondary recess by removing the sidewall nitride film. Forming a region (20); and using a hot acid using the laminated insulating film pattern as an oxidation mask.
Process by said primary recessed region and the second oxide film (22) on said first oxide layer and the second recess region
A method for manufacturing a semiconductor device, comprising: forming a secondary recess region so as to be buried ; and selectively removing the stacked insulating film pattern.