JP2979653B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus which operates under the control of a micro instruction.

[0002]

2. Description of the Related Art A conventional information processing apparatus of this type does not have a function of operating with a clock signal of a single cycle and switching to a clock signal of a different cycle according to an execution address of an arbitrary microinstruction. Was.

[0003]

Since the above-mentioned conventional information processing apparatus operates with a single-cycle clock signal, the processing operation performed by the hardware unit and the processing operation performed by the microprogram unit are performed. In a device including, for example, when the processing by the hardware unit is longer than the time executed by the microprogram unit, the clock cycle executable by the former is used. There is a disadvantage that the information processing speed cannot be increased because a clock signal of a short cycle that can operate cannot be used.

Further, in an apparatus which performs a preset process using only a group of micro-instructions, the execution time for executing most of the micro-instructions is short, but the execution time for some of the micro-instructions is long. Must use a clock signal having a cycle capable of executing the micro instruction having the longest execution time, so that when executing the instructions of the above-described micro instruction group, the cycle of the clock signal can be shortened as a whole. not there is a drawback that it can not shorten the processing time of information.

It is an object of the present invention to use a clock signal having a short period when executing an instruction which can be executed at a high speed, and to execute an instruction which must be executed at a low speed. It is an object of the present invention to provide an information processing apparatus capable of selecting and using a clock signal having a long cycle capable of executing such an instruction.

[0006]

According to the present invention, there is provided an information processing apparatus according to the present invention, wherein an address of a microinstruction stored in a control storage means is stored in the control storage means in accordance with an address signal from a microinstruction holding means which holds the addresses in the execution order. A microinstruction stored at the address specified by the address signal from the microinstruction executing means, and executes a process corresponding to the microinstruction taken out by the microinstruction executing means to perform processing of preset information. The microinstructions stored in the control storage means
And the address of the first microinstruction predetermined in
Store and output the address of the second microinstruction respectively
First and second registers and the microinstruction holding means
And the output of the first register are compared.
Outputting a first match signal when the forces match
The output of the comparator and the micro instruction holding means and the
The outputs of the second register are compared, and both outputs match.
When the second comparator outputs the coincidence signal
The microinstruction address comparing means having:
OR gate for generating and outputting a logical sum of the first and second coincidence signals
And the output of the OR gate as a set input and reset
Signal as a reset input, and
The first Q output and the negative value of the first Q output
Output first RS flip-flop and the first match
Signal as a set input and the second coincidence signal as a reset input
And controlled synchronously by the first clock signal.
A second Q output that outputs a negative value of the second Q output and the second Q output.
And the negative value of the first Q output
A logical product of the second Q output is generated and used as a first selection signal.
Output from the first AND gate and the first Q output
A logical product of a constant value and a negative value of the second Q output is generated,
And a second AND gate for outputting as a selection signal of
Clock cycle switching instructing means and clocks having different cycles from each other.
First and second clock generating means for generating a lock signal
And the second Q signal with the first Q signal as input
Therefore, synchronous control is performed, and the set signal and the set signal are
A third flip-flop for outputting a negative value and the set
The negative value of the signal, the negative value of the first Q output and the first
Generates the logical product of the clock signal and the clock signal
A third AND gate to be output and the first selection signal.
And Tsu reset input before the reset input of the issue said second selection 択信
The fourth Q output is synchronously controlled by the second clock signal.
And a fourth RS free signal for outputting a negative value of the fourth Q output.
Controlled by the flip-flop and the fourth Q output.
The second clock generating means when the Q output is "1";
And the fourth Q output is "0"
Select the output from the first clock generating means.
A first selector for outputting the first clock signal;
The fourth Q is controlled by a negative value of the fourth Q output.
When the negative value of the output is "1", the second clock is generated.
Selecting the output from the generator and negating the fourth Q output
When the value is "0", the first clock generation means
And outputs the second clock signal.
The clock circuit section having a selector of
The output of the third AND gate is used as a clock for information processing operation.
It is characterized in that the signal is a clock signal.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention.

The logic circuit section 1 has a control storage means 3 for storing a plurality of microinstructions and a microinstruction address holding means for storing the addresses of the microinstructions stored in the control storage means 3 in the order of execution. Micro-instruction holding means 4 for temporarily holding a micro-instruction 100 output from the control storage means 3 by the address signal 103 output from the micro-instruction address holding means 7;
Microinstruction decoding means 5 which decodes the microinstruction 101 held by the microinstruction holding means 4 and converts it into an instruction 102 which can be operated by a microinstruction execution means which will be described later; and information corresponding to the decoded instruction 102 Micro-instruction executing means 6 for performing the above-mentioned processing, and an address in the aforementioned control storage means 3 at which a plurality of predetermined micro-instructions among the micro-instructions stored in the aforementioned control storage means 3 are stored. And compares the address signal 104 output from the microinstruction address holding means 7 with the address of the previously stored microinstruction, and when they match, a match signal (e.g., In FIG. 1, 110 and 1
11), and a clock switching instructing means 9 for designating a clock signal having a cycle corresponding to the coincidence signals 110 and 111. Each of these components is a clock signal 109 output from a clock circuit unit 2 described later.
Synchronize control.

The clock circuit section 2 generates first clock signals 122 and 123 having different periods from each other.
In response to the designation of the clock generation means 10 and the second clock generation means 11 and the clock cycle switching instruction means 9 described above, one of the clock signals 122 and 123 is selected and output as the clock signal 109. And a clock cycle switching means 12.

Now, it is assumed that the cycle of the clock signal 122 is shorter than the cycle of the clock signal 123.
Requires a longer execution time than when executing other micro-instructions only when executing a specific micro-instruction stored in the micro-instruction. It is assumed that the program can be executed even when the synchronization is controlled by the clock signal 122 described above.

In such a case, the address at which the specific microinstruction is stored in the control storage means 3 is stored in the microinstruction address comparison means 8, and the specific instruction is stored in the microinstruction address comparing means 8. When a microinstruction is executed and a microinstruction different from this specific microinstruction is executed, the microinstruction executed immediately after the execution of the specific microinstruction is stored in the control storage means 3 described above. The addresses stored in the micro instruction address comparing means 8 are also stored in advance.

In this way, immediately before the above-mentioned specific micro-instruction is executed by the above-mentioned micro-instruction address comparing means 8, the clock signal 122 capable of executing this micro-instruction is selected, and synchronization control is performed by this clock signal. The micro-instruction is executed by executing the above-described clock signal 123 when the other micro-instruction is executed.
Can be used to execute microinstructions.

FIG. 2 is a block diagram showing one embodiment of the microinstruction address comparing means 8, the clock cycle switching instructing means 9 and the clock circuit section 2 shown in FIG. 1, and FIG. 6 is a timing chart illustrating the operation of each of the illustrated parts.

As the clock signal 109 shown in FIGS. 1 and 2, it is assumed that the output signal 122 supplied from the first clock generating means 10 is selectively output.

Among the micro-instructions stored in the control storage means 3 described with reference to FIG. 1, the above-mentioned micro-instructions which need to operate under the synchronous control of a specific clock signal are stored. The address value A in the control storage means 3 is stored in advance, and this address value A is output signal 10
7 and the above-mentioned control storage means 3 which stores the micro-instruction for other micro-instructions following the above-mentioned specific micro-instruction.
Is stored in advance, and this address value B
Is output as the output signal 108, the output signal 107 is compared with the address signal 104 output from the microinstruction address holding means 7, and when they match, a logical value is set as the first match signal 111. A first comparator 15 that outputs a value “1”, and a second comparator that compares an output signal 108 with the above-described address signal 104 and outputs “1” as a second match signal 110 when they match. The address signal 10 inputted to the micro-instruction address comparing means 8 comprising
4 matches the address value A, the first comparator 15 outputs the first match signal 111 having the value “1”, and the OR gate 17 and the second flip-flop 22 in the clock cycle switching instructing means 9 are output. To the set input terminal S.

The output of the OR gate 17 becomes "1" and this output is applied to the set input terminal of the first flip-flop 21 in the clock cycle switching instructing means 9.

The first and second flip-flops 21
And 22 are RS flip-flops that are synchronously controlled by a first clock signal 124. As the first clock signal 124, the output signal 122 of the first clock generating means 10 is the first signal in the clock circuit unit 2. Selector 2
5 is selectively connected and output.

From the Q output terminal of the first flip-flop 21, a Q signal output 112 having a value "1" is output.
To the input side of the third flip-flop 23 in the clock circuit section 2 of FIG. Also, the first flip-flop 2
From the output of the negative value of Q of 1, the signal 11 having the value "0" is output.
3 is output and applied to the input of the third AND gate 20 in the clock circuit unit 2. When the signal 113 is input, the output of the clock signal 109 which has been output as the output from the AND gate 20 is interrupted.

The third flip-flop 23 is synchronously controlled by a second selector 26 in the clock circuit section 2 by a second clock signal 125 connected to the output signal 123 of the second clock generator 11. D flip-flop.

The third flip-flop 23 outputs a reset signal 118 which is a Q signal having a value "1" in response to the input of the Q signal 112 having the value "1" and an output signal having a negative value of Q. The value “0” is set to the third as 119
The output of the clock signal 109 is interrupted in addition to the input of the AND gate 20 of FIG.

Since this reset signal 118 is applied to the reset terminal R of the first flip-flop 21, the first
The value of the Q signal output 112 of the flip-flop 21 becomes “0”, and the value of the output signal 113 having a negative value of Q becomes “1”. Accordingly, the value of the output signal 119 of the negative value of Q of the third flip-flop 23 becomes “1”, so that the clock signal 109 can be output from the third AND gate 20 if the first clock signal 124 is added. State.

As described above, the first coincidence signal 1
When 11 is input to the set terminal S of the second flip-flop 22, a signal 114 having a value “1” is output from the Q output of the second flip-flop 22. The Q output signal 114 of the second flip-flop 22 is input to the first AND gate 18 in the clock cycle switching instructing means 9 together with the output signal 113 of the negative value of Q of the first flip-flop 21 described above. You.

As described above, the output signal 1 of the negative value of Q of the first flip-flop 21 is generated by the reset signal 118.
When the value of 13 becomes "1", the value of the Q output signal 114 has already become "1", so that the first selection signal 116 having the value "1" is output from the first AND gate and the clock circuit unit 2 to the set terminal S of the fourth flip-flop 24. The fourth flip-flop 24 is an RS flip-flop controlled by the second clock signal 125.

When the first selection signal 116 is input to the fourth flip-flop 24, the value "1" is output as the Q output signal.
Is output.

The first selector 25 is controlled by the signal 120. When the signal 120 has the value "1", the first selector 25 selects the output signal 123 of the second clock generating means 11 and outputs it as the first clock signal 124. , And signal 1
When the value of 20 is "0", the first clock generation means 1
An output signal 122 of 0 is output as a first clock signal 124.

The value of the signal 121, which is the output of the negative value of Q of the fourth flip-flop 24, is "0" in the case described above. The second selector 26 is controlled by the signal 121. When the value of the signal 121 is "0", the output signal 122 of the first clock generating means 10 is selectively connected and output as the second clock signal 125. When the value of the signal 121 is "1", the output signal 123 of the second clock generating means 11 is selected and output as the second clock signal 125. In the above case, the second clock is output by the second selector 26. The signal 122 is selectively output as the signal 125.

The above-mentioned first flip-flop 21 is connected to the input side of the third AND gate 20 in the clock circuit section 2.
Output 113 of the negative value of Q and the third flip-flop 2
The output 119 of the negative value of Q of 3 and the first clock signal 12
4 is connected, in the above-described state, the output signal 123 from the second clock generating means 11 is selected and output as the output signal 109 of the third AND gate as the clock signal.

Next, in the above-described state, the address designation signal 104 from the micro-instruction address holding means 7 is changed to the clock signal 1 generated by the second clock generation means 11.
When the second comparator 16 outputs a signal synchronized with the address value B of the microinstruction of the second register 14 under the synchronous control of the second register 14, the second comparator 16 having the value “1”
Is output to the OR gate 17 and the reset terminal R of the second flip-flop 22.

The value "1" is output from the OR gate 17, the Q output signal 112 of the first flip-flop 21 becomes "1", and the output 113 of the negative value of Q becomes "0". The output of the clock signal 109 from 20 is interrupted. During this time, the third flip-flop 2
Reset signal 118 having a value “1” from the Q output terminal
Is output to the reset terminal R of the first flip-flop 21 to put the first flip-flop 21 in a reset state, so that the Q output signal 1 of the first flip-flop 21
12 becomes “0” and the output signal 1 of the negative value of Q
The value of 13 becomes “1”. However, these operations are synchronously controlled by the first clock signal 124, and this clock signal 124 is the signal 123 selectively connected by the first selector 25.

As a result, the value of the negative value output 119 of Q of the third flip-flop 23 also becomes "1" and can be output as the clock signal 109 when the first clock signal 124 is again input to the third AND gate. State. Here, the signal 122 is selectively used by the second selector 26 as the second clock signal 125 for controlling the synchronization of the third flip-flop 23.

On the other hand, the second comparator 16
Of the second flip-flop 22 by the coincidence signal 110 of
Is reset, so that the output signal 113 of the negative value of Q of the first flip-flop 21 and the signal 115 of the negative value of Q of the second flip-flop 22 are input. A second selection signal 117 having a value “1” is output from the second AND gate 19,
It is applied to the reset terminal R of the fourth flip-flop 24.

The fourth flip-flop 24 outputs the signal 117
, The value of the signal 121 which is the output of the negative value of Q becomes “1”, and the value of the signal 120 becomes “0”.
Becomes Therefore, the signal 12
2 is selected and output as the first clock signal 124, and the signal 123 is selected by the second selector 26 and output as the second clock signal 125, so that the third AND gate 20 outputs The signal 122 output from the first clock generation means 10 is the clock signal 10
9 will be output.

[0034]

As described above, the information processing apparatus of the present invention, when a micro instruction having a long processing time is executed in advance, executes the micro instruction with a clock signal having a long cycle capable of executing the micro instruction. When shifting from the specific micro-instruction with a long execution time to the micro-instruction with a short execution time, a clock signal having a short cycle in which the micro-instruction can be executed is selected, and information processing is performed by the selected clock signal. Since it can be executed, there is an effect that information processing can be efficiently performed in a short time as compared with a conventional information processing apparatus of this type.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of an information processing apparatus according to the present invention.

FIG. 2 is a block diagram showing an example of a micro-instruction address comparing unit, a clock cycle switching supporting unit, and a clock circuit unit of FIG. 1;

FIG. 3 is a flowchart for explaining the operation of FIG. 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logic circuit part 2 Clock circuit part 3 Control storage means 4 Micro instruction holding means 5 Micro instruction decoding means 6 Micro instruction execution means 7 Micro instruction address holding means 8 Micro instruction address comparison means 9 Clock cycle switching instructing means 10 First clock Generating means 11 second clock generating means 12 clock cycle switching means 13 first address register 14 second address register 15 first comparator 16 second comparator 17 OR gate 18 first AND gate 19 second AND Gate 20 Third AND gate 21 First flip-flop 22 Second flip-flop 23 Third flip-flop 24 Fourth flip-flop 25 First selector 26 Second selector

Claims (1)

(57) [Claims] 1. An address designated by the address signal from the control storage means according to an address signal from a microinstruction holding means which holds the addresses of the microinstructions stored in the control storage means in the order of execution. In the information processing apparatus for performing processing of preset information by executing a process corresponding to the extracted microinstruction by the microinstruction execution unit by extracting the microinstruction stored in the control storage unit, Ma
Of the first micro-instruction predetermined in the micro-instruction
Address and the address of the second microinstruction respectively
First and second registers for storing and outputting, and
Comparing the output of the first instruction register with the output of the first register.
When the two outputs match, the first match signal is output.
Of the first comparator and the microinstruction holding means
Comparing the output of the second register with the output of the second register.
Output the second coincidence signal when
Said microinstruction address comparison means having a comparator
And a stage for generating and outputting a logical sum of the first and second coincidence signals
OR gate and the output of the OR gate
A reset signal as a reset input and a first clock signal
The first Q output and the first Q output are synchronously controlled by
A first RS flip-flop that outputs a negative value of
Using the first coincidence signal as a set input, the second coincidence signal
Synchronized by the first clock signal as a reset input
Controlled output of the second Q output and the negative value of the second Q output
A second RS flip-flop and the first Q output
The logical product of the negated value of
A first AND gate that outputs a selection signal and the first AND gate.
The logical product of the negative value of the Q output and the negative value of the second Q output is
A second AND gate for generating and outputting as a second selection signal
Clock cycle switching instructing means having
First and second clocks for generating different clock signals
Generating means, and a second clock receiving the first Q signal as input.
The set signal and the set
And a third flip-flop that outputs a negative value of the
The negative value of the set signal and the negative value of the first Q output
A logical product with the first clock signal is generated to generate a clock signal.
And a third AND gate for outputting as a signal
Signal is set input and the second selection signal is reset input
The fourth clock signal is synchronously controlled by the second clock signal.
And a fourth output that outputs a negative value of the fourth Q output and the fourth Q output.
Controlled by an RS flip-flop and the fourth Q output
When the fourth Q output is "1", the second clock
The output from the generating means is selected and the fourth Q output is
When "0", the output from the first clock generation means is output.
A first cell for selecting a first clock signal and outputting the first clock signal.
Controlled by the negative value of the fourth Q output
When the negative value of the fourth Q output is "1", the second
Selecting the output from the clock generation means and selecting the fourth Q
When the negative value of the output is "0", the first clock is generated.
Output from the generating means and output the second clock signal.
The clock circuit unit having a second selector for inputting the clock signal;
And outputs the output of the third AND gate in the previous period for the information processing operation.
An information processing apparatus characterized in that the information processing apparatus uses a clock signal for the same .