JP2970836B2 - Data signal transmission / reception system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data signal transmission / reception system, and more particularly, to a transmission apparatus for transmitting transmission data in synchronization with a clock signal from a transmission apparatus, and for a reception apparatus to transmit the transmission data to the clock within the apparatus. The present invention relates to a data signal transmission / reception system adapted to take in synchronization with a signal.

[0002]

2. Description of the Related Art An example of a conventional data transmission / reception system of this type will be described with reference to FIG. In FIG. 4, the transmission device 100 has a D-type flip-flop (hereinafter simply referred to as FF) 4 having a latch function.
Reference numeral 4 denotes a unit for transmitting transmission data to the transmission line 300 while latching transmission data in synchronization with a clock signal supplied from the receiving device 200 via the transmission line 300.

In the receiving device 200, the transmission data from the transmission line 300 is latched by the FF 12 in synchronization with the clock signal and becomes one input of the selector 16 while the FF 13
Is latched in synchronization with the inverted signal of the clock signal by the inverter 14, and further latched in synchronization with the clock signal by the FF 15 and becomes another input of the selector 16.

FIG. 5 shows an example of the waveform of each part of the block of FIG. 4. The waveforms of FIGS. 5A to 5D correspond to the waveforms of the signals a to d of each part of the block of FIG. Shall be shown.

[0005] The clock signal of the receiving apparatus 200 is shown in FIG.
In the case of (a), a clock signal delayed by the delay time t by the transmission line 300 is supplied to the clock input of the FF 4 of the transmission device 100 as shown in FIG. 5B. The transmission data is identified and latched by the FF 4 by this clock signal, and is transmitted as transmission data as shown in FIG. 5C.

Since this transmission data is also supplied to the receiving device 200 with a delay of the delay time t of the transmission line 300, it has a phase difference of 2t from the clock signal in the receiving device 200 as shown in FIG. Such a data signal is obtained.

In the receiving apparatus 200, two kinds of clock signals of a normal phase and a negative phase are controlled by the inverter 14 so that the rising edge (latch timing) of the clock signal does not approach the changing point (level transition point) of the received data signal d. FF12, FF13, and FF15 are used to identify and latch received data, respectively, and an oscilloscope or the like is used to observe which latch output is appropriate in consideration of the phase difference of 2t. The selector 16 is manually switched.

[0008]

In such a conventional data signal transmitting / receiving system, selection of a clock signal capable of identifying a data signal in a receiving device is measured by a measuring instrument such as an oscilloscope, and clock signal switching is performed by manual operation. Is disadvantageous because it is complicated.

An object of the present invention is to provide a data signal transmission / reception system which automatically selects a clock signal for data identification and eliminates the complexity of manual operation.

[0010]

According to the present invention, there is provided a receiving apparatus for generating a clock signal and receiving received data in synchronization with the clock signal, and supplying the clock signal from the receiving apparatus. And a transmitting device for transmitting transmission data to the receiving device in synchronization with the clock signal, wherein the transmitting device responds to a system activation from the receiving device for a certain period of time. Clock wrapping means for wrapping and transmitting the supplied clock signal to the receiving device;
And a data transmitting means for transmitting the transmission data in synchronization with the clock signal to the receiving device, the receiving device,
Phase difference detecting means for detecting a phase difference between the clock signal transmitted from the transmitting device during the certain period and the generated clock signal in the own device, and synchronizing transmission data from the transmitting device with the generated clock signal. First latch means for taking in the data, second latch means for taking in synchronism with a clock signal opposite to the generated clock signal, and the first and second latch means in accordance with the detection result of the phase difference detecting means. And a selecting means for selectively deriving the output of the data signal.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention will be described. When a system is started up at the time of power-on or the like, a clock signal supplied from the receiving side is transmitted back to the transmitting side for a certain period of time and transmitted to the receiving side. A phase difference between a transmitted clock signal and a clock signal in the apparatus is detected, and a data signal discriminated and latched by either a normal phase clock signal or a reverse phase clock signal is selected according to the phase difference. This eliminates manual data signal selection.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention, and the same parts as those in FIG. 4 are denoted by the same reference numerals. In FIG. 1, a selector 2 is provided in a transmission device 100, and a latch output of the FF 4 is output to the reception device 200.
Of the clock signal supplied from the selector 2
And transmitted to the transmission path 300.

A counter 1 is provided to control the selection of the selector 2. The counter 1 counts a supply clock signal and generates a switching signal when the supply clock signal reaches a constant value. In response to power-on at the time of starting the system, the selector 2 counts a clock signal supplied from the receiving device, and when the counter 1 reaches a predetermined value, the counter 1 generates a switching signal so that the selector 2 selects the latch output of the FF 4. To control.

Further, a signal disconnection detection circuit 3 is provided so that when the clock signal supplied from the receiving device is disconnected, the counter 1 is reset to return to the initial state.

In the receiving device 200, the FFs 12, 13, 1
5, a clock signal detection circuit 10 and a phase difference detection circuit 11 are provided in addition to the inverter 14 and the selector 16. The phase difference detection circuit 11 detects a phase difference between the clock signal of the transmission apparatus 100 and the clock signal returned from the transmission apparatus 100, that is, a round-trip delay time 2t of the transmission path 300.

The clock signal detecting circuit 10 includes a transmitting device 10
When the supply clock signal from 0 is no longer detected, the phase difference detection function of the phase difference detection circuit 11 is stopped. The other configuration is the same as that of FIG. 4 and the description is omitted.

FIG. 2 shows a waveform example of a signal transmitted from the transmitting apparatus 100 for explaining the operation of FIG. When the system is activated and powered on, the transmitting device 10
When 0 rises, the selector 2 first selects the clock signal supplied from the receiver and transmits it to the transmission line 300, and the counter 1 starts counting the clock signal.
This state is maintained until the count value reaches the constant value A. During this time, the receiving apparatus 200 uses the phase difference detection circuit 11
Operates to detect the phase difference between the clock signal of its own device and the clock signal from the transmitting device.

When the count value of the counter 1 reaches a constant value A, the selector 2 selects the latch output of the FF 4 and transmits it to the transmission line 300. On the receiving side 200, the phase difference detection circuit 11 The phase difference, that is, the transmission path 30
0 delay time 2t is detected, and this delay time 2t
, The selection of the selector 16 is controlled.

When the count value of the counter 1 reaches a constant value A, the transmission of the clock signal from the transmitting device is stopped. This is detected by the clock signal detecting circuit 10 and the function of the phase difference detecting circuit 11 is stopped. You.

FIG. 3 shows the relationship between the timing of the reception data DATA transmitted from the transmission device 100 and the timing of the identification clock signal in the reception device.
(C). (A) shows that the received data is latched at the rising timing of the clock signal to identify the received data.

FIG. 2B shows that the rising edge of the clock signal is near the transition point of the received data due to the delay 2t of the transmission line 300, and the data identification is not performed correctly. Therefore, in this case, as shown in (C), the FF1 that uses the inverted clock signal as the latch timing is used.
If the data of the path 3 is controlled to be selected by the selector 16, the change point of the received data is far from the rising timing of the inverted clock signal, so that the state becomes close to (A) and the received data can be correctly identified. It becomes.

The FF1 latched by the positive-phase clock signal
The reason why 5 is provided after the FF 13 is to adjust the phase of the data to the normal phase timing of the clock signal.

The phase difference 2t (t
Is a variable that fluctuates according to the distance of the transmission path 300). It is obvious that which latch output should be selected may be determined in advance according to the phase difference.

Since the disconnection detection circuit 3 resets the counter 1 when the clock signal is disconnected, the operation of the phase difference detection circuit 11 becomes possible again when the clock signal is restored.

[0026]

As described above, according to the present invention, even if the data signal change point and the clock signal rising point are close to each other due to the delay state of the transmission path, the phase difference can be detected. Then, the most suitable one is automatically selected as the phase of the latch clock signal, so that there is an effect that the need for manual operation is eliminated. In addition, since a clock signal is returned from the transmitting device to detect the phase difference, the clock signal is placed at the head of the data signal, so that there is no need to provide a transmission path for returning the clock signal.

[Brief description of the drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a waveform of a transmission signal from a transmission side to a reception side in the block of FIG.

FIG. 3 is a timing chart of waveforms showing the operation of the example of the present invention.

FIG. 4 is a block diagram of a conventional data signal transmission / reception system.

FIG. 5 is a waveform diagram of each part showing the operation of the block in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Counter 2, 16 Selector 3 Disconnection detection circuit 4, 12, 13, 15 FF 10 Clock signal detection circuit 11 Phase difference detection circuit 14 Inverter 100 Transmitting device 200 Receiving device 300 Transmission line

Claims (4)

(57) [Claims] 1. A receiving device which generates a clock signal and takes in received data in synchronization with the clock signal, and receives a supply of the clock signal from the receiving device and synchronizes with the clock signal. A transmission device for transmitting transmission data to the reception device, wherein the transmission device transmits a clock signal supplied from the reception device for a predetermined period in response to a system activation. Clock wrapping means for wrapping and sending back to
And a data transmitting means for transmitting the transmission data in synchronization with the clock signal after the over to the receiving apparatus, the receiving apparatus, generation of the predetermined period to the transmission equipment clock signal and the own apparatus has been transmitted from the Phase difference detecting means for detecting a phase difference from a clock signal; first latch means for taking in transmission data from the transmitting device in synchronization with the generated clock signal; A second latch unit which takes in in synchronization with the first and second latch units according to a detection result of the phase difference detecting unit;
And a selection means for selectively deriving an output of the latch means. 2. The transmission device according to claim 1, wherein the transmitting device is configured to transmit the clock for the predetermined period .
2. The data signal transmission / reception system according to claim 1, further comprising transmission selection means for transmitting an output of the lock return means and thereafter transmitting transmission data synchronized with the clock signal. 3. The clock wrapping means has counting means for counting the clock signal in response to system activation, and when the count value reaches a preset value, the transmission selection means selects the state. 3. The data signal transmitting / receiving system according to claim 2, wherein the data signal is switched. 4. The clock return means according to claim 2, wherein said clock return means has a disconnection detecting means for resetting said counting means in response to detection of a disconnection of a clock signal supplied from said receiving device. Data signal transmission / reception system.