JP2951703B2 - Interference compensator - Google Patents

Interference compensator

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Publication number
JP2951703B2
JP2951703B2 JP20658790A JP20658790A JP2951703B2 JP 2951703 B2 JP2951703 B2 JP 2951703B2 JP 20658790 A JP20658790 A JP 20658790A JP 20658790 A JP20658790 A JP 20658790A JP 2951703 B2 JP2951703 B2 JP 2951703B2
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JP
Japan
Prior art keywords
signal
input
output
circuit
interference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP20658790A
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Japanese (ja)
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JPH0490625A (en
Inventor
俊之 貝塚
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Nippon Telegraph and Telephone Corp
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Nippon Telegraph and Telephone Corp
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Priority to JP20658790A priority Critical patent/JP2951703B2/en
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、無線通信の干渉補償装置に利用する。特
に、干渉波を抑圧して希望する信号を受信する装置に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for an interference compensation device for wireless communication. In particular, the present invention relates to a device that suppresses an interference wave and receives a desired signal.

〔従来の技術〕[Conventional technology]

第2図は従来例の干渉補償装置のブロック構成図であ
る。
FIG. 2 is a block diagram of a conventional interference compensation apparatus.

従来、干渉補償装置は、第2図に示すような構成であ
った。第2図において、1、2は入力端子、3は振幅位
相制御回路、4は信号合成回路、5A、5Bは増幅器、周波
数変換器および帯域濾波器などから構成される信号受信
回路、7、8は乗積検波器、10は干渉波補償出力端子な
らびに17は90゜移相器を示す。
Conventionally, the interference compensator has a configuration as shown in FIG. In FIG. 2, reference numerals 1 and 2 denote input terminals, 3 denotes an amplitude and phase control circuit, 4 denotes a signal synthesizing circuit, 5A and 5B denote signal receiving circuits composed of an amplifier, a frequency converter, a bandpass filter, and the like; Denotes a product detector, 10 denotes an interference wave compensation output terminal, and 17 denotes a 90 ° phase shifter.

入力端子1には通常の通信のための信号が入力する
が、干渉波も混入する。入力端子2には主に干渉波が入
力する。入力端子2に入力した干渉波は2系統に分岐さ
れ、一方の信号は振幅位相制御回路3でその振幅および
位相が制御され、入力端子1からの信号と信号合成回路
4で合成される。この合成信号と入力端子2の他方の信
号とはそれぞれ信号受信回路5A、5Bで周波数変換および
増幅された後、さらに2分岐され乗積検波器7、8で検
波される。このとき乗積検波器7、8に入力する四つの
信号の内の一つは90゜移相器17で90゜位相推移される。
この乗積検波器7、8の出力信号は入力端子1から入力
される干渉波と入力端子2から入力される干渉波との振
幅が同じで位相が反転するように振幅位相制御回路3を
制御する。以上により干渉波補償出力端子10の出力に干
渉波の含まれない信号が得られる。
A signal for normal communication is input to the input terminal 1, but an interference wave is also mixed. The input terminal 2 mainly receives an interference wave. The interference wave input to the input terminal 2 is branched into two systems. One of the signals is controlled in amplitude and phase by an amplitude / phase control circuit 3, and is combined with a signal from the input terminal 1 by a signal combining circuit 4. The synthesized signal and the other signal at the input terminal 2 are frequency-converted and amplified by the signal receiving circuits 5A and 5B, respectively, and further branched into two to be detected by the product detectors 7 and 8. At this time, one of the four signals input to the product detectors 7 and 8 is shifted by 90 ° in phase by the 90 ° phase shifter 17.
The output signals of the product detectors 7 and 8 control the amplitude and phase control circuit 3 so that the amplitude of the interference wave input from the input terminal 1 and the amplitude of the interference wave input from the input terminal 2 are the same and the phases are inverted. I do. As described above, a signal that does not include an interference wave is obtained in the output of the interference wave compensation output terminal 10.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかし、このような従来例の干渉補償装置では、信号
受信回路が2系統必要であり、また精度良く干渉波を抑
圧するためには両信号受信回路の位相および振幅の変動
特性を合わせる必要があり、そのために構成部品が多く
その振幅位相特性変動の調整などが難しい欠点があっ
た。
However, such a conventional interference compensator requires two signal receiving circuits, and it is necessary to match the phase and amplitude fluctuation characteristics of both signal receiving circuits in order to suppress interference waves with high accuracy. For this reason, there is a drawback that there are many components and it is difficult to adjust the fluctuation of the amplitude / phase characteristics.

本発明は上記の欠点を解決するもので、信号受信回路
が2系統必要なく、かつ構成が簡易で調整の容易な干渉
補償装置を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide an interference compensator which does not require two signal receiving circuits, has a simple configuration, and can be easily adjusted.

〔課題を解決するための手段〕[Means for solving the problem]

本発明は、希望受信波の他に干渉波が混入した第一の
入力信号を入力する第一の入力端子(1)と、上記干渉
波を主成分とする第二の入力信号を入力する第二の入力
端子(2)と、入力する制御電圧に基づき上記第二の入
力信号を制御して上記第一の入力信号の干渉波と振幅が
ほぼ同じで位相がほぼ反転した信号を出力する振幅位相
制御回路(3)と、この振幅位相制御回路の出力信号と
上記第一の入力信号とを合成して干渉波補償信号を出力
する第一の信号合成回路(4)とを備えた干渉補償装置
において、上記信号合成回路の出力信号を上記干渉波に
比して周波数の低い低周波信号により変調する第一の変
調器(12)および上記出力信号を90゜位相推移させた信
号をこの低周波信号を90゜位相推移させた信号により変
調する第二の変調器(13)と、この二つの変調器(12、
13)の変調出力を合成する第二の信号合成回路(16)
と、この第二の信号合成回路の出力を入力とし中間周波
信号に変換する信号受信回路(5)と、この中間周波信
号を包絡線検波する包絡線検波器(9)と、この包絡線
検波器の出力をそれぞれ入力とし上記低周波信号および
上記低周波信号の位相を90゜位相推移させた信号でそれ
ぞれ乗積検波して上記制御電圧として出力する二つの乗
積検波器(7、8)とを備えたことを特徴とする。
The present invention provides a first input terminal (1) for inputting a first input signal mixed with an interference wave in addition to a desired reception wave, and a second input terminal for inputting a second input signal mainly containing the interference wave. An input terminal for controlling the second input signal based on a control voltage to be input and outputting a signal whose amplitude is substantially the same as that of the interference wave of the first input signal and whose phase is substantially inverted; Interference compensation comprising a phase control circuit (3) and a first signal combining circuit (4) for combining an output signal of the amplitude / phase control circuit and the first input signal to output an interference wave compensation signal. In the apparatus, a first modulator (12) for modulating an output signal of the signal combining circuit with a low-frequency signal having a lower frequency than the interference wave, and a signal obtained by shifting the output signal by 90 ° in phase. A second modulator (1) that modulates the frequency signal with a signal shifted by 90 ° 3) and these two modulators (12,
13) Second signal synthesis circuit that synthesizes the modulation output of (16)
A signal receiving circuit (5) which receives an output of the second signal synthesizing circuit as an input and converts the signal into an intermediate frequency signal, an envelope detector (9) which detects the intermediate frequency signal by an envelope, and an envelope detector Two product detectors (7, 8), each of which receives the output of the detector as an input, performs product detection with the low-frequency signal and a signal obtained by shifting the phase of the low-frequency signal by 90 °, and outputs the resultant as the control voltage. And characterized in that:

また、本発明は、上記第一および第二の変調器(12、
13)は共に振幅変調器であることができる。
The present invention also provides the first and second modulators (12,
13) can both be amplitude modulators.

さらに、本発明は、上記信号受信回路(5)の入力に
上記第二の信号合成回路(16)の出力と上記第二の入力
信号とを合成する第三の信号合成回路(6)が設けられ
ることができる。
Further, in the present invention, a third signal synthesizing circuit (6) for synthesizing an output of the second signal synthesizing circuit (16) and the second input signal is provided at an input of the signal receiving circuit (5). Can be done.

また、本発明は、上記信号受信回路には自動利得制御
手段を含むことができる。
In the present invention, the signal receiving circuit may include an automatic gain control means.

さらに、本発明は、上記第二の入力信号が所定レベル
以下であるとき、上記振幅位相制御回路の出力を無効と
する手段を備えることができる。
Further, the present invention can include means for invalidating the output of the amplitude / phase control circuit when the second input signal is below a predetermined level.

〔作用〕[Action]

第一の変調器(12)は第一の信号合成回路(4)の出
力信号を干渉波に比して周波数の低い低周波信号により
変調し、上記第二の変調器(13)は上記出力信号を90゜
位相推移させた信号を上記低周波信号を90゜位相推移さ
せた信号により変調する。第二の信号合成回路(16)は
第一および第二の変調器の変調出力を合成する。その合
成出力には低周波信号で変調された干渉波が出力され
る。いま、スイッチ(20)が「オフ」の状態とする。信
号受信回路(5)は第二の合成回路の出力を入力し中間
周波信号に変換する。包絡線検波器(9)はこの中間周
波信号を包絡検波する。乗積検波器(7、8)は包絡線
検波器の検波出力の直流分をそれぞれカットして上記低
周波信号および上記低周波信号を90゜位相推移させた信
号でそれぞれ乗積検波し、低域濾波器でこの乗積検波出
力の直流成分を取出し制御電圧として振幅位相制御回路
に与える。
The first modulator (12) modulates the output signal of the first signal synthesizing circuit (4) with a low-frequency signal having a lower frequency than the interference wave, and the second modulator (13) modulates the output signal. The signal obtained by shifting the signal by 90 ° is modulated by the signal obtained by shifting the low frequency signal by 90 °. A second signal combining circuit (16) combines the modulated outputs of the first and second modulators. An interference wave modulated by a low-frequency signal is output to the combined output. Now, it is assumed that the switch (20) is in the "OFF" state. The signal receiving circuit (5) receives the output of the second combining circuit and converts it into an intermediate frequency signal. An envelope detector (9) performs envelope detection on the intermediate frequency signal. The multiplying detectors (7, 8) cut the DC component of the detection output of the envelope detector and perform multiplying detection with the low-frequency signal and a signal obtained by shifting the low-frequency signal by 90 °, respectively. The bandpass filter extracts the DC component of the product detection output and supplies it to the amplitude and phase control circuit as a control voltage.

また、スイッチ(20)が「オン」の場合を考えると第
三の信号合成回路(6)で第二の信号合成回路(16)の
出力と第二の入力信号とを合成して信号受信回路に与え
る。信号受信回路に自動利得制御手段を設けて第二の入
力信号のレベル変動に対して安定な補償動作が得られる
ようにすることができる。
Considering the case where the switch (20) is "ON", the third signal synthesizing circuit (6) synthesizes the output of the second signal synthesizing circuit (16) and the second input signal, and the signal receiving circuit Give to. An automatic gain control means can be provided in the signal receiving circuit so that a stable compensation operation can be obtained for the level fluctuation of the second input signal.

さらに、第二の入力信号が所定レベル以下であるとき
は、干渉波がなくなっているものとして振幅位相制御回
路の出力信号を無効とする。
Further, when the second input signal is lower than the predetermined level, the output signal of the amplitude / phase control circuit is invalidated assuming that the interference wave has disappeared.

以上により信号受信回路が2系統必要なくなり、かつ
構成が簡易で調整が容易にできる。
As described above, two signal receiving circuits are not required, and the configuration is simple and adjustment can be easily performed.

〔実施例〕〔Example〕

本発明の実施例について図面を参照して説明する。第
1図は本発明一実施例干渉補償装置のブロック構成図で
ある。第3図は本発明の干渉補償装置の振幅位相制御回
路のブロック構成図である。第1図において、干渉補償
装置は、希望受信波の他に干渉波が混入した第一の入力
信号を入力する第一の入力端子として入力端子1と、上
記干渉波を主成分とする第二の入力信号を入力する第二
の入力端子として入力端子2と、入力する制御電圧に基
づき上記第二の入力信号を制御して上記第一の入力信号
の干渉波と振幅がほぼ同じで位相がほぼ反転した信号を
出力する振幅位相制御回路3と、振幅位相制御回路3の
出力信号と上記第一の入力信号とを合成して干渉波補償
信号を出力する第一の信号合成回路として信号合成回路
4と、この干渉波補償信号を出力する干渉波補償出力端
子10とを備える。
Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an interference compensation apparatus according to an embodiment of the present invention. FIG. 3 is a block diagram of the amplitude / phase control circuit of the interference compensation device of the present invention. In FIG. 1, an interference compensator includes an input terminal 1 as a first input terminal for inputting a first input signal mixed with an interference wave in addition to a desired reception wave, and a second input terminal mainly including the interference wave. And an input terminal 2 as a second input terminal for inputting an input signal of the input signal, and controlling the second input signal based on a control voltage to be input so that the amplitude and the phase of the interference wave of the first input signal are substantially the same as those of the first input signal. An amplitude / phase control circuit 3 that outputs a substantially inverted signal, and a signal synthesis circuit that synthesizes an output signal of the amplitude / phase control circuit 3 and the first input signal to output an interference wave compensation signal. The circuit includes a circuit 4 and an interference wave compensation output terminal 10 for outputting the interference wave compensation signal.

ここで本発明の特徴とするところは、信号合成回路4
の出力信号を上記干渉波に比して周波数の低い低周波信
号により変調する第一の変調器および上記出力信号を90
゜位相推移させた信号をこの低周波信号を90゜位相推移
させた信号により変調する第二の変調器として変調器1
2、13、90゜移相器11、15および低周波信号発振器14
と、変調器12、13の変調出力を合成する第二の信号合成
回路として信号合成回路16と、信号合成回路16の出力を
入力とし中間周波信号に変換する信号受信回路5と、こ
の中間周波信号を包絡線検波する包絡線検波器9と、包
絡線検波器9の出力をそれぞれ高域濾波器21、22を介し
て入力し上記低周波信号および上記低周波信号の位相を
90゜位相推移させた信号でそれぞれ乗積検波し低域濾波
器23、24および直流積分回路25、26を介して上記制御電
圧として出力する二つの乗積検波器7、8とを備えたこ
とにある。また、変調器12、13はここでは共に振幅変調
器である。
The feature of the present invention is that the signal synthesizing circuit 4
A first modulator that modulates the output signal of the first signal with a low-frequency signal having a frequency lower than that of the interference wave, and
Modulator 1 as a second modulator that modulates the phase-shifted signal with this low-frequency signal shifted by 90 °
2, 13, 90 ° phase shifters 11, 15 and low-frequency signal oscillator 14
A signal synthesizing circuit 16 as a second signal synthesizing circuit for synthesizing the modulation outputs of the modulators 12 and 13; a signal receiving circuit 5 which receives the output of the signal synthesizing circuit 16 as an input and converts it into an intermediate frequency signal; An envelope detector 9 for envelope detection of a signal and an output of the envelope detector 9 are input through high-pass filters 21 and 22, respectively, and the phases of the low-frequency signal and the low-frequency signal are detected.
It is provided with two product detectors 7 and 8 that respectively perform product detection on the signals whose phases have been shifted by 90 ° and output the control voltages through low-pass filters 23 and 24 and DC integration circuits 25 and 26. It is in. The modulators 12 and 13 are both amplitude modulators here.

さらに、信号受信回路5の入力に信号合成回路16の出
力と上記第二の入力信号とを合成する第三の信号合成回
路として信号合成回路6が設けられる。
Further, a signal synthesizing circuit 6 is provided as an input of the signal receiving circuit 5 as a third signal synthesizing circuit for synthesizing the output of the signal synthesizing circuit 16 and the second input signal.

また、信号受信回路5には自動利得制御手段を含む。 The signal receiving circuit 5 includes an automatic gain control unit.

さらに、上記第二の入力信号が所定レベル以下である
とき、振幅位相制御回路3の出力を無効とする手段とし
て包絡線検波器9の出力に接続されたスイッチ18を備え
る。
Further, a switch 18 connected to the output of the envelope detector 9 is provided as means for invalidating the output of the amplitude / phase control circuit 3 when the second input signal is below a predetermined level.

第3図は干渉補償装置の振幅位相制御回路のブロック
構成図である。第3図において、31は入力端子、32は信
号分岐回路、33a〜33dは固定移相器、34a〜34dはPINダ
イオード減衰器、35は信号合成器、36a、36bは制御信号
入力端子および37は出力端子である。第3図の構成およ
び動作については特公昭62−16580号公報に詳細な説明
がある。
FIG. 3 is a block diagram of the amplitude / phase control circuit of the interference compensator. In FIG. 3, 31 is an input terminal, 32 is a signal branch circuit, 33a to 33d are fixed phase shifters, 34a to 34d are PIN diode attenuators, 35 is a signal synthesizer, 36a and 36b are control signal input terminals and 37. Is an output terminal. The configuration and operation of FIG. 3 are described in detail in Japanese Patent Publication No. 62-16580.

このような構成の干渉補償装置の動作について説明す
る。第1図において、入力端子2に入力した干渉波は、
2分岐されて振幅位相制御回路3および信号受信回路5
に入力される。この2分岐された信号は複素表示により
次のように表せる。
The operation of the interference compensation device having such a configuration will be described. In FIG. 1, the interference wave input to the input terminal 2 is
Amplitude / Phase control circuit 3 and signal receiving circuit 5
Is input to The two-branched signal can be expressed as follows in a complex representation.

IA=iA ejΩt iA :入力端子2に入力する干渉波する振幅 Ω :干渉波角周波数 振幅位相制御回路3では制御電圧v1、v2に対して、出
力信号を次のように制御し出力する。
I A = i A e jΩt i A: amplitude interfering wave to the input terminal 2 Omega: against the interference wave angular frequency amplitude-phase control circuit 3 controls the voltage v 1, v 2, the output signal as follows Control and output.

IV=−KV(v1+jv2)IA =−KV ViA ej(Ωt+φ) −KV:振幅位相制御回路の制御感度 Vejφ=v1+jv2 この振幅位相制御回路3の出力信号は、信号合成回路
4で入力端子1からの信号と合成される。このときに入
力端子1からの干渉波信号は次式で表され、 IM=iM ej(Ωt+α) iM :入力端子1に入力する干渉波の振幅 α :入力端子1に入力する干渉波と入力端子2に入力
する干渉波との位相差 合成信号は次式となる。
I V = -K V (v 1 + jv 2) I A = -K V Vi A e j (Ωt + φ) -K V: the control sensitivity Ve jφ = v 1 + jv 2 amplitude phase control circuit 3 of the amplitude phase control circuit The output signal is combined with the signal from the input terminal 1 by the signal combining circuit 4. Interference signal from the input terminal 1 at this time is represented by the following formula, I M = i M e j (Ωt + α) i M: amplitude of the interference wave to the input terminal 1 alpha: interference applied to the input terminal 1 The phase difference between the wave and the interference wave input to the input terminal 2 is as follows.

IR=iM ej(Ωt+α)−KV ViA ej(Ωt+φ) =rej(Ωt+θ) ただし、rejθ=iM ejα−KV ViA ejφこの合成信
号を2系統に分岐し、この2分岐された一方の信号の位
相を90゜位相推移させると各信号は次のように表わせ
る。
Branch I R = i M e j ( Ωt + α) -K V Vi A e j (Ωt + φ) = re j (Ωt + θ) However, the re jθ = i M e jα -K V Vi A e jφ this combined signal into two systems When the phase of one of the two branched signals is shifted by 90 °, each signal can be expressed as follows.

この各信号に、位相の90゜異なる低周波信号発振器14
の出力信号およびこの出力信号を90゜位相器15により位
相推移した信号でそれぞれ変調器12、13で「オン」−
「オフ」の振幅変調を行うと次式のように表わせる。
Each of these signals has a low-frequency signal oscillator 14 with a phase difference of 90 °.
The output signal of the phase shifter 15 and the signal whose phase has been shifted by the 90 ° phase shifter 15 are “on” by the modulators 12 and 13, respectively.
When the amplitude modulation of “OFF” is performed, it can be expressed by the following equation.

ω:変調信号角周波数 この振幅変調された二つの信号を信号合成回路16で合
成し、さらにこの合成された信号と入力端子2の入力信
号とを信号合成回路6で合成すると次式となる。
ω: Modulated signal angular frequency The two signals subjected to the amplitude modulation are combined by the signal combining circuit 16 and the combined signal and the input signal of the input terminal 2 are combined by the signal combining circuit 6 to obtain the following equation.

この合成信号を包絡線検波器9で、たとえば自乗検波
すると次式を得る。
When this composite signal is subjected to, for example, square detection by the envelope detector 9, the following equation is obtained.

このS2の直流分を低域濾波器で取出し、この直流分出
力が一定となるように自動利得制御(AGC)をかける。
すなわち低域濾波器で取出した直流電圧は、 iA 2/2 ただしiA≫r これに基づきAGCによる増幅利得を ただし、K=一定 とすると、S2は次式となる。
Taken out DC component of the S 2 in the low-pass filter, multiplying the automatic gain control (AGC) as the DC component output becomes constant.
Ie dc voltage taken out by the low-pass filter is, i A 2/2 However i A >> R amplification gain by the AGC based on this However, if K = constant, S 2 is given by the following equation.

本式の直流成分をコンデンサなどの高域濾波器21、22
によりカットし、変調信号、すなわち低周波信号発振器
14の出力信号およびこの出力信号を90゜移相器15で位相
推移した信号で乗積検波器7、8において乗積検波し、
この検波出力の直流成分を低域濾波器23、24および直流
積分回路25、26により得る。すなわち乗積検波器7、8
の出力する制御電圧E1、E2はそれぞれ次式となる。
This type of DC component is filtered by high-pass filters 21, 22 such as capacitors.
Cut by the modulated signal, ie the low frequency signal oscillator
The output signal of 14 and the signal whose phase has been shifted by the 90 ° phase shifter 15 are subjected to product detection in the product detectors 7 and 8,
The DC component of the detection output is obtained by low-pass filters 23 and 24 and DC integration circuits 25 and 26. That is, the product detectors 7, 8
Control voltages E 1 and E 2 output by the following equation.

E1=(K2 r/π2 iA)cosθ E2=(K2 r/π2 iA)sinθ ただし、iA≫r この二つの出力信号E1、E2を適切な利得Gで増幅し、
上述の制御電圧v1、v2に加算して制御すると、信号合成
回路4の出力信号は次式となり、 IR=iM ej(Ωt+α)−KV ViA ej(Ωt+φ) −KV(K2 G/π)rej(Ωt+θ) ={1−(kr K2 G/π)}rej(Ωt+θ) 制御ループ利得KV K2 G/πを適切に設定すればIR
「0」となり、最終的に干渉波が抑圧され、干渉波補償
出力端子10から希望波のみの信号が得られる。
E 1 = (K 2 r / π 2 i A ) cos θ E 2 = (K 2 r / π 2 i A ) sin θ where i A ≫r These two output signals E 1 and E 2 are divided by an appropriate gain G. Amplify,
When the control is added to the control voltage v 1, v 2 described above, the output signal of the signal combining circuit 4 is given by the following formula, I R = i M e j (Ωt + α) -K V Vi A e j (Ωt + φ) -K V (K 2 G / π 2 ) re j (Ωt + θ) = {1- (k r K 2 G / π 2)} re j (Ωt + θ) control loop gain K V K 2 G / π 2 appropriately setting them For example, I R becomes “0”, the interference wave is finally suppressed, and a signal of only the desired wave is obtained from the interference wave compensation output terminal 10.

また、「0」−「π」の位相変調を行うとすると、変
調信号は、 および となり、同様の過程をもって干渉波補償が可能である。
「オン」−「オフ」または「0」−「π」変調のように
高周波を含む変調波ではなく正弦波による変調によって
も干渉波補償が可能である。
If the phase modulation of “0” − “π” is performed, the modulation signal is and Thus, interference wave compensation can be performed in a similar process.
Interference wave compensation can be performed not by a modulation wave including a high frequency but by a sine wave modulation such as “on”-“off” or “0”-“π” modulation.

また、上述の説明では、包絡線検波器9で自乗検波の
場合について説明したが包絡線を得る方法として、位相
同期回路などにより、入力端子2に入力した干渉波に同
期した信号AsinΩt(A:定数)を得て、これで検波して
も同様の結果が得られる。すなわち、AsinΩtでSを検
波すると、 ただし、高周波成分、すなわち2Ωの周波数成分を含む
項は省略している。この直流分 (ただし、iA≫r)でAGCをかけると、 この直流分を除き、変調信号、すなわち低周波信号発振
器14の出力信号およびこの出力信号を90゜移相器15で位
相推移した信号で乗積検波器7、8において乗積検波
し、その直流分を得る。
In the above description, the case of the square detection by the envelope detector 9 has been described. However, as a method for obtaining the envelope, a signal AsinΩt (A: At) synchronized with the interference wave input to the input terminal 2 by a phase synchronization circuit or the like. Constant), and the same result can be obtained by detection with this. That is, if S is detected by AsinΩt, However, a term including a high-frequency component, that is, a frequency component of 2Ω is omitted. This DC component (However, if I apply AGC with i A ≫r) Excluding this DC component, the product signals are subjected to product detection in the product detectors 7 and 8 using the modulated signal, that is, the output signal of the low-frequency signal oscillator 14 and the signal whose phase has been shifted by the 90 ° phase shifter 15. Get a minute.

E1=(Kr2 iA)(1+1/9+1/25 +1/49+…‥)sinθ ≒0.125(Kr/iA)sinθ E2=(Kr/π2 iA)(1+1/9+1/25 +1/49+…‥)cosθ ≒0.125(Kr/iA)cosθ このように上述の説明と同様に(r/iA)cosθおよび
(r/iA)sinθに比例した電圧が得られ、干渉波を抑圧
できる。
E 1 = (K r / π 2 i A) (1 + 1/9 + 1/25 + 1/49 + ... ‥) sinθ ≒ 0.125 (Kr / i A) sinθ E 2 = (Kr / π 2 i A) (1 + 1/9 + 1 / 25 + 1/49 +...)) Cos θ K0.125 (Kr / i A ) cos θ As described above, a voltage proportional to (r / i A ) cos θ and (r / i A ) sin θ is obtained, and interference occurs. Can suppress waves.

また、AGCは、高周波数帯、中間周波数帯で行う場合
について説明したが、低周波帯または直流信号において
も可能である。たとえば、高周波数帯、中間周波数帯で
AGCをかけてない場合の直流電圧E1は自乗検波のとき次
式となる。
Although AGC is performed in a high frequency band and an intermediate frequency band, it is also possible to use AGC in a low frequency band or a DC signal. For example, in the high frequency band, the intermediate frequency band
DC voltage E 1 when not wearing the AGC becomes the following equation when the square-law detection.

E1=(iA r/2π)cosθ これを自乗検波出力の直流分iA 2/2に基づき2K/i
A 2(Kは一定)の利得で増幅する。この結果、直流電圧
E1は次のようになり、同様の結果が得られる。
E 1 = (i A r / 2π 2) cosθ which based on the DC component i A 2/2 of the square-law detection output 2K / i
Amplify with a gain of A 2 (K is constant). As a result, the DC voltage
E 1 is as follows, with similar results.

E1=(Kr/π2 iA)cosθ 以上の説明はAGCを行う場合についてであるが、AGCを
行わなくても干渉波の補償は可能である。しかし、入力
干渉波のレベル変動に対してループ利得が変動するため
補償動作が不安定となる。このためにAGCをかけたほう
が安定な補償動作が得られる。
E 1 = (Kr / π 2 i A ) cos θ The above description is for the case where AGC is performed, but the interference wave can be compensated without performing AGC. However, the compensation operation becomes unstable because the loop gain fluctuates with respect to the level fluctuation of the input interference wave. Therefore, a stable compensation operation can be obtained by applying AGC.

また、干渉となる信号の送信が停止されるなどの場合
には干渉補償装置は熱雑音などに対して動作するため希
望波に有害な影響を与える可能性がある。このために、
干渉波が存在するときだけ干渉補償を行うようにしたほ
うがよい。すなわち、入力端子2の入力信号の干渉波レ
ベルを検出し、干渉波が検出されないときには入力端子
1の入力信号に入力端子2の入力信号が合成されないよ
うにする必要がある。具体的にはAGCの制御電圧を監視
し、雑音レベル以上の所定レベルに相当する電圧が検出
されたときに振幅位相制御回路3の出力信号に設けたス
イッチ18を「オン」にするように制御する方法などが考
えられる。
Further, when transmission of a signal causing interference is stopped or the like, the interference compensator operates against thermal noise or the like, which may have a harmful effect on a desired wave. For this,
It is better to perform interference compensation only when an interference wave exists. That is, it is necessary to detect the interference wave level of the input signal of the input terminal 2 and to prevent the input signal of the input terminal 2 from being combined with the input signal of the input terminal 1 when no interference wave is detected. Specifically, the control voltage of the AGC is monitored, and when a voltage corresponding to a predetermined level equal to or higher than the noise level is detected, the switch 18 provided in the output signal of the amplitude / phase control circuit 3 is controlled to be turned on. There are various ways to do this.

〔発明の効果〕〔The invention's effect〕

以上説明したように、本発明は、信号受信回路が2系
統必要なく、かつ構成が簡易で調整が容易な優れた効果
がある。
As described above, the present invention has an excellent effect that two signal receiving circuits are not required, the configuration is simple, and the adjustment is easy.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明一実施例干渉補償装置のブロック構成
図。 第2図は従来例の干渉補償装置のブロック構成図。 第3図は干渉補償装置の振幅位相制御回路のブロック構
成図。 1、2……入力端子、3……振幅位相制御回路、4、
6、16……信号合成回路、5、5A、5B……信号受信回
路、7、8……乗積検波器、9……包絡線検波器、10…
…干渉波補償出力端子、11、15、17……90゜移相器、1
2、13……変調器、14……低周波信号発振器、18、20…
…スイッチ、21、22……高域濾波器(HPF)、23、24…
…低域濾波器(LPF)、25、26……直流積分回路、31…
…入力端子、32……信号分岐回路、33a〜33d……固定移
相器、34a〜34d……PINダイオード減衰器、35……信号
合成器、36a、36b……制御信号入力端子、37……出力端
子。
FIG. 1 is a block diagram of an interference compensation apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram of a conventional interference compensator. FIG. 3 is a block diagram of an amplitude / phase control circuit of the interference compensator. 1, 2, ... input terminals, 3 ... amplitude and phase control circuit, 4,
6, 16 ... signal synthesis circuit, 5, 5A, 5B ... signal reception circuit, 7, 8 ... product detector, 9 ... envelope detector, 10 ...
… Interference wave compensation output terminal, 11, 15, 17 …… 90 ° phase shifter, 1
2, 13… Modulator, 14… Low-frequency signal oscillator, 18, 20…
… Switch, 21, 22 …… High-pass filter (HPF), 23, 24…
… Low-pass filter (LPF), 25, 26 …… DC integration circuit, 31…
... Input terminals, 32 ... Signal branch circuits, 33a-33d ... Fixed phase shifters, 34a-34d ... PIN diode attenuators, 35 ... Signal combiners, 36a, 36b ... Control signal input terminals, 37 ... ... Output terminal.

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】希望受信波の他に干渉波が混入した第一の
入力信号を入力する第一の入力端子(1)と、上記干渉
波を主成分とする第二の入力信号を入力する第二の入力
端子(2)と、入力する制御電圧に基づき上記第二の入
力信号を制御して上記第一の入力信号の干渉波と振幅が
ほぼ同じで位相がほぼ反転した信号を出力する振幅位相
制御回路(3)と、この振幅位相制御回路の出力信号と
上記第一の入力信号とを合成して干渉波補償信号を出力
する第一の信号合成回路(4)とを備えた 干渉補償装置において、 上記信号合成回路の出力信号を上記干渉波に比して周波
数の低い低周波信号により変調する第一の変調器(12)
および上記出力信号を90゜位相推移させた信号をこの低
周波信号を90゜位相推移させた信号により変調する第二
の変調器(13)と、この二つの変調器(12、13)の変調
出力を合成する第二の信号合成回路(16)と、この第二
の信号合成回路の出力を入力とし中間周波信号に変換す
る信号受信回路(5)と、この中間周波信号を包絡線検
波する包絡線検波器(9)と、この包絡線検波器の出力
をそれぞれ入力とし上記低周波信号および上記低周波信
号の位相を90゜位相推移させた信号でそれぞれ乗積検波
して上記制御電圧として出力する二つの乗積検波器
(7、8)とを備えた ことを特徴とする干渉補償装置。
1. A first input terminal (1) for inputting a first input signal mixed with an interference wave in addition to a desired reception wave, and a second input signal mainly containing the interference wave. A second input terminal for controlling the second input signal based on an input control voltage and outputting a signal having substantially the same amplitude as the interference wave of the first input signal and having a substantially inverted phase; Interference comprising: an amplitude / phase control circuit (3); and a first signal synthesis circuit (4) that synthesizes an output signal of the amplitude / phase control circuit and the first input signal and outputs an interference wave compensation signal. In the compensator, a first modulator for modulating an output signal of the signal combining circuit with a low-frequency signal having a lower frequency than the interference wave (12)
And a second modulator (13) for modulating a signal obtained by shifting the output signal by 90 ° with a signal obtained by shifting the low-frequency signal by 90 °, and a modulation of the two modulators (12, 13). A second signal synthesizing circuit (16) for synthesizing an output, a signal receiving circuit (5) for receiving an output of the second signal synthesizing circuit as an input and converting the intermediate frequency signal into an intermediate frequency signal, and performing envelope detection on the intermediate frequency signal An envelope detector (9), and the outputs of the envelope detector are respectively input and the low frequency signal and a signal obtained by shifting the phase of the low frequency signal by 90 ° are respectively multiplied and detected to obtain the control voltage. An interference compensator comprising: two output product detectors (7, 8) for outputting.
【請求項2】上記第一および第二の変調器(12、13)は
共に振幅変調器である請求項1記載の干渉補償装置。
2. An interference compensator according to claim 1, wherein said first and second modulators (12, 13) are both amplitude modulators.
【請求項3】上記信号受信回路(5)の入力に上記第二
の信号合成回路(16)の出力と上記第二の入力信号とを
合成する第三の信号合成回路(6)が設けられた請求項
1記載の干渉補償装置。
3. A third signal synthesizing circuit (6) for synthesizing an output of the second signal synthesizing circuit (16) and the second input signal at an input of the signal receiving circuit (5). The interference compensator according to claim 1.
【請求項4】上記信号受信回路には自動利得制御手段を
含む請求項3記載の干渉補償装置。
4. An interference compensator according to claim 3, wherein said signal receiving circuit includes an automatic gain control means.
【請求項5】上記第二の入力信号が所定レベル以下であ
るとき、上記振幅位相制御回路の出力を無効とする手段
を備えた請求項3記載の干渉補償装置。
5. An interference compensator according to claim 3, further comprising means for invalidating the output of said amplitude / phase control circuit when said second input signal is lower than a predetermined level.
JP20658790A 1990-08-03 1990-08-03 Interference compensator Expired - Fee Related JP2951703B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20658790A JP2951703B2 (en) 1990-08-03 1990-08-03 Interference compensator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20658790A JP2951703B2 (en) 1990-08-03 1990-08-03 Interference compensator

Publications (2)

Publication Number Publication Date
JPH0490625A JPH0490625A (en) 1992-03-24
JP2951703B2 true JP2951703B2 (en) 1999-09-20

Family

ID=16525874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20658790A Expired - Fee Related JP2951703B2 (en) 1990-08-03 1990-08-03 Interference compensator

Country Status (1)

Country Link
JP (1) JP2951703B2 (en)

Also Published As

Publication number Publication date
JPH0490625A (en) 1992-03-24

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