JP2943772B2 - Branch prediction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction processing method for an information processing apparatus, and more particularly to a branch instruction processing method for reducing pipeline disturbance due to branching in a pipeline processor.

[0002]

2. Description of the Related Art A pipeline-type processor for performing branch prediction can be divided into a static branch prediction method and a dynamic branch prediction method.

In the static branch prediction method, a branch direction is determined at the time of compiling a program.
At the time of execution of the branch instruction, the direction of the prediction does not change. Although the validity of branch prediction is not very high, hardware cost is not required because of the software method.

On the other hand, in the dynamic branch prediction system, branch prediction is performed based on the execution history up to the present. That is, the direction of prediction is changed as needed based on the behavior of the branch instruction in the program up to the present. A conventional method for implementing dynamic branch prediction uses a branch destination buffer. The operation of the branch destination buffer will be described below with reference to FIG.

As shown in FIG. 12, the branch destination buffer includes a register for storing a branch instruction address, a register for storing a predicted next address, and a register group consisting of one or more bits for storing predicted data. N
Consider a configuration with only

A program counter (hereinafter referred to as "PC") which is currently fetching an instruction and a branch instruction address currently entered in a branch destination buffer are searched. If there is a match, the instruction currently being fetched is a branch instruction, and the PC for instruction fetch is updated immediately with the corresponding predicted next address as the next PC, and instruction fetch is started.

Thereafter, if the branch result does not match the prediction, the predicted next address is updated and the fetch is performed again. If it matches the prediction, execution is continued as a prediction hit.

On the other hand, if there is no match in the branch destination buffer, it is determined that the instruction currently being fetched is not a branch instruction, the PC is updated as usual, and the next instruction fetch is performed on this PC.

Thereafter, if the instruction is recognized as a branch instruction in the instruction decoding stage of the pipeline, the instruction is entered into the branch destination buffer together with the next PC.

Each of the branch instructions entered in the branch destination buffer has prediction data, and records whether the branch is predicted to be taken or not taken.

Based on the prediction data and the current branch status, the prediction data can be updated based on a predetermined branch prediction algorithm, and can be used to determine whether or not the predicted next address should be updated immediately when a prediction error occurs. As a branch prediction algorithm, a one-bit prediction method, a two-bit prediction method, and the like are known, and a prediction is performed based on a history of several previous branches.

In order to realize a branch prediction that requires a high hit ratio, dynamic branch prediction using a branch destination buffer or the like is effective. However, there is a disadvantage in terms of hardware cost that a large buffer must be provided. When a branch destination buffer is used, there is an upper limit to the number of entries, and the processing becomes complicated to support a program having the number of branch instructions exceeding the number of entries in the buffer. Further, since the branch destination buffer is empty at the start of the program, branch prediction mistakes inevitably increase.

In order to solve the above problem, there has been proposed a method of providing a prediction information field in an instruction field of a branch instruction. There is also known a method of determining whether or not to register in the branch destination buffer by looking at the prediction information field, preparing a minimum buffer, and reducing hardware cost. There is also known a method of determining a content of a prediction operation, a register to be used, and the like by examining a prediction information field, and performing branch prediction.

[0014]

In a conventional branch prediction system in which a prediction information field is provided in an instruction field of a branch instruction, it is assumed that a branch destination buffer is used, and a method of effectively using the branch destination buffer is as follows. I have been. Further, in order to improve the validity of the dynamic branch prediction, a large branch destination buffer is used.

Conventionally, there has been proposed a method for suppressing an increase in the number of entries in a branch destination buffer by a method such as selecting a branch instruction to make an entry in order to reduce hardware costs.

However, the branch destination buffer is indispensable for dynamic branch prediction, and this partial hardware is required at a minimum. The search processing of the branch destination buffer also complicates the circuit and lowers the processing capability of the processor.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object to provide a branch instruction processing method which does not use a branch destination buffer and suppresses an excessive increase in hardware cost. Is to do.

[0018]

Means for Solving the Problems] To achieve the above object, a branch instruction processing system of the present invention, have a branch instruction with at any time rewritable prediction data fields in the instruction field of the branch instruction, the prediction data field Is a branch
A field for storing measurement information, and a field for updating the prediction information.
Stores prediction information update permission information that controls prohibition / permission
And a field .

The present invention includes means for providing dynamic prediction information such as a past branch history in a prediction data field and changing it at any time when each branch instruction is executed. In the present invention
Preferably, the prediction data field is
Dynamic prediction for branch prediction using history of several branches
Field for storing information and updating of the dynamic prediction information
The dynamic prediction information update permission information that controls the prohibition / permission of
And a field to store.

The present invention, when using a dynamic prediction information such as past branch history in the prediction data field, is what determines the initial value in a static branch prediction.

The present invention uses static branch prediction information in the prediction data field, and does not update the prediction information in the initial stage of program processing or in the entire program processing.

According to the present invention, when dynamic prediction information such as a past branch history is stored in the prediction data field, updating of the prediction information at any time during program processing can be prohibited.

According to the present invention, the prediction data field is provided with selection information so that a method for providing the prediction data field with information such as dynamic prediction information and static branch prediction can be selected at any time during program processing. .

The present invention has a function of reflecting the result in the prediction data field of the branch instruction when the program has a branch prediction process or when it is desired to directly rewrite the information in the prediction data field of the branch instruction at a certain point in time. I do.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. In a preferred embodiment of the present invention, the instruction field of the branch instruction has a rewritable prediction data field at any time, in which dynamic prediction information such as past branch history, static branch prediction information, prediction method selection, It includes information (prediction information update permission bit) that can prohibit updating of prediction information (see FIGS. 2 to 5).

Since the instruction field of the branch instruction has a predictable data field which can be rewritten at any time, in the conventional method, the branch instruction determined at the time of compilation can change the content of the instruction during program execution. ,
Flexible branch prediction processing can be performed, so that the validity rate of branch prediction can be improved.

In a preferred embodiment of the present invention, the prediction data field is provided with dynamic prediction information such as a past branch history (see FIGS. 6 (b) and 6 (c)).
Based on the prediction information, a branch destination is determined, and dynamic prediction information such as a branch history is updated during branch instruction processing,
It has a function of writing back to the memory where the branch instruction is stored.

In the present invention, dynamic prediction information such as a past branch history is stored in a branch instruction. For this reason,
Large hardware such as a branch destination buffer is not required, which is advantageous in cost.

Further, since the prediction information corresponding to each branch instruction is included in each instruction, the prediction information obtained by searching the branch destination buffer in the conventional method is immediately obtained at the time of instruction fetch in the present invention. Therefore, the processing can be simplified, the speed of the branch prediction processing can be increased, and the performance of the processor can be improved.

Further, according to the preferred embodiment of the present invention, when dynamic prediction information such as a past branch history is provided in the prediction data field, the initial value of the prediction information is statically calculated at the time of compilation. It can be determined by dynamic branch prediction information.

[0031] In the branch instruction processing method of this, when using the dynamic prediction information such as past branch history, determined by the static branch prediction information performed the initial value of the prediction information at compile time, the program processing start The validity of dynamic branch prediction at the time can be improved.

In a preferred embodiment of the present invention, the prediction data field is provided with static branch prediction information performed at the time of compilation, and when it is not desired to update the prediction information, the prediction information update is performed. Has a function of updating the prediction information when the prediction information update is permitted during the program processing.

[0033] In the branch instruction processing method of this, it is effective when using a static branch prediction information performed at compile time. In addition, when the update of the prediction information is permitted during the program processing, the prediction information can be updated, so that the flexible branch prediction processing can be performed when the static branch information is not used at a certain time.

In a preferred embodiment of the present invention, when the prediction data field has dynamic prediction information such as a past branch history, the prediction information is updated at a certain point during program processing. When the user does not want to perform the update, the prediction information update is prohibited, and when the update of the prediction information is permitted, the prediction information is updated.

[0035] In the branch instruction processing method of this, when you have a dynamic prediction information such as past branch history, at some point during program processing, since it is prohibited and allow prediction information updating Thereafter, the flexible branch prediction Processing becomes possible.

In a preferred embodiment of the present invention, the type of prediction information, such as dynamic prediction information and information such as static branch prediction, and the prediction method are stored in the prediction data field at a certain point during program processing. The prediction data field is provided with selection information so that it can be selected at any time.

[0037] In the branch instruction processing system of this, dynamic prediction information, the type of prediction information such as static branch prediction, the prediction method, at some point during program processing, it is possible to select any time, flexible branch prediction process It becomes possible.

According to a preferred embodiment of the present invention, when a program has a branch prediction process and the result is desired to be reflected in a prediction data field of the branch instruction, the branch instruction is directly processed at some point during the program processing. Has the function of updating the prediction data field of the branch instruction when it is desired to rewrite the information of the prediction data field.

[0039] In the branch instruction processing method of this has a complex branch prediction algorithm in the program can be simplified complex branch prediction algorithm processing program for reflect the result to the prediction data field of the branch instruction, the branch The prediction process can be sped up. Further, the content of the branch instruction can be rewritten at any time during the program processing, and the speed of the branch prediction processing can be increased.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. The pipeline type processor used in the following description is a five-stage pipeline, and as shown in FIG. 1, the instruction fetch (IF), instruction decode (ID), operation execution (EX), memory Access (M
EM) and register write (WB) processing stages.

As shown in FIG. 2, the branch instruction field includes an instruction code, an immediate value indicating a relative branch destination, and a rewritable prediction data field. FIG.
, A register code may be provided, and the contents of the corresponding register may be set as a relative branch destination.

As shown in FIG. 4, the prediction data field includes dynamic prediction information, static prediction information, a dynamic prediction information update permission bit, a static prediction information update permission bit, and a prediction information selection bit. Each permission bit indicates update and prohibition of prediction information. In this case, the following functions are allowed.

It is assumed that the initial value of the dynamic prediction information update permission bit is set to the update permission state, and the initial value of the static prediction information update permission bit is set to the update inhibition state. First, dynamic prediction information and static prediction information can be selected. At a certain point in time during the program processing of the dynamic prediction information, update inhibition is set, and the prediction information at that point can be treated as if it were static prediction information. In this case, when dynamic prediction is performed again, update permission is set.

When it is desired to update the static prediction information determined at the time of compilation at a certain point during the program processing, the static prediction information update permission bit is set to "update permitted".

Both columns of the prediction information in the prediction data field can be used for static prediction information or dynamic prediction information. At some point during the program processing, it is possible to change the dynamic or static method.

If the prediction data field cannot have a sufficient field width, the processing can be performed even with the configuration shown in FIG. Referring to FIG. 5, the prediction data field includes a prediction information update permission bit and prediction information. However,
If the process uses the static prediction information determined at compile time and switches to the process using dynamic prediction information, and if the static prediction information determined at compile time is used again, separate the static prediction information Must be stored.

The operation of the branch instruction processing system having a prediction data field as shown in FIG. 5 will be described with reference to FIGS. 6 and 7. Consider a case having an instruction field as shown in FIG. Each instruction has a branch instruction identification bit in the instruction code, and when the value of the branch instruction identification bit is 0, the instruction is not a branch instruction (FIG. 6).
(See FIG. 6A.) When 1, the instruction is assumed to be a branch instruction (see FIGS. 6B and 6C). Note that this information may be obtained by decoding the encoded instruction code at any time to compress the instruction code.

The instruction code of the branch instruction has a selection bit so that the immediate value in the instruction field (see FIG. 6C) and the contents of the register can be used as the relative branch destination address (see FIG. 6C). 6 (b)). If a sufficient instruction field cannot be obtained, the selected bit can be deleted by fixing the address to one of the relative branch destination addresses.

The branch instruction has a prediction data field. In the example shown in FIG. 6, it is assumed that the branch instruction has two bits as dynamic prediction information and performs prediction using two past histories. As the prediction algorithm, a known technique that has been conventionally proposed is used.

If it is predicted that the branch is taken, 2
When it is predicted that the upper bit of the prediction information of a bit is 1 and the branch is not taken, the past history state is assigned so that the upper bit of the prediction information becomes 0.

Further, the prediction data field has bits for permitting and prohibiting updating of prediction information. When this bit is 1, update of prediction information is permitted, and dynamic branch prediction becomes possible. On the other hand, when the value is 0, the update of the prediction information is prohibited, and the prediction information at the time of prohibition can be treated as static prediction information.

A branch instruction processing method having an instruction set as shown in FIG. 6 can be realized by a configuration as shown in FIG.
Of course, the example shown in FIG. 7 is a configuration for explanation,
Simplification, addition of functions, and the like are possible.

Referring to FIG. 7, increment 4 is
The current instruction fetch address is incremented to generate the next instruction fetch address when the branch is not taken.

The adder 3 adds the current instruction fetch address and the relative branch destination address to generate the next instruction fetch address when the branch is taken. The relative branch destination address input to the adder 3 selects the immediate value of the currently fetched instruction or the contents of the register by the multiplexer 2. As a selection signal for the multiplexer 2, a relative branch destination address selection bit is examined. The contents of the register serving as the relative branch destination address are selected from the register specified by the register code from the register file 1 and read out.

Assuming that the instruction currently being fetched is a branch instruction, the next instruction fetch address and the branch when the branch is not taken are passed through the multiplexers 5 and 6 by the prediction information upper bits indicating information for predicting whether the branch is taken or not taken. The next instruction fetch address at the time of establishment is sent to the predicted PC 7 and the non-predicted PC 8.

That is, when it is predicted that the branch is taken, the next instruction fetch address when the branch is taken is sent to the prediction PC 7, and when the branch is not taken, the next instruction fetch address is sent to the non-prediction PC 8. The next instruction fetch address when the branch is not taken is sent to the prediction PC 7 and the next instruction fetch address when the branch is taken is sent to the non-prediction PC 8.

Since the instruction currently being fetched is a branch instruction and is significant only when the instruction being fetched is the branch instruction, the AND condition element 18 which takes the logical product of the branch instruction identification bit and the prediction information upper bit causes the multiplexer 5, 6 are generated.

The prediction PC 7 always has the multiplexers 5 and 6
Latches the next instruction fetch address sent through the interface.

The non-prediction PC 8 latches only when the currently fetched instruction is a branch instruction. Therefore, the non-prediction PC 8 stores the next instruction fetch address for refetching when the prediction is missed. Usually, an address stored in the prediction PC 7 is selected by the multiplexer 9 as a next instruction fetch address. If there is a refetch request in the case of a prediction error, the refetch address stored in the non-prediction PC 8 is read.

The pre-PC 10, pre-PC 11 and update branch instruction address latch 12 serve as a delay element for holding an address for updating a branch instruction at the MEM stage of a branch instruction. These are usually provided in the processor for other purposes and need not be prepared here. Similarly, the pre-predicted data latch 14, the pre-predicted data latch 15, and the updated predicted data latch 1
Reference numeral 7 serves as a delay element for holding prediction data for updating a branch instruction. These are also usually provided with a register for storing the decoded value of the instruction in the processor, and may be added if necessary.

Prediction judgment and prediction data update circuit 16
Determines whether the prediction is valid based on the state information of the calculation result or the like. If it is determined that a prediction error has occurred, a refetch request is output. Further, the prediction information is updated, in this case, the branch history is updated. When the prediction information update permission bit is 0, no update is performed.

The memory 13 stores instructions, and outputs an instruction code when an instruction fetch address is input. Here, since a write-back process of the branch instruction is required, the medium must be a writable medium such as a RAM (random access memory). If writable, a data area may coexist or a configuration like an instruction cache may be used. Further, for simplification of the circuit, a configuration in which only the prediction data field portion can be written may be used.

The operation for each cycle of the configuration of the branch instruction processing system shown in FIG. 7 will be described with reference to FIGS. 8 to 11, it is assumed that the (n + 1) th instruction is a branch instruction.
The instruction at address n + 1 is stored at address 1, and the relative branch address of the branch instruction is b. That is, when the branch instruction is taken, the next instruction fetch address is 1 + b, and when the branch is not taken, the next instruction fetch address is 2. x is handled as an indefinite value which is a value set in the previous processing.

In FIGS. 8 to 11, the prediction P
C, the underlined part of the unpredicted PC indicates the operation of the multiplexer 9 selected as the instruction fetch address.
Whether the branch is taken or not can be determined when the n-th instruction has completed the EX stage. This is because the processor has a configuration in which the result of the operation is reflected in the branch. That is, the validity of the branch prediction is processed at the EX stage of the branch instruction at the earliest.

FIG. 8 shows a case where the branch is not taken and the prediction hits. Since the (n + 1) th instruction is a branch instruction, the branch instruction identification bit becomes 1, and the non-predicted PC
7 latches the next instruction fetch address that has passed through the multiplexer 5. In this case, since it is predicted that the branch is not taken, the non-prediction PC 7 latches the next instruction fetch address 1 + b when the branch is taken, while the prediction PC 8
Latches the next instruction fetch address 2 when the branch is not taken. Since the n-th instruction EX stage has been completed in the next cycle, the validity of the prediction is known. Here, since it is a prediction hit, the value of the non-prediction PC 7 is not used, and the processing is continued as it is.

FIG. 9 shows a case where the branch is not taken and the prediction is missed. Since the (n + 1) th instruction is a branch instruction, the branch instruction identification bit becomes 1, and the non-predicted PC 7
Latches the next instruction fetch address that has passed through the multiplexer 5. In this case, since it is predicted that the branch is not taken, the non-prediction PC 7 latches the instruction fetch address 1 + b when the branch is taken. On the other hand, the prediction PC 8 latches the next instruction fetch address 2 when the branch is not taken. The operation so far is the same as the operation shown in FIG. In the next cycle, it is determined that a prediction error has occurred, and a refetch request is issued. Here, as the next instruction fetch address, the next instruction fetch address 1 + b at the time of branch taken stored in the non-prediction PC 7 is selected by the multiplexer 9, and the refetch is completed. At the same time, invalidate the mispredicted instruction.

FIG. 10 shows a case where the branch is predicted to be taken and the prediction is hit. Since the (n + 1) th instruction is a branch instruction, the branch instruction identification bit becomes 1, and the non-predicted PC 7
Latches the next instruction fetch address that has passed through the multiplexer 5. In this case, since the branch is predicted to be taken, the next instruction fetch address 2 when the branch is not taken is latched. On the other hand, the prediction PC 8 latches the next instruction fetch address 1 + b when the branch is not taken. Since the EX stage of the n-th instruction is completed in the next cycle, the validity of the prediction is known. Here, since it is a prediction hit, the value of the non-prediction PC 7 is not used, and the processing is continued as it is.

FIG. 11 shows a case where the branch is predicted to be taken and the prediction is missed. Since the (n + 1) th instruction is a branch instruction, the branch instruction identification bit becomes 1, and the non-prediction PC 7 latches the next instruction fetch address passed through the multiplexer 5. In this case, since the branch is predicted to be taken, the next instruction fetch address 2 when the branch is taken is latched. On the other hand, the prediction PC 8 latches the next instruction fetch address 1 + b when the branch is not taken. So far,
This is the same as the operation shown in FIG. In the next cycle, it is determined that a prediction error has occurred, and a refetch request is issued. Here, the next instruction fetch address is determined by the
The next instruction fetch address 2 when the branch is not taken stored in C7 is selected, and the refetch is completed. At the same time, invalidate the mispredicted instruction.

Although common to FIG. 8 to FIG. 11, at the MEM stage of the branch instruction, the address 1 from which the updated branch instruction address was originally fetched appears, so that the branch instruction can be updated.

In this embodiment, when there is a continuous branch instruction, the value stored in the non-prediction PC 7 is updated. For this reason, when a continuous branch instruction is permitted, it can be solved by connecting the non-prediction PCs 7 in two stages in series. Although not shown in this embodiment, the circuit configuration when the branch instruction has static prediction information and dynamic prediction information and is used by switching with the selection bit is also provided with a multiplexer in a portion corresponding to the prediction information upper bits. This can be realized without adding excessive hardware such as inserting, setting the bit width of the latch of the prediction data to an appropriate value, and changing the prediction determination and prediction data update circuit.

Furthermore, since the prediction field in the branch instruction can be rewritten by a normal memory write instruction, it is particularly easy to change the prediction information update permission bit, prediction information permission bit, and the like. Of course, the change of the prediction information can also be executed by a normal memory write instruction.

[0072]

As described above, according to the present invention,
No special hardware such as a branch destination buffer is required,
Dynamic branch prediction becomes possible, and processing can be simplified. As a result, the hardware cost can be reduced, highly accurate and flexible branch prediction can be performed, and an improvement in the processing capability of the processor can be expected.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining one embodiment of the present invention;
FIG. 3 is an explanatory diagram showing each stage of the pipeline and a processing order.

FIG. 2 is a diagram for explaining one embodiment of the present invention;
FIG. 11 is a diagram illustrating an instruction field of a branch instruction having a relative branch destination address as an immediate value.

FIG. 3 is a diagram for explaining one embodiment of the present invention;
FIG. 11 is a diagram illustrating an instruction field of a branch instruction having a register code of a register having a relative branch destination address.

FIG. 4 is a diagram illustrating a prediction data field having static prediction information and dynamic prediction information in one embodiment of the present invention.

FIG. 5 is a diagram illustrating a prediction data field in which static prediction information and dynamic prediction information coexist in one embodiment of the present invention.

6A and 6B are diagrams showing the format of an instruction field of an instruction used in an embodiment of the present invention, wherein FIG. 6A is a non-branch instruction, FIG. 6B is a branch instruction (using a register), and FIG. Indicates the format of the instruction (using immediate values).

FIG. 7 is a block diagram illustrating an operation of a branch instruction processing system to which an embodiment of the present invention is applied;

FIG. 8 is a diagram for explaining one embodiment of the present invention;
It is a figure explaining operation | movement at the time of predicting that a branch is not taken and making a prediction hit.

FIG. 9 is a diagram for explaining one embodiment of the present invention;
It is a figure explaining operation | movement at the time of predicting that a branch is not taken and making a prediction mistake.

FIG. 10 is a diagram for explaining an embodiment of the present invention, and is a diagram for explaining an operation when a branch is predicted and a prediction hit occurs.

FIG. 11 is a diagram for explaining one embodiment of the present invention, and is a diagram for explaining an operation when a branch is predicted to be taken and a prediction error occurs.

FIG. 12 is a diagram illustrating the configuration and operation of a branch destination buffer.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 register file 2 multiplexer 3 adder 4 incrementer 5, 6 multiplexer 7 unpredicted PC 8 predicted PC 9 multiplexer 10 pre-PC 11 pre-PC 12 updated branch instruction address latch 13 memory 14 predicted data 15 pre-predicted data 16 prediction Judgment and prediction data update circuit 17 Update prediction data latch

Claims (5)

(57) [Claims] 1. A branch instruction processing system in a pipeline processor, the branch instruction is in the instruction field, has a predicted data fields rewritable any time, the prediction data field, the prediction information of the branch Store
Fields and the prohibition / permission of updating the forecast information.
A field for storing prediction information update permission information to be controlled,
Branch instruction processing method characterized by having a. 2. A branch instruction processing method in a pipeline type processor, wherein a branch instruction has, in its instruction field, a prediction data field which can be rewritten at any time , and the prediction data field is stored in a plurality of times in the past. Branch history
To store dynamic prediction information for branch prediction using
Field and the prohibition / permission of updating the dynamic prediction information.
Field for storing dynamic prediction information update permission information
And a branch instruction processing method. 3. A branch instruction processing method in a pipeline type processor, wherein a branch instruction has, in its instruction field, a prediction data field which can be rewritten at any time , and the prediction data field has a plurality of past prediction data fields. Branch history
To store dynamic prediction information for branch prediction using
Field and field for storing static branch prediction information
And a file storing prediction selection information for selecting a prediction method.
And the prohibition / permission of updating the dynamic prediction information
For storing dynamic prediction information update permission information
And static control for controlling prohibition / permission of updating the static prediction information.
And a field for storing dynamic prediction information update permission information.
The static prediction information and the dynamic prediction information are dynamically selected.
A branch instruction processing method characterized by being selectable . 4. The method according to claim 1, wherein said prediction selection information is
The dynamic prediction information updating permission information, before Symbol static prediction information update
Permission information, the dynamic prediction information, and the static prediction information
4. The branch instruction processing method according to claim 3 , wherein the branch instruction processing method is set variably . 5. A processor in a pipeline type processor.
Branch instruction processing method , branch instruction can be rewritten at any time in its instruction field
Prediction data field that stores branch prediction information.
Fields to be stored and prohibition / permission of updating the forecast information
For storing prediction information update permission information that controls
Includes a prediction data fields with and has a branch prediction process in the program, the branch prediction process <br/> result, provided with a function to reflect the predicted data field of said branch instruction, characterized Branch instruction processing method.