JP2901608B2 - Ring oscillation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] A CMOS-structured voltage-controlled oscillator (Voltage-controlled oscillator)
Oscillator, hereinafter referred to as VCO) circuit, especially PLL (Ph
The present invention relates to a ring oscillator type oscillation circuit suitable for use in an ase-locked-loop circuit.

[Summary of the Invention]

In a ring oscillator type VCO with a CMOS delay circuit inserted in the positive feedback loop, a circuit that is resistant to noise without large current flowing between the power supply and ground during frequency control. An input signal is supplied to a gate of a first FET of the delay circuit, a control signal is supplied to a gate of a second FET, and a common drain is connected to a reference potential (ground).
A capacitor is connected therebetween, and a delay circuit that obtains an output signal from a common drain through a buffer circuit is used.

[Conventional technology]

VCO circuits having a CMOS configuration are roughly classified into a multivibrator type and a ring oscillator type. FIG. 2 shows a conventional example of a multivibrator type, in which a) shows a circuit diagram, b) shows a state 1, and c) shows a state 2. In the circuit of FIG.
P ₁ and P ₂ are P-channel MOS FETs, N ₁ and N ₂ are N-channel
This shows a MOS type FET. At points A and B, the source side of each FET is connected. Besides, capacitor C ₁ , inverter 1,
2, a buffer amplifier 3, an AND circuit 4, NOR circuits 5, 6, etc. The NOR circuits 5 and 6 constitute a latch circuit 10.

Here, when the point C is at the H level, the point D takes the L level,
P ₁ is ON, N ₁ is the OFF state, P ₂ is the OFF state, N ₂ is turned ON, B point is connected to the oscillation control power. Therefore, C)
Is charged beginning of capacitor C ₁ in the state 2 illustrated in FIG., The voltage inverter 1 at the point B exceeds the level of the inverting amplifier, NOR5 is inverted, it becomes point C in L, b) showing a state 1 Move on to Oscillation is performed by repeating the operation in which the states 1 and 2 are interchanged in this manner.

Here, when the capacitor C ₁ enters disturbance such as noise before it is charged to a predetermined value, would be inverted latch circuit 10 stably exceed levels that for example, an inverter 1 is inverted amplifying, if the oscillation period is shortened There is.

Thus, the multivibrator type has a drawback that it is susceptible to noise.

FIG. 3 shows a conventional example of a ring oscillator type. It is constructed by connecting odd-numbered stages of CMOS inverters in cascade and applying positive feedback. Each inverter is, for example, a third
The inverter 301 is configured as shown by 301 surrounded by a dotted line.
The oscillation frequency is controlled by controlling the power supply voltage Vc.

Therefore, when controlling the oscillation frequency, there is a disadvantage that a large current flows between the power supply of each stage of the inverter and the ground (GND).

In practice, it is customary to provide a CR time constant for each stage of the ring oscillator type VCO inverter to enable long period oscillation with a small number of inverter stages.
212 as a prior art (FIG. 4). In that example, the time constant is used in combination with the capacitance of the capacitor, using the space between the source and drain of the enhancement type MOSFET as a pure resistance. The gate of the enhancement type MOSFET is connected to the power supply of the CMOS inverter, and the power supply voltage is controlled to control the oscillation frequency.
On the other hand, the gist of the invention disclosed in Japanese Patent Publication No. 59-15212 is to obtain an oscillator having a duty cycle of less than 50% by making the CR time constant different between charge and discharge. Therefore, the FET is replaced with a depletion-type FET, and means for connecting the gate to the source or drain is used (FIG. 5).

However, in the related art of the ring oscillator type VCO, in order to obtain a general oscillator including a duty cycle of 50%, the frequency variable means depends on the power supply voltage control of the inverter circuit. Not resolved.

[Problems to be solved by the invention]

In the present invention, a multivibrator type is provided with a means for solving both a disadvantage that it is susceptible to noise, and a ring oscillator type with a means for solving the disadvantage that a large current flows between a power supply and GND during frequency control, and a means for varying the oscillation frequency over a wide range. What you want to do.

[Means for solving the problem]

In a ring oscillator type VCO having a CMOS configuration, one or a plurality of delay circuits are cascaded and inserted into a positive feedback loop, and the delay circuit has the following configuration. That is, a gate of a first field-effect transistor (FET) constituting the CMOS of the delay circuit is used as an input terminal, a control signal is applied to a gate of a second FET, and a common connection between the first and second FETs is performed. A capacitor is connected between the drain and the reference potential (source of the first FET), and an output signal is obtained from the drain through a voltage amplification buffer circuit having a threshold. The voltage amplifying buffer circuit having the threshold value is formed, for example, by cascade-connecting two stages of inverters.

[Action]

Although the delay circuit of the present invention has a CMOS configuration, it operates in principle different from the conventional example.

That is, in the conventional example (Japanese Patent Publication No. 59-15212), CMOS
Are operated simply as an inverter circuit, and are configured by applying FETs that perform a pure resistance operation as R of the CR time constant. In the present invention, however, the two FETs of the CMOS FET that operates as a NAND circuit with each gate as an input terminal and receives a control signal for frequency variation
Also functions as a current control element.

As a result, even if the current flowing through the CMOS circuit is changed by the current control element, it is not necessary to change the voltage between the power supply and the reference potential (the source potential of the FET to which the input signal is input; for example, the ground). No large current flows between the power supply and the reference potential.

Further, the frequency is controlled using the charging time of the capacity, and the charging time is proportional to the capacity of the capacitor and inversely proportional to the magnitude of the current controlled by the current control element. This relationship is rarely disturbed by noise, and a voltage amplifying buffer circuit having a threshold is connected between the output terminal and the output terminal to stably obtain an output voltage of a predetermined level. Since the buffer circuit for voltage amplification does not have a multivibrator circuit such as a latch, it does not unexpectedly reverse.
Therefore, it is strong against noise. Further, since the voltage amplifying buffer circuit having the threshold value is provided in the delay circuit, the delay amount can be set large, and the variable range of the oscillation frequency can be widened.

〔Example〕

FIG. 1 shows an embodiment, in which a) is a circuit diagram of the embodiment, b) is a detail of the delay circuit 100 , c) is a time chart of details of the delay circuit, and d) is a time chart of the delay circuit 13 .

In the embodiment shown in FIG. 1A), the delay circuit 100 includes N stages (N is a positive integer; the sum of N and the number of stages of the other inverting circuits in the positive feedback loop is an odd number) connected to a cascaded delay circuit array 13 . An inverter 11 having a switch circuit 12 , a feedback circuit 14, a switch circuit input terminal (EN) 15, a control signal source 16, an inverter 17,
An oscillation output terminal 18 is provided.

When the switch circuit input terminal (EN) 15 is at a high level (H), the switch circuit 12 is a P-channel transistor connected between the power supply and the output terminal of the inverter 11 and Tr ₁ is OFF.
State, N = channel transistor having a source of N-channel transistor Tr ₄ is connected between the ground of the inverter 11
Tr ₂ is turned on, and the voltage of the common drain 20 of the inverter 11 is inverted and amplified by the inverter 17 and output to the oscillation output terminal 18.

On the other hand, the voltage of the common drain 20 of the inverter 11 is input to the delay circuit array 13 through a feedback circuit 14, the delay circuit array 13
Is composed of N stages of delay circuits having a NAND configuration, and forms a feedback loop including an odd number of stages of inverting circuits in combination with the inverter 11 and the feedback circuit 14, so that it becomes a positive feedback and becomes an oscillation circuit. The delay circuits at each stage can be controlled by a control signal (control voltage) from the control signal source 16 to control the oscillation frequency.

Next, details of the delay circuit 100 will be described based on FIG. Now, a positive power supply voltage V _DD is selected as a first reference potential, and a ground V _SS is selected as a second reference potential. Two FETs complementary connected between the first and second reference potentials are connected to the aforementioned reference potential. with the selection of the potential, the first FET (FET1) is N-channel type, the second FET (FET2) are each drain with chosen P-channel type is a complementary connected D, source S ₁ of the FET1 is V _SS the source S ₂ of FET2 are connected to V _DD. The gate G ₁ of the FET1 is used as a delay circuit input terminal, a gate G ₂ of FET2 is used as a control signal (control voltage) input from the control signal source.

The drain D capacitor 4 between the second reference potential (ground) is connected from being connected to the buffer circuit 101 constituted separately by the drain D of, for example two stages of inverters, the delay circuit output terminal of the circuit 101 Output terminal Q. The capacitor 4 is, for example, an MIS (Metal-In
(sulator-semiconductor) type capacitor.

The operation of the delay circuit will be described. First, FET1 and FET2 operate as a NAND circuit, and the delay circuit input voltage V _IN
Is high level (H) and the control signal voltage Vc is high level (H), the FET 1 is ON and the voltage d _out of the drain D is low level (L). Here, in order to make the FET 2 also function as a current control element, the Vc is always a voltage within the range of the H level, and the output voltage d _{out of the} NAND circuit is used.
Is high or low is controlled by whether the _VIN is high or low. In the delay circuit time chart of FIG. 1 c), V _IN is H
When the level shifts from the L level to the L level, the FET 1 goes to the OFF state, and the capacitor 4 is charged as the voltage of D rises,
When the voltage exceeds the threshold voltage of the buffer circuit 101, the voltage of the output terminal Q reaches the H level. V _IN goes high again due to positive feedback, and the above operation is repeated.

Here, the operation of the delay time control of the delay circuit will be described. The potential V of the d _out is V ≒ 0 at the initial time t = 0.
Since there is a relationship of electric charge q = CV (C is capacitance), It is.

If the threshold voltage for logical operation is V _DD / 2, Is the delay time of this delay circuit. (The delay time of the buffer circuit is ignored here).

Rewriting the above formula, However, focusing on FET2 as a current control element, the following equation was substituted.

Here, since _VGS can be controlled, the frequency is variable.
As a result, the drawbacks of the VCO of the type in which the frequency is changed by controlling the power supply voltage of the inverter as shown in the conventional example are eliminated, and the frequency variable range can be widened.

The oscillation frequency is determined by the number of stages of the delay circuit and the capacitance C of the capacitor 4 in addition to the current of the FET 2 of the delay circuit. Since the configuration of this circuit is simple and flexible, VCOs having various frequency ranges can be easily obtained. In addition, this circuit is excellent in noise resistance as described in the section of operation.

In the present embodiment, the switch circuit 12 is connected by providing the inverter 11 ; however, the switch circuit 12 may be directly connected to one of the delay circuits 100 (the delay circuit is an odd number of stages).

〔The invention's effect〕

According to the embodiment of the present invention, the power supply voltage of the delay circuit is not operated during the frequency control. Therefore, a large current does not flow through the CMOS delay circuit provided between the first and second reference potentials (for example, between the power supply and the ground). Since the multi-vibrator circuit or the like is not included in the positive feedback loop that regulates the time constant, a ring oscillation circuit that is resistant to interference by noise can be obtained. Since the circuit has a wide frequency variable range and a simple and flexible circuit configuration, VCOs having various frequency ranges can be easily obtained. Therefore, particularly when used for an integrated circuit, the effect of preventing heat generation, increasing the degree of freedom in design, and preventing malfunction is extremely large, and the design of a PLL (Phase-locked loop) circuit or the like can be facilitated.

[Brief description of the drawings]

FIG. 1 is an embodiment, and FIG. 1 a) is a circuit diagram of the embodiment.
Figure b) is the details of the delay circuit 100, FIG. 1 c) a delay circuit 100
1 (d) is a time chart of the delay circuit array 13 . Figure 2 shows a conventional example (1) of a multivibrator type VCO type.
2a) is a circuit diagram, FIG. 2b) is state 1, FIG. 2c).
Indicates state 2. FIG. 3 shows a prior art (2) ring oscillator type VCO circuit. Fig. 4 shows a VCO introduced as a conventional example in JP-B-59-15212.
FIG. 5 shows an embodiment of the circuit shown in FIG. 11 … Inverter 12 … Switch circuit 13 … Delay circuit row 14… Feedback circuit 100 … Delay circuit 101 … Buffer circuit

Claims (1)

(57) [Claims] 1. A ring oscillation circuit comprising a plurality of CMOS-structured delay circuits connected in cascade and inserted into a positive feedback loop, wherein each of the plurality of delay circuits is connected between a first reference potential and a second reference potential. A gate of the first FET of the first and second field-effect transistors (FETs) complementarily connected to each other is used as an input terminal, a control signal is applied to a gate of the second FET, and the first and second FETs are connected. Connected to the common drain of the FET and the first
A capacitor is connected between the reference potential connected to the source side of the FET, a voltage amplification buffer circuit having a threshold value is connected between the drain and an output terminal, and a gate of the second FET is connected Apply the control signal to
A ring oscillation circuit, wherein an oscillation frequency is varied by controlling an output current of the FET.