JP2901499B2 - Active matrix substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate for forming a display device such as a color liquid crystal display, and more particularly to an active matrix substrate having a structure of an intersection between a lower metal wiring and an upper metal wiring.

[0002]

2. Description of the Related Art Liquid crystal displays have been put to practical use in various fields such as televisions, personal computers, in-vehicle devices, and measuring instruments because of their low voltage drive, low power consumption, and flat panel characteristics. In particular, active-matrix-driven displays have attracted attention as display means capable of full-color display, realizing large size and high definition.

FIG. 6 is an equivalent circuit diagram of an active matrix substrate used in this type of liquid crystal display. As shown in the figure, in the active matrix substrate, a gate wiring 2 and a drain wiring 5 are arranged on a glass substrate 1 so as to intersect. A thin film transistor 7 having a gate electrode connected to the gate wiring 2, a drain connected to the drain wiring 5, and a source connected to the pixel electrode 6 is arranged on the glass substrate 1 in a matrix.

As described above, in the active matrix substrate, it is necessary to arrange the gate wiring 2 and the drain wiring 5 so as to cross each other. In an active matrix substrate using an inverted staggered transistor, the gate wiring 2 is formed in a lower layer, and the drain wiring 5 is formed in an upper layer.

FIG. 7A is a plan view showing the structure of a conventional intersection of this type, and FIG. 7B is a sectional view taken along line bb. As shown in FIGS. 7A and 7B, a gate wiring 2 is formed on a glass substrate 1, and a drain wiring 5 orthogonal to the gate wiring 2 is formed via an interlayer insulating film 3 (hereinafter, referred to as a gate wiring 2).
This is called a first conventional example). Thus, the side wall of the lower layer gate wiring 2 tends to be vertical or inversely tapered, and the structure of the first conventional example has a drawback that the upper layer drain wiring 5 is easily disconnected.

To overcome this drawback, Japanese Patent Application Laid-Open
Japanese Patent No. 257638 proposes that the cross-sectional shape of the wiring is tapered by providing a side wall-shaped second metal layer on the side surface of the lower metal wiring (hereinafter referred to as a second conventional example). ). Although it is not related to an active matrix substrate, Japanese Patent Application Laid-Open No. 1-245542 proposes that the upper end of the lower wiring is processed into a round shape by performing a sputter etching process after forming the lower wiring. (Hereinafter, this is referred to as a third conventional example).

Japanese Unexamined Patent Publication No. Sho 62-210494 discloses a gate wiring 2 and a drain wiring as shown in FIG. 8 (A) and a sectional view taken along the line cc of FIG. 8 (B). It is proposed that an interlayer insulating film 3 and an amorphous Si film 4 be interposed between them (hereinafter referred to as a fourth conventional example).

[0008]

FIG. 7 (A)
The first conventional example shown in FIG. 2B has a drawback that the drain wiring 5 as the upper layer wiring is highly likely to be disconnected as described above. On the other hand, in the second and third conventional examples,
Disconnection of the upper wiring can be prevented because the cross-sectional shape of the lower wiring is not steep, but there is a disadvantage that another step for tapering the lower wiring is required. Further, when the upper end portion of the lower wiring is processed into a round shape, the gate electrode is also processed into a round shape at the same time, so that the effective gate length is shortened and the transistor operation becomes unstable.

In the fourth conventional example, amorphous Si
Although the film reduces the level difference of the lower wiring somewhat, it has not solved the fundamental problem.
There is a disadvantage that a new step is generated by the film. The present invention has been made in view of the above-described drawbacks and problems of the conventional examples, and has as its object to provide an active matrix having a structure capable of preventing disconnection of an upper wiring without adding a new process. It is to provide a substrate.

[0010]

According to the present invention, there is provided an active matrix substrate in which thin film transistors each having one end connected to a pixel electrode are arranged in a matrix, and a lower metal wiring and an upper metal wiring connected to a gate or a drain of the thin film transistor. There are those which are arranged orthogonally through the interlayer insulating film, in the intersection of the lower metal wiring and the upper layer metal wiring, is formed protruding portion, the lower metal interconnect, the tip of the projecting portion width, said being narrower than the width of the upper metal wiring of the part, yet to the lower metal wiring of the intersection, there sides with an angle between the lower metal wiring direction than the upper metal wiring direction of Or the upper metal wiring is formed via an insole semiconductor layer.
And has a width of the upper layer metal wiring direction of the distal end portion of the insole semiconductor layer, wherein are formed narrower than the width of the upper metal wiring that part, yet it heavy and said upper metal wire and the insole semiconductor layer If it overlaps with the lower wiring
The insole semiconductor layer of a portion without the existence edges having an angle between the lower metal wiring direction than the upper metal wiring direction
And the width of the upper metal wiring is in front of the insole semiconductor layer.
In the area that does not overlap with the lower metal wiring,
Formed so as to be wider than the maximum width of the semiconductor layer, and
In a region of the conductor layer overlapping with the lower metal wiring,
The semiconductor device is characterized in that the semiconductor device has a configuration in which the width is smaller than the maximum width of the semiconductor layer .

According to the arrangement of the invention, the upper metal interconnect can exceed the level difference of the underlying metal interconnect or insole semiconductor layer without a plurality of angles, yet at an angle which varies continuously. Generally, etching and film formation are not performed uniformly in all directions. Therefore, the step may be formed in a reverse taper shape at a certain angle, or the film formed on the step forming an angle may become thinner.

For this reason, in a structure in which the upper layer wiring extends over the step only at a right angle as in the conventional example, if the step is formed in a reverse taper shape, or if the film in this direction is made thin, It will be easy to break. However,
According to the above configuration of the present invention (a configuration in which the upper metal wiring crosses the step at different angles), even if the step at a certain angle has a reverse taper, or the film formation at that angle may be thin. However, since the metal film covers the step at another angle, a disconnection accident can be suppressed.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiment.

(First Embodiment) FIG. 1A shows a first embodiment of the present invention.
FIG. 1B is a plan view of an intersection in the embodiment of FIG.
It is the aa line sectional view. FIG. 2 is a sectional view of a pixel portion (thin film transistor portion) in the first embodiment (the configuration of this portion is the same as that of the conventional example). Since the structure of the first embodiment will be apparent from the description of the manufacturing method, a method of manufacturing the active matrix substrate of the present embodiment will be described below with reference to FIGS.

First, as shown in FIG. 1B, a metal such as Cr is deposited to a predetermined thickness on a glass substrate 1 by a sputtering method, and this is patterned to form a gate wiring 2.
The gate wiring 2 becomes a gate electrode 2a in the thin film transistor section (see FIG. 2). Next, by a plasma CVD method, a composite film of a silicon oxide film and a silicon nitride film is deposited to form an interlayer insulating film 3, and subsequently silicon is deposited in the same CVD apparatus to form a non-doped amorphous Si.
An amorphous Si film 4 composed of the film 4a and the n ⁺ type amorphous Si film 4b is formed.

Subsequently, the amorphous Si film 4 is patterned so as to remain in an island shape at the intersection of the thin film transistor forming portion and the wiring. At this time, the amorphous Si film 4 at the intersection is formed in a rectangular shape with a corner portion dropped. By forming the shape with the corner portion dropped, the upper layer wiring passing thereover intersects the step at more angles.

Next, a metal such as Cr is deposited to a predetermined thickness by a sputtering method, and is patterned to form a drain wiring 5 serving as an upper wiring. Projections are formed on both sides of the drain wiring 5 beyond the step.
(See FIG. 1 (A)). In the step of forming the drain wiring 5, the drain electrode 5a is simultaneously formed in the thin film transistor region.
And a source electrode 5b are formed (see FIG. 2).

Next, ITO, which is a transparent conductive film, is deposited by sputtering, and is patterned to form a source electrode 5b.
Is formed (see FIG. 2). Then, the n ⁺ -type amorphous Si film 4b (see FIG. 2) between the drain electrode 5a and the source electrode 5b is removed by etching, and although not shown, a protective film is formed thereafter to form the active matrix substrate of the present embodiment. Production is completed.

In the cross wiring structure formed as shown in FIG. 1A, the drain wiring 5 intersects the end of the amorphous Si film 4 forming the step at five different angles on one side. Therefore, even if the film is formed thin at a certain angle, the other portions have a sufficient film thickness, so that the occurrence of a disconnection accident can be avoided.

(Second Embodiment) FIG. 3 is a plan view showing a state of an intersection according to a second embodiment of the present invention. In the second embodiment, projections are provided on both the amorphous Si film 4 and the drain wiring 5 which are the insole at the step over the step. In the second embodiment, the projections of the amorphous Si film 4 have a polygonal shape, but instead, projections having a curved outer shape may be provided.

(Third and Fourth Embodiments) FIGS. 4 and 5 are plan views showing states of intersections in third and fourth embodiments of the present invention, respectively. In the third and fourth embodiments, the projection is provided on the gate wiring 2 which is the lower wiring. The third embodiment is different from the first and second embodiments in that an insulative amorphous Si film is not used.

In the third embodiment, as shown in FIG. 4, the protrusion of the gate wiring 2 has a smooth curve. Even in the case of such a configuration, since the drain wiring 5 crosses the step at different angles (slightly changing), the disconnection of the upper layer wiring can be prevented. Also,
The third and fourth embodiments have the advantage that the area of the intersection can be made smaller than in the first and second embodiments.

In the above-described first to third embodiments, the description has been made of one having an inverted staggered transistor.
The present invention is also applicable to an active matrix substrate on which a positive staggered thin film transistor is formed. In this case, the drain wiring becomes a lower wiring and the gate wiring becomes an upper wiring, which are also included in the present invention.

[0024]

As described above in detail, the active matrix substrate according to the present invention is configured such that when the upper layer wiring crosses the step, the step intersects the step at a different angle, so that the step at a specific angle is formed in a reverse taper shape. Or
Even if a film formed at a specific angle is formed to be thin, it is possible to cover a disconnection therefor with a metal film at another angle, and it is possible to greatly reduce a disconnection accident at an intersection. Further, the active matrix substrate according to the present invention does not add any change to the conventional manufacturing process, and therefore can be implemented without increasing the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a view showing a state of an intersection according to a first embodiment of the present invention, wherein (A) is a plan view thereof, and (B) is a cross-sectional view taken along line aa of (A).

FIG. 2 is a sectional view of a display unit according to the first embodiment of the present invention.

FIG. 3 is a plan view of an intersection according to a second embodiment of the present invention.

FIG. 4 is a plan view of an intersection according to a third embodiment of the present invention.

FIG. 5 is a plan view of an intersection according to a fourth embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of an active matrix substrate.

FIGS. 7A and 7B are diagrams showing a first conventional example, in which FIG. 7A is a plan view and FIG. 7B is a cross-sectional view taken along line bb of FIG.

8A and 8B are views showing a fourth conventional example, wherein FIG. 8A is a plan view thereof, and FIG. 8B is a sectional view taken along line cc of FIG. 8A.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Gate wiring 2a Gate electrode 3 Interlayer insulating film 4 Amorphous Si film 4a Non-doped amorphous Si film 4b n ⁺ type amorphous Si film 5 Drain wiring 5a Drain electrode 5b Source electrode 6 Pixel electrode 7 Thin film transistor

Claims (3)

(57) [Claims] 1. A thin film transistor having one end connected to a pixel electrode is arranged in a matrix, and a lower metal wiring connected to one of a gate and a drain of the thin film transistor and one of a gate and a drain of the thin film transistor connected to the other. An active matrix substrate in which the upper metal wiring is orthogonally arranged with an interlayer insulating film interposed therebetween, wherein at the intersection of the lower metal wiring and the upper metal wiring, a projection is formed on the lower metal wiring, The width of the tip of the protrusion is formed to be narrower than the width of the upper metal wiring at that portion, and the protrusion has a polygonal shape.
The active matrix substrate characterized in that that. 2. A thin film transistor having one end connected to a pixel electrode is arranged in a matrix , and
Underlayer gold connected to either gate or drain
Metal wiring and thin film transistor gate or drain
Or the upper metal wiring connected to the other via an interlayer insulating film.
Active matrix substrates arranged orthogonally
At the intersection of the lower metal wiring and the upper metal wiring,
A protrusion is formed on the lower metal wiring, and a tip of the protrusion is formed.
The width of the part is smaller than the width of the upper metal wiring of the part.
An active matrix substrate , wherein the projection has a curved shape on a plane. 3. A thin film transistor having one end connected to a pixel electrode is arranged in a matrix, and a lower metal wiring connected to one of a gate and a drain of the thin film transistor and one of a gate and a drain of the thin film transistor. in the active matrix substrate upper metal wire and are arranged orthogonally through the interlayer insulating film, in the intersection of the lower metal wiring and the upper layer metal wiring, the upper metal interconnect through the insole semiconductor layer formed was are, the width of the upper layer metal wiring direction of the distal end portion of the insole semiconductor layer overlies said being upper metal narrower than the width of the wiring of the portion, and with the insole semiconductor layer and the upper metal interconnect the insole semiconductor layer in a portion which does not overlap with the lower wiring a portion have a polygonal shape or curve
Has a shape, a width of the upper layer metal wiring, the in the region where the does not overlap with the lower metal interconnect insole semiconductor layer is formed wider than the maximum width of the insole semiconductor layer, and wherein the insole semiconductor layer An active matrix substrate having a configuration in which a region overlapping with a lower metal wiring is formed to be narrower than a maximum width of the insole semiconductor layer.