JP2875435B2 - Memory module and computer using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module and a computer using the same, and more particularly, to a memory module which can be mounted on a memory expansion connector which handles data for error detection of data written in a memory, and a memory module. The present invention relates to a computer in which a memory module that does not store error detection data can be mounted on a memory expansion connector having such specifications.

[0002]

2. Description of the Related Art Conventionally, in a memory used for a computer, in particular, a semiconductor memory which can be freely read and written,
In order to ensure the reliability of the written data, information such as parity and checksum is added. Taking parity as an example, a processor (hereinafter, CPU)
) And a memory are provided with a parity generator that takes in the data and generates parity. The parity generator normally generates 1-bit parity data for 8-bit data. The memory has a 9-bit configuration. When 8-bit data is written, parity data generated by the parity generator is written in the ninth bit. When the width of the data bus is large, parity data is added every 8 bits.
In the case of 6 bits and 32 bits, the data to which the parity bit is added becomes 18 bits and 36 bits, respectively.

On the other hand, when reading data, the parity of 9-bit data is checked, and if the parity does not have the parity determined at the time of writing, some correspondence is taken as a parity error. By the way, there are various ways of assuring the reliability of the contents of the memory, and there are various methods for processing as a serious error and those for processing as a minor error. According to the former idea, the data includes an instruction to be executed by the CPU, and if a parity error occurs, there is a risk of runaway, and the operation of the CPU is immediately stopped. On the other hand, when only simple data is stored, there is an idea that special measures such as stopping the CPU are not performed. These are determined by the characteristics of the computer incorporating the memory system, the purpose of use, and the like.

[0004]

However, a computer provided with an additional slot for expanding the memory capacity has a parity check signal exchanged with a memory module connected to an expansion connector. And a configuration in which parity check is not performed, which has been a problem in commonizing memory modules. In other words, if it is designed according to the former, if it is mounted on the latter, the memory for parity check will be wasted. Can not.

In recent years, the reliability of semiconductor memories has been improved and the possibility of parity errors has become extremely low. Even when it can be determined that a parity check is unnecessary for a memory module, the parity check is emphasized. In many cases, expensive memory must be used in consideration of the possibility of being attached to a computer with an old design.
This has been a problem from the viewpoint of not only cost reduction but also resource saving and energy saving.

An object of the present invention is to solve the above problems and to provide a memory module capable of flexibly coping with a parity check configuration and a computer using the same, and has the following configuration.

[0007]

As shown in FIG. 1, a memory module according to the present invention is connected to a memory extension connector M1 provided with a signal line at least capable of reading data from a processor in a computer. a memory module that, the signal for reading the data stored in the memory, upon receiving via the memory expansion connector M1, in accordance with the data read from the memory, the read data That the data is correct
Is generated as error detection data , and
Error detection data generating means M for outputting to the computer side
The gist is to have 2.

On the other hand, a computer according to the present invention includes a processor for performing a logical operation, an internal memory for storing at least data related to processing of the processor, a memory expansion connector to which a memory module can be attached, When writing data to a memory module attached to the memory expansion connector, error detection data output means for generating and outputting error detection data in accordance with the data, and reading data from the internal memory. A data determination unit that reads the error detection data stored at the time of writing in association with the data, and determines the likelihood of the read data from the data and the error detection data. In addition, the additional connector has a connection to a memory module by the processor. When writing data, an error data output signal line for outputting error detection data generated by the error detection data output means is connected, and the data stored in the memory module is read. The present invention further comprises an error detection data generation unit that generates the error detection data in accordance with the data read from the memory module and outputs the data to the data determination unit.

[0009]

When the memory module of the present invention configured as described above receives a signal for reading data stored in the memory via the memory extension connector M1, the error detection data generating means M2 transmits the signal from the memory. Read data is correct data according to the read data.
Generating data indicating that the data for error detection
This is output to the computer . Accordingly, the memory module also connects to a memory Expansion connector M1 configurations performing erroneous Ri detected when reading data, can be used as it is.

On the other hand, the computer according to the present invention has a memory module mounted on a connector for adding a memory, and an error detection data output means and a data judgment means are provided inside the computer. It is possible to determine the certainty of data written to the memory module mounted on the connector. 2. The memory expansion connector according to claim 1, wherein an error data output signal line for outputting error detection data generated by the error detection data output means is connected to the memory expansion connector. The memory module does not use this signal. On the other hand, when reading data from the memory module, the error detection data generation means generates error detection data according to the data read from the memory module, and outputs the data to the data determination means. Therefore, even if there is no memory for storing the error detection data, the memory module can be mounted on a computer for determining the reliability of the data and used.

The error detection data generating means is preferably provided on the memory module, but may be connected to another expansion slot of the computer or an internal connector directly connected to the bus. Also,
As the error detection data, in addition to the parity data, various known data such as a checksum, a harmonic code, a cyclic redundancy code (CRC), and the like can be used.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to further clarify the structure and operation of the present invention described above, preferred embodiments of the present invention will be described below. FIG. 2 shows a memory module 1 as an embodiment.
Is a schematic configuration diagram showing an internal configuration of the computer 5 in which the memory module 1 is mounted on the extension connector 3. FIG. 3 is a block diagram showing an internal configuration of the memory module 1.

As shown in FIG. 1, a well-known CPU 11, ROM 12, RAM 14,
An image controller 18 for outputting image data to the liquid crystal display 16, a parity controller 20, and the like are provided. The CPU 11, the ROM 12, and the like are interconnected by an internal bus 22 including an address signal line, a data signal line, and a control signal line. The computer 5 has an architecture with a data bus width of 16 bits and an address bus width of 24 bits. The RAM 14 is composed of 18 1-bit × 1 mega dynamic RAMs. These dynamic memories form a low-order byte and a high-order byte as a set of eight, respectively.
AM is used for storing one parity bit for each set. The role of these elements in a computer is well known, and a description thereof will be omitted.

The parity controller 20 includes a memory 14
Corresponding to the internal configuration {(8 + 1) × 2 sets}, two sets of the same configuration for checking the evenness of the number of bits of value 1 in 9-bit data are provided. As an element for checking the parity, for example, TTL74LS280 manufactured by Texas Instruments or the like can be used. 9
Considering a bit as a unit, the 8-bit input terminals A to H of the element are the upper byte or lower byte of the internal data bus, and the 1-bit input terminal I is the data output of the parity check memory provided in the RAM 14. Connected to terminal O. The element that checks for parity is
When data is read from or written to the RAM 14, the number of 1-value bits included in the 8-bit data and 1-bit parity data output to the data bus is counted. The output ODD has an output of a high level when the number is one.

Therefore, when the internal RAM 14 is accessed, the parity controller 20 and the RAM
The data exchange with 14 is as follows. When Writing Data to RAM 14 When writing data from the CPU 11, the write address output by the CPU 11 is time-divided into upper and lower bits and output to the address bus. Simultaneously with the establishment of the address signal, the data to be written to the RAM 14 is output onto the data bus, and the write enable signal / WE for permitting the writing of the data to the RAM 14 is set to the active state (low level). At this time, the parity input I
In this case, since no data is output from the CPU 11, the input I is maintained at the low level. The element in the parity controller 20 receiving the 8-bit data D0 to D7 and D8 to D15 output to the data bus and the data to the terminal I, based on the parity of the number of bits of value 1 included in the data, The output ODD is determined to be low level (parity = even number) or high level (parity = odd number). The contents of the output ODD are written to the parity memory of the RAM 14.

When Reading Data from RAM 14 When CPU 11 reads data from RAM 14,
The read address output from the PU is time-divided into upper and lower parts and output to the address bus. This address signal is RA
When the write enable signal / WE is disabled and a predetermined time has passed while the write enable signal / WE is disabled, the RAM 1
The data of the corresponding address is read from the four memory elements and output to the data bus. This address signal is R
Since the data is also provided to the parity memory of the AM 14, 1-bit data for the parity is simultaneously read and output to the input terminal I of the parity controller 20. In the parity memory, the value 0 is written for even parity and the value 1 is written for odd parity at the time of data writing. Therefore, the entire 9 bits including the parity data (1 bit) are written. , The result is that even parity is maintained. Therefore, the output ODD of the parity controller 20 is kept at a low level when data is read from the RAM 14 unless there is a parity error. As described above, the parity controller 2
0 has two sets of the above configuration, so that the same processing is performed for 16-bit data (1 word) for each of the upper byte and the lower byte.

When data is read from the RAM 14, if a bit drop or the like occurs in the data in the RAM 14 due to a soft error or the like, the parity of the data in the RAM 14 in units of 8 bits may become an odd number. , The output ODD of the parity controller 20 becomes high level. This output ODD is connected via an AND gate 24 to an interrupt input terminal INT of the CPU 11, and the other input terminal of the AND gate 24 is connected to a write enable signal / WE. RAM14
When data is read from the write enable signal /
Since WE is kept in the disabled state (high level), the CPU 11 can know the occurrence of the parity error by the interrupt request.

The parity check for the RAM 14 as the internal memory of the computer 5 has been described above. Next, the parity check in the memory module 1 connected to the memory expansion connector 3 will be described. FIG. 3 is a block diagram schematically showing a configuration inside the memory module 1. Although the width of the data bus of the memory module 1 is 16 bits, since the upper byte and the lower byte have almost the same configuration, only the configuration of the lower byte data D0 to D7 will be described here.
The upper byte has the same configuration, but illustration and description are omitted.

The memory module 1 includes eight dynamic RAMs 31 to 38 for a lower byte, a multiplexer 40 for time-dividing an address signal, a parity generator 41, and two octal line buffers 4.
4, 45, etc. are provided. 8 dynamic R
Each of the AMs 31 to 38 is a well-known device having a configuration of 1 bit × 1 megabit, and is connected to the multiplexed output bus of the multiplexer 40 in eight pieces in parallel so that 1
Configures a megabyte memory space. A signal obtained by decoding a higher-order signal of an address that determines the allocation of the memory module 1 to the memory space of the entire computer 5 is also connected to the memory module 1, but is not shown.

The octal line buffers 44 and 45
The connection between the data input terminals Din and output terminals Dout of the RAMs 31 to 38 and the data buses D0 to D7 is controlled.
Is shown as being controlled. That is, the DRAM 31
When the write enable signal / WE attains a low level at the time of writing data to the data through to 38, the output of the octal line buffer 44 is enabled,
Data buses D0 to D7 are DRAMs 31 to 38
Are connected to the respective data input terminals Din. On the other hand, when data is read from the DRAMs 31 to 38 and the write enable signal / WE goes high, the write enable signal / WE
Since the gate terminal G of 45 is controlled by the signal inverted at 8, the output of the octal line buffer 45 is enabled, and D0 to D7 of the data bus are set to D.
The RAMs 31 to 38 are connected to the respective data output terminals Dout.

The data output terminals Dout of the DRAMs 31 to 38 are connected to the input terminals A to H of the parity generator 41 together with the octal line buffer 45, and the output ODD of the parity generator 41 is used as a parity check signal PC for extension. Output to connector 3. In this embodiment, the parity check signal PC is connected to the input terminal I of the parity controller 20. Accordingly, the parity of the data read from the memory module 1 is checked by the parity controller 20 together with the parity check signal PC.

Since a normal memory module has a memory for storing parity therein, when data is read, the parity check data is read together with the data, and the parity controller 20 checks the parity of the data. It is done. If the parity of the data is not properly maintained, the CPU 11 is notified of the parity error by the interrupt INT as in the case of reading data from the RAM 14 which is an internal memory.

On the other hand, in the memory module 1 of this embodiment, when data is written from the CPU 11, the parity data output from the parity controller 20 is ignored. On the other hand, when data is read from the memory module 1 by the CPU 11, the parity generator 41 generates parity data in accordance with the data read from the DRAMs 31 to 38, and generates the parity data in accordance with the output of the data. Signal P
Output as C. The parity of the read data and the parity check signal PC is checked by the parity controller 20.

Here, the parity check signal PC is:
Since it is generated according to the data read at that time,
The parity of the data and the parity check signal PC is always in a correct state. Therefore, the parity controller 20 cannot detect a parity error.

As described above, according to the memory module 1 of the present embodiment, while being attachable to the additional connector 3 of the computer 5 for performing the parity check,
There is no need to provide an extra memory for storing parity data. Normally, one bit is provided for 8-bit data, so that the memory can be reduced to 8/9 of the conventional memory module. Therefore, it is possible to eliminate waste of memory in an application that does not require a parity check. Further, the present invention can be used equally whether the computer to be mounted is configured to perform a parity check on the memory module mounted on the memory expansion connector or not.

On the other hand, in the computer 5 using the memory module 1, when data is written, conventionally, data to be written is established on the data bus, and the parity generator responds accordingly. Only after generating the data can the data be written to the memory. On the other hand, in the memory module 1 of the embodiment, since it is not necessary to write the parity data, the data can be written to the memory immediately after the data is established on the data bus. In data transfer, when a bus configuration is used in which an acknowledge signal ACK is returned from the slave side, this configuration in which parity data is not written in memory directly contributes to a reduction in data write time.

The embodiment of the present invention has been described above.
The present invention is not limited to such embodiments. For example, a configuration for applying another error correction code such as a harmonic code, a configuration applied to a memory module having a built-in ROM, and an external storage device using a flash memory may be used. The configuration applied to the memory module, the parity generator 41 is provided outside the memory module 1 (for example,
A configuration provided in another extension connector of the computer 5 or an adapter interposed between the extension connector 3 and the memory module 1), an external storage device in which the memory module stores data in a file format such as a hard disk or the like Of course, the present invention can be implemented in various modes without departing from the gist of the present invention.

[0028]

Memory module of the present invention described above, according to the present invention, while it can be attached to an expansion connector of the computer that performs error detection of the parity check or the like, erroneous
The advantage is that the memory for storing the detection data is not required. For this reason, the memory module can be shared, and resources and energy can be saved. Further, in a computer using this memory module, the time required for writing data to the memory module can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a basic configuration of a memory module according to the present invention.

FIG. 2 is a schematic configuration diagram of a computer in which a memory module 1 according to an embodiment of the present invention is mounted on an additional connector 3.

FIG. 3 is a block diagram illustrating an internal configuration of a memory module 1 according to the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory module 3 ... Extension connector 5 ... Computer 11 ... CPU 12 ... ROM 14 ... RAM 16 ... CRT 18 ... CRTC 20 ... Parity controller 22 ... Internal bus 24 ... And gates 31 to 38 ... DRAM 40 ... Multiplexer 41 ... Parity generator 44 ... Octal line buffer

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 12/16 320 G06F 11/10 320

Claims (2)

(57) [Claims] 1. A memory module connected to a memory expansion connector having a signal line configured to at least read data from a processor in a computer, wherein the memory module transmits a signal for reading data stored in the memory to the memory module. when received via the extension connector, in accordance with the data read from the memory, the read the data
A memory module comprising : error detection data generating means for generating data indicating that is correct data as error detection data , and outputting the data to the computer side . 2. A processor for performing a logical operation, an internal memory for storing at least data related to processing of the processor, a memory expansion connector to which a memory module can be attached, and the internal memory or the memory expansion connector. When writing data to the mounted memory module, error detection data output means for generating and outputting error detection data in accordance with the data, and when reading data from the internal memory, linking the data with the data. A computer for reading the error detection data stored at the time of writing, and data determination means for determining the certainty of the read data from the data and the error detection data; When the processor writes data to the memory module, An error data output signal line for outputting error detection data generated by the output data output means is connected, and further, when data stored in the memory module is read, the data read from the memory module is read out. A computer comprising: an error detection data generation unit that generates the error detection data according to data and outputs the data to the data determination unit.