JP2874619B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a synchronous DRAM (Synchronous Dynamic Input / Output) for inputting addresses and commands and inputting / outputting data in synchronization with an external clock signal.
The present invention relates to a semiconductor memory device in which a setup time and a hold time of a command control signal are shortened in a random access memory (Random Access Memory).

[0002]

2. Description of the Related Art In recent years, with the speeding up of DRAMs, 100
Synchronous D synchronized to an external clock exceeding MHz
RAM is about to emerge. At that time, a stricter specification than before is required for the characteristics of the setup time and the hold time.

An example of a command decoding method in a conventional synchronous DRAM is disclosed in Japanese Patent Laid-Open No. 7-141870.
You can see in such. In this synchronous DRAM, CLK is used as a clock input terminal, and CKE, CSB, RASB, CASB, WE are used as command input terminals.
B and DQM (B at the end of the signal name indicates a low enable signal).
To Ai, and DQ0 to DQ as data input / output terminals.
j, each of which inputs an address and a command and inputs and outputs data with reference to a rising edge of the external clock signal CLK.

Referring to FIG. 6 which shows a block diagram of an example of the above-described command decoding method, in the semiconductor memory device 200, an input buffer circuit 1 is connected to an external clock signal CLK input terminal 21. This input buffer circuit 1 has a clock enable terminal for controlling whether or not to output an input clock signal, and its output terminal is connected to the leading drive buffer N1 of the cascade-connected drive buffers N1 and N2. Is done. Drive buffer N2 outputs internal clock signal ICLK.

The input buffer circuit 2 is connected to the external clock enable signal CKE input terminal 22. The output terminal of the input buffer circuit 2 is connected to the leading drive buffer N3 of the cascade-connected drive buffers N3 and N4. It outputs the internal clock enable signal ICKE and is also connected to the enable terminal of the input buffer circuit 1.

[0006] Chip select signal CSB input terminal 23
, The input buffer circuit 4 is connected to the row address selection signal RASB input terminal 24, the input buffer circuit 5 is connected to the column address selection signal CASB input terminal 25, and the write enable signal WE is connected.
The input buffer circuit 6 is connected to the B input terminal 26, and these input buffer circuits 3 to 6 are connected to the output line A1 at the output terminal thereof.
Through A4, respectively, to both the command decode circuits 9 and 10.

The output end of command decode circuit 9 is connected to internal clock skew signal I via decode output line C1.
CLK1 is supplied to a latch circuit 11, from which an operation mode determination signal MODE1 is supplied to an internal circuit.

The output terminal of the command decode circuit 10 is connected via a decode output line C2 to a latch circuit 11 to which an internal clock skew signal ICLK2 is supplied, and from this latch circuit 11, an operation mode determination signal MODE2 is sent to the internal circuit. Supplied.

In the operation of the semiconductor memory device 200, first, an external clock signal CLK is fetched through the input buffer circuit 1. The input buffer circuit 1 is activated by the internal clock enable signal ICKE output through the driving buffers N3 and N4 of the output of the input buffer circuit 2 receiving the clock enable signal CKE. That is, the input buffer circuit 1 is activated when the internal clock enable signal ICKE is at a high logic level (hereinafter, referred to as H level), takes in the external clock signal CLK, and outputs the internal clock signal ICLK.
Is supplied to the internal circuit.

In this example, a chip select signal CSB, a row address strobe signal RASB, and a column address signal are used in order to shorten the time required for decoding in the command decode circuit 9 and to simplify the circuit.
Strobe signal CASB, write enable signal WE
The command control signals of B are fetched through the input buffer circuits 3 to 6 and are directly received by the command decode circuit 9.
And 10 are entered. The outputs of the command decode circuits 9 and 10 are connected to the latch circuits 11 and 1 respectively.
2, the command decode signal is latched and held in synchronization with the rising edges of the internal clock skew signals ICLK1 and ICLK2, and the operation mode determination signals MODE1 and MODE2 are output.

Although the address signal is also used for the final operation mode determination, it is omitted in FIG.

Referring also to FIG. 7 which shows a timing chart in the command decode system, the signal C
With KE at H level, the external clock signal CL
K is made valid. Command control signals (CSB, RAS
B, CASB, and WEB) are input so as to have a setup time (tSE) and a hold time (tHE) with respect to the external clock signal CLK.

The signals on the output lines A1 to A4 correspond to the command control signal in the time (t) passing through the input buffer circuits 3 to 6.
0) Change by minutes. Next, the signals on the output lines C1 and C2 correspond to the delay due to the wiring length from each of the input buffer circuits 3 to 6 to the command decode circuits 9 and 10, and the time required to pass through each of the command decode circuits 9 and 10. It changes with a delay (t11 and t12). These signal changes are read and held by latch circuits 11 and 12 in synchronization with the rising edge of internal clock signal ICLK. However, the internal clock signal ICL
Since K also has a shift (skew) Δt due to a wiring delay or the like, these internal clock signals ICLK are denoted as internal clock skew signals ICLK1 and ICLK2.

Referring to FIG. 8 which shows a block diagram of another example of the command decode system, in the semiconductor memory device 300, an input buffer circuit 1 connected to an external clock signal CLK input terminal 21 has an input The output terminal is connected to the leading drive buffer N1 of the cascade-connected drive buffers N1 and N2 and to the delay circuit 7, respectively. The driving buffer N2 outputs an internal clock signal ICLK, and the output terminal of the delay circuit 7 is connected to the leading buffer N3 of the driving buffers N3 and N4 connected in cascade, and the driving buffer N4 outputs the internal clock delay signal ICLKD. .

Clock enable signal CKE input terminal 2
2, an output terminal thereof is connected to the leading drive buffer N3 of the cascade-connected drive buffers N3 and N4, and an output terminal of the drive buffer N4 outputs the internal clock enable signal ICKE and It is also connected to the enable terminal of the buffer circuit 1.

Chip select signal CSB input terminal 23
Is connected to the flip-flop circuit DF / F8a to which the internal clock skew signal ICLK1 is supplied via the output line A1.

The input buffer circuit 4 is connected to the row address selection signal RAS input terminal 24, and its output terminal is connected to the output line A.
2 is connected to a DF / F circuit 8b to which the internal clock skew signal ICLK2 is supplied.

The input buffer circuit 5 is connected to the column address selection signal CAS input terminal 25, and its output terminal is connected to the output line A.
3 is connected to a DF / F circuit 8c to which the internal clock skew signal ICLK3 is supplied.

Write enable signal WE input terminal 26
Is connected to a DF / F circuit 8d to which an internal clock skew signal ICLK4 is supplied via an output line A4. The output terminals of these DF / F circuits 8a to 8d are connected to both command decode circuits 9 and 10, respectively.

The output end of the command decode circuit 9 is connected via a decode output line C1 to a latch circuit 11 to which an internal clock delay skew signal ICLKD1 is supplied.
The operation mode determination signal MODE1 is output from the latch circuit 11.
Is supplied to the internal circuit.

The output end of the command decode circuit 10 is connected via a decode output line C2 to a latch circuit 12 to which an internal clock delay skew signal ICLKD2 is supplied.
E2 is supplied to the internal circuit.

In the operation of the semiconductor memory device 300, first, the external clock signal CLK is fetched through the input buffer circuit 1. The input buffer circuit 1 is activated by the internal clock enable signal ICKE as in the case of the semiconductor memory device 200 described above. In this example, each command control signal CSB, RASB, CAS
B and WEB are fetched through the input buffer circuits 3 to 6, respectively, and are read and held by the DF / F circuits 8a to 8d in synchronization with the rising edge of the internal clock signal ICLK.

Further, these read signals are supplied to command decode circuits 9 and 10. Outputs decoded by these command decode circuits 9 and 10 are supplied to latch circuits 11 via output lines C1 and C2.
And 12 respectively. Latch circuits 11 and 12 receive internal clock signal I as their clock signals.
CLK is latched in synchronization with rising edges of internal clock delay skew signals ICLKD1 and ICLKD2 delayed by delay circuit 7, and operation mode determination signals MODE1 and MODE2 are output. The reason for providing the latch circuit in this way is to prevent noise and hazard from being put on the mode determination signal.

Referring now to FIG. 9 which shows a timing diagram in the command decoding system, the external clock enable signal CKE is at H level, the external clock signal CLK is enabled, and the command control signal Each of the signals (CSB, RASB, CASB, WEB) is input so as to have a setup time (tSE) and a hold time (tHE) with respect to the external clock signal CLK, as in the semiconductor memory device 200 described above. It is.

First, the signals on the output lines A1 to A4 change with a delay (t0) through the input buffer circuits 3 to 6 with respect to the command control signal. These changes are synchronized with the rising edge of the internal clock signal ICLK,
The data is read and held by the DF / F circuits 8a to 8d. However, since there is skew in ICLK as described above, these internal clock skew signals are output from ICLK.
1 to 4.

Next, the signals on the output lines C1 and C2 are respectively
The delay time (t11, t12) changes by a delay time caused by the wiring length from the F circuits 8a to 8d to the command decode circuits 9 and 10, and by a time passing through the command decode circuits 9 and 10.

These signal changes correspond to the internal clock signal I
CLK is latched by latch circuits 11 and 12 in synchronization with the rising edge of internal clock delay signal ICLKD delayed by delay circuit 7, and operation mode determination signals MODE1 and MODE2 are output.

Since internal clock delay signal ICLKD has a skew similarly to internal clock signal ICLK, these internal clock delay signals ICLKD are described as internal clock delay skew signals ICLKD1 and ICLKD2. The delay time of the delay circuit 7 is determined by the internal clock signal ICL.
After the time (t21) when the change of the output lines C1-2 is determined from the rise of K, the internal clock delay signal ICL
KD is set to rise.

[0029]

Here, the sum (internal window width) of the setup time (tSI) and the hold time (tHI) inside the chip in the semiconductor memory devices 200 and 300 described above will be considered. First, in the case of FIG. 7 showing a timing chart of the semiconductor memory device 200, for simplicity, t11> t12, Δt (IC of ICLK2)
(Skew with respect to LK1), and assuming that tSE + tHE = tSI + tHI + (t11−t12) + Δt (1), the internal window width is (t11−t12) +
There has been a problem that the width becomes smaller than the external window width by Δt.

In the case of FIG. 9 showing a timing chart of the semiconductor memory device 300, if Δt = skew width of ICLK, then tSE + tHE = tSI + tHI + Δt (2). Therefore, there is a problem that the inner window width becomes smaller than the outer window width by the time Δt. In other words, in the specifications of the conventional setup time and hold time, the reduction of the window width was negligible compared to the window width in any of the above cases.
In the specifications of the setup time and the hold time in the high-frequency operation exceeding z, the clock width is shortened and the window width is also narrowed, so that the ratio of the reduction in the window width to the window width cannot be ignored.

An object of the present invention has been made in view of the above-mentioned drawbacks, and provides a semiconductor device corresponding to high speed by having an internal window width equal to the external window width in a command control signal of the semiconductor memory device. It is in.

[0032]

A feature of the semiconductor memory device of the present invention is that an internal clock skew signal and an internal clock delay in response to a clock signal supplied from an external terminal are provided.
A first input means for supplying to the internal circuit, respectively as a skew signal, and a plurality of second input means for a predetermined control signal is supplied from a plurality of external terminals, the internal output from the first input means Signal holding means for latching and holding output signals output from the plurality of second input means at the same timing in synchronism with a clock skew signal, and a plurality of outputs output from the signal holding means A plurality of decoding means for decoding a signal and outputting a predetermined signal respectively, wherein a signal delay for equalizing a delay time of each signal transmitted from the plurality of second input means to the signal holding means is provided. An adjustment means is provided.

A synchronous DRA whose operation is synchronized in accordance with a clock signal supplied from an external terminal
M, each signal transmitted from the second input means to the signal holding means is a mode control signal for designating an operation mode of the DRAM.

Furthermore, the signal delay adjustment means, said double
Transmitted from the second input means to the signal holding means
Mode control signal equal delay time of each signal,
The internal clock skew of the output of the first input means
Signals and the internal clock delay skew signal, at timings when the signals are read from the plurality of second input means to the signal holding means in synchronization with the internal clock skew signal, respectively. The wiring lengths of the signal lines transmitting these signals or the respective delay times may be adjusted so that the timings of changing from invalid data to valid data coincide with each other.

[0035] Furthermore, the signal delay adjustment means, wherein all of the flip-flops used in the signal holding means is Matomera are in arranged in one block.

Further, the mode control signal output based on the operation result of the signal delay adjusting means is output to the internal clock.
By reading in synchronism with the click-skew signal, the effective set-up time and the internal clock skew change timing to the data from the point of matching respectively to read timing of the mode control signal from the internal clock skew signal The valid data changes to invalid data from the read timing by the signal .
It is also possible to make the internal window width, whose hold time is up to a certain timing, equal to the external window width when supplied from an external terminal.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor memory device of the present invention, an internal window width equal to an external window width can be obtained in a command control signal, so that a setup time and a hold time are reduced.

First, an embodiment of the semiconductor memory device of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment. Referring to FIG. 1, semiconductor memory device 100 has an external clock signal CLK input terminal 2
1 has an enable terminal for controlling whether or not to output an input clock signal, similarly to the above-mentioned conventional example, and has an output terminal connected to a cascade-connected drive buffer. The first drive buffer N1 of N1 and N2 are connected to the delay circuit 7, respectively.

The driving buffer N2 outputs an internal clock signal.
Output the signal ICLK,This signal is internal to a predetermined internal circuit.
Provided as clock skew signals ICLK1,2,.
Paid,The output terminal of the delay circuit 7 is
Connected to the first buffer N5 of the
The driving buffer N6 outputs the internal clock delay signal ICLKD.
outputThis signal is internally delayed by a predetermined internal circuit.
Supplied as skew signals ICLKD1, 2,.
You.

The input buffer circuit 2 is connected to the clock enable signal CKE input terminal 22, the output terminal of which is connected to the leading drive buffer N3 of the cascade-connected drive buffers N3 and N4, and the output terminal of the drive buffer N4. It outputs the internal clock enable signal ICKE and is also connected to the enable terminal of the input buffer circuit 1.

Input terminal 2 for chip select signal CSB
3 is connected to an input buffer circuit 3 whose output terminal is connected to an internal clock skew signal ICLK1 via an output line B1.
Is supplied to the first input terminal of the DF / F circuit 8 to which the signal is supplied.

The input buffer circuit 4 is connected to the input terminal 24 of the row address strobe signal RAS, and the output terminal thereof is connected to the second input terminal of the DF / F circuit 8 via the output line B2. . The output line B1 is, for example, the output line B1.
Is assumed to have the largest signal delay, this signal line B1
The output line B2 is extended to a predetermined length so as to have the same delay time as described above, and is bent down as appropriate to be wired.

Column address strobe signal CAS
Is connected to an input terminal 25 of the DF / F circuit 10 via an output line B3.
Is connected to the input terminal of This output line B3 is also connected to the signal line B1.
The output line B3 is extended to a predetermined length so as to have the same delay time as that described above, and is bent downward as needed.

Input terminal 2 for write enable signal WE
The input buffer circuit 6 is connected to an input buffer circuit 6 whose output terminal is connected to a fourth input terminal of the DF / F circuit 8 via an output line B4. The output line B3 is also extended by a predetermined length and bent as appropriate so that the output line B3 has the same delay time as the signal line B1, and is wired as appropriate. In this figure, it is assumed that the output line B3 has the same wiring length as the output line B1. Is shown.

Although the above-described wiring lengths are bent to adjust the respective delay time lengths, they may be adjusted by inserting an element such as an inverter.

Mode control in which these delay times are adjusted
The output lines D1 to D4 of the DF / F circuit 8 to which the signals B1 to B4 are connected are connected to corresponding input terminals of the command decode circuits 9 and 10, respectively.

The output terminal of the command decode circuit 9 is connected via a decode output line C1 to a latch circuit 11 to which an internal clock delay skew signal ICLKD1 is supplied.
The operation mode determination signal MODE1 is output from the latch circuit 11.
Is supplied to the internal circuit.

The output terminal of the command decode circuit 10 is connected via a decode output line C2 to a latch circuit 12 to which an internal clock delay signal skew ICLKD2 is supplied.
E2 is supplied to the internal circuit.

Referring to FIG. 3 showing a circuit diagram of the DF / F circuit 8, the DF / F circuit 8 has an input terminal 31 to which the output line B1 of the input buffer circuit 3 is connected. It is connected to the input terminal of the master side latch unit ML1 via the buffers N7 and N8 and the transfer gate CS1. Its output terminal is connected to the input terminal of the slave side latch unit SL1 via the transfer gate CS2, and its output terminal is connected to the output line D1 via the terminal.

Similarly, internal drive buffers N9 and N10
, Transfer gate CS3 and master latch circuit M
L2, the transfer gate CS4, and the slave side latch unit SL2 are inserted between the terminals 32 and 37 in a cascade connection state.

The internal drive buffers N11 and N12 and the transfer gate CS are connected between the terminals 33 and 38.
5, the master side latch circuit section ML3, the transfer gate CS6 and the slave side latch section SL3 are inserted in a cascade connection state.

Internal drive buffers N13 and N14 and transfer gate CS are connected between terminals 34 and 39.
7, the master side latch circuit section ML4, the transfer gate CS8 and the slave side latch section SL4 are inserted in a cascade connection state.

The transfer gates CS1 to CS8 are all composed of a combination of a P-channel transistor and an N-channel transfer gate, and the gate electrodes of the master-side P-channel transistor and the slave-side N-channel transistor have an internal clock skew signal ICLK.
1 is connected via clock driving buffers N15 and N16, and an internal clock internal clock skew signal ICLK1 is supplied to the gate electrodes of the master-side N-channel transistor and the slave-side P-channel transistor via the clock driving buffer N17. Connected.

The DF / F circuit 8 is, for example, as described above, in order to make the signal propagation times from the outputs of the input buffer circuits 3 to 6 to the output of the DF / F circuit 8 equal to each other. One latch circuit and one clock drive buffer
Are aggregated into one block.

On the other hand, referring to FIG. 4 showing a circuit diagram of latch circuits 11 and 12, these latch circuits 11 and 12 have the same configuration, and a terminal to which an output signal of command decode circuit 9 is supplied. Transfer gate CS9, inverter 59 and internal drive buffer N20 are inserted in a cascade connection between 56 and output terminal 57,
The output terminal of inverter 59 is connected to the input terminal of transistor 59 via inverter 60 and transfer gate CS10, and the internal clock delay skew signal I is applied to the gate electrodes of the P-channel transistor of transfer gate CS9 and the N-channel transistor of CS10.
CLKD1 is the clock drive buffer N18 and N19.
The internal clock delay skew signal ICLKD1 is connected to the gate electrodes of the N-channel transistor of the transfer gate CS9 and the P-channel transistor of the CS10 via the clock driving buffer N18.

Command decode circuits 9 and 10 are connected to output line D1 of DF / F circuit 8 according to the table shown in FIG.
D4 is a circuit for appropriately selecting one signal from the signals of information D1 to D4. For example, when the signals of the output lines D1 to D4 of the DF / F circuit 8 are "1111", C1 is selected and output.
When the signal of D4 is "1110", C2 is selectively output. These bits are weighted according to a control signal designating an operation mode, that is, a relationship between each command control signal and the operation mode determination signals MODE1, 2,.

The operation of the above-described semiconductor memory device 100 is as follows.
First, the external clock signal CLK is applied to the input buffer circuit 1
Through the internal clock enable signal I
Activated by CKE. CSB, RASB, CAS
The B and WEB command control signals are fetched through the input buffer circuits 3 to 6. Input buffer circuits 3-6
As described above, the wiring length from to the DF / F circuit 8 is made equal, and is read into the DF / F circuit 8 in synchronization with the rising edge of the internal clock signal ICLK and held. You.

Further, the output lines D1 to D of the DF / F circuit 8
The signal on 4 is supplied to command decode circuits 9 and 10, respectively. The outputs of command decode circuits 9 and 10 are selected and output on output lines C1 and C2 according to the table of FIG. The signals on the selected output lines C1 and C2 are latched in synchronization with the rising edges of internal clock delay skew signals ICLKD1 and ICLKD2, respectively, which are delayed by a predetermined time from internal clock signal ICLK by delay circuit 7. And 12 respectively, and output operation mode determination signals MODE1 and MODE2.

Referring to FIG. 2 showing a timing chart in the above-described command decoding method, it is assumed that the external clock signal CLK is made valid while the clock enable signal CKE is at H level. Tip ・
Select signal CSB, row address strobe signal RASB, column address strobe signal CAS
B. The command control signals of the write enable signal WEB are supplied with their timings adjusted in advance so as to have a setup time (tSE) and a hold time (tHE) with respect to the external clock signal CLK. This is the same as the conventional example.

First, output lines B1 to B4 for each command control signal
Are set so that the time required for the command control signal to pass through the input buffer circuits 3 to 6 and the signal wiring length from the input buffer circuits 3 to 6 to the DF / F circuit 8 are equal to each other. The data changes from invalid data to valid data with a delay (t1) of the delay time caused by the adjusted wiring length. Thereafter, these signals changed to valid data are read and held by the DF / F circuit 8 in synchronization with the rising edge of the internal clock signal ICLK. However, since the internal clock signal ICLK has a skew as described above, the internal clock signal ICLK is
The internal clock skew signal ICLK1 is distinguished.

[0061] Thus, the command control signal supplied from the outside, after being aligned such that the delay time is equal, and collectively in synchronization with the internal clock skew signal ICLK1 by D-F / F circuit 8 As read and retained, the inner window width is equal to the outer window width. That is, tSE + tHE = tSI + tHI.........

Next, command decode circuits 9 and 10
The signals on the output lines C1 and C2 are divided by the signal propagation delay caused by the wiring length from the DF / F circuit 8 to the command decode circuits 9 and 10, and each command decode circuit 9
And 10 (t11 and t12) delayed by the time passed.

These changes depend on the internal clock signal ICL
K is latched by latch circuits 11 and 12 in synchronization with the rising edge of internal clock delay signal ICLKD delayed by delay circuit 7 from K, and operation mode determination signals MODE1 and MODE2 are output.

Since internal clock delay signal ICLKD has a skew similarly to internal clock signal ICLK, these internal clock delay signals ICLKD are described as internal clock delay skew signals ICLKD1 and ICLKD1.

The delay time of the delay circuit 7 is such that the internal clock delay skew signal ICL waits for a time t21 when the change of the signals on the output lines C1 and C2 is determined from the rising timing of the internal clock signal ICLK.
KD1 and KD2 are set to rise.

Therefore, in the semiconductor memory device of the present invention, since the internal window width equal to the external window width is obtained in the command control signal, the setup time and the hold time are reduced.

[0067]

As described above, in the semiconductor memory device according to the present invention, at the timing when the command control signal supplied from the outside is read into the DF / F circuit in synchronization with the internal clock signal, respectively. The wiring lengths or the respective delay times of the signal lines transmitting these signals are adjusted so that the change timings of these signals to valid data are respectively matched, and the DF / Since all the F circuits are arranged in one block, an internal window width equal to the external window width is obtained.
A highly reliable semiconductor memory device capable of shortening a setup time and a hold time and capable of stably inputting a command even in a high-frequency operation is provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a timing chart for explaining the operation of the block in FIG. 1;

FIG. 3 is a circuit diagram illustrating an example of a DF / F circuit applied to the block of FIG. 1;

FIG. 4 is a circuit diagram showing an example of a latch circuit applied to the block of FIG. 1;

FIG. 5 is a table showing a decoding state of a command decoding circuit applied to the block of FIG. 1;

FIG. 6 is a block diagram illustrating an example of a conventional semiconductor memory device.

FIG. 7 is a timing chart for explaining the operation of the block in FIG. 7;

FIG. 8 is a block diagram showing another example of a conventional semiconductor memory device.

FIG. 9 is a timing chart for explaining the operation of the block in FIG. 8;

[Explanation of symbols]

 1-6 Input buffer circuit 7 Delay circuit 8,8a-8d DF / F circuit 9,10 Command decode circuit 11,12 Latch circuit 21-26,31-35,40,42 Input terminal 36-39,56 To 58 output terminals 40 to 55, 59, 60 inverters A1 to A4 output lines of input buffer circuits 1 to 6 B1 to B4 input buffer circuit 3 whose wiring length is adjusted
~ 6Mode control signal  C1-2 Output line of command decode circuit CS1-CS10 Transfer gate CLK External clock signal CKE Clock enable signal CSB Chip select signal CASB Column address strobe signal D1-D4 DF / F integrated into one block circuit
8 output lines ICLK internal clock signals ICLK1 to ICLK4Internal clock skew signal
issue ICLKD Internal clock delay signal ICLKD1, Internal clock delay skew signal N1 to N20 Internal drive buffer RASB Row address strobe signal WEB Write enable signal

Claims (5)

(57) [Claims] A first input means for receiving a clock signal supplied from an external terminal and supplying the clock signal to an internal circuit as an internal clock skew signal and an internal clock delay skew signal; and a predetermined control signal from a plurality of external terminals. And the output signals output from the plurality of second input means in synchronization with the internal clock skew signal output from the first input means, respectively. A signal holding means for latching and holding at the timing of: and a plurality of decoding means for decoding a plurality of output signals output from the signal holding means and respectively outputting predetermined predetermined signals; A signal delay adjusting means for equalizing a delay time of each signal transmitted from the second input means to the signal holding means. Semiconductor storage device. 2. A synchronous DRAM whose operation is synchronized in accordance with a clock signal supplied from an external terminal, wherein each signal transmitted from said second input means to said signal holding means is said DRAM. 2. The semiconductor device according to claim 1, wherein the mode control signal is a mode control signal for designating the operation mode. 3. The signal delay adjusting unit according to claim 1, wherein the mode control signal that equalizes the delay time of each signal transmitted from the plurality of second input units to the signal holding unit is output from the first input unit. Out of the internal clock skew signal and the internal clock delay skew signal, the signals are read from the plurality of second input means to the signal holding means in synchronization with the internal clock skew signal. 2. The semiconductor memory device according to claim 1, wherein the lengths of the signal lines for transmitting these signals or the respective delay times are adjusted so that the timings of change from invalid data to valid data coincide with each other. 4. The semiconductor device according to claim 3, wherein in said signal delay adjusting means, all of the flip-flops used for said signal holding means are arranged in one block. Wherein said signal delay the said mode control signal output based on the operation result of the adjustment means internal clock
By reading in synchronism with the skew signal, by the effective change timing to data from said time that matches each internal clock setup time by skew signal to read timing of the mode control signal and the internal clock skew signal The external window width when supplied from an external terminal is made equal to an internal window width which is a hold time from a read timing to a timing when the valid data changes to invalid data. Semiconductor storage device.