JP2871139B2 - Image data encoding device and decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding device and a decoding device for performing high-compression encoding of image data.

[0002]

2. Description of the Related Art When an image signal is stored as digital data in a storage device such as a memory card, a magnetic disk, or a magnetic tape, or when an image signal is transmitted and received by an image communication device, the amount of data is increased. In order to record or transmit / receive many frame images within a limited storage capacity, some efficient compression must be applied to the data of the obtained image signals. Need to be done.

Further, in a digital electronic still camera or the like, the time required for recording and reproducing data must be short. In addition, digital VTR (video tape recorder)
The same applies when a moving image is recorded in a digital moving image file or the like. That is, even for a still image,
Even for moving images, it is necessary that the time required for data recording / reproducing processing be short.

As a highly efficient image data compression method, an encoding method combining orthogonal transform encoding and variable length encoding is widely known. As a typical example, there is a method being studied in international standardization of still image coding.
The outline of this method will be described below.

First, image data is divided into blocks of a predetermined size, and two-dimensional DCT (discrete cosine transform) is performed for each of the divided blocks as an orthogonal transform. Next, linear quantization according to each frequency component is performed, and Huffman coding is performed on the quantized value as variable length coding.
At this time, the difference value between the DC component and the DC component of the neighboring block is Huffman-coded. The AC component scans from a low frequency component to a high frequency component, called a zigzag scan, and performs two-dimensional Huffman coding from the continuous number of invalid (value 0) components and the value of the valid components that follow. .

The above operation will be described in detail with reference to FIG. 8. First, as shown in FIG. 8A, image data of one frame is converted into a block of a predetermined size (for example, 8 × 8) into blocks A, B, C,...
As shown in (2), a two-dimensional DCT (discrete cosine transform) is performed as an orthogonal transform for each of the divided blocks.
The data is sequentially stored on a × 8 matrix.

When viewing image data on a two-dimensional plane,
It has a spatial frequency which is frequency information based on the distribution of density information. Therefore, by performing the above DCT,
The image data is converted into a DC component DC and an AC component AC,
On the 8 × 8 matrix, data indicating the value of the DC component DC at the origin position (0, 0 position), and (0, 7)
At the position, data indicating the maximum frequency value of the AC component AC in the horizontal axis direction, at the (7,0) position, data indicating the maximum frequency value of the AC component AC in the vertical axis direction, ,
At the (7, 7) position, data indicating the maximum frequency value of the AC component AC in the oblique direction is stored, and at the intermediate position, the frequency data in the direction related by each coordinate position is stored from the origin side. It is stored in such a form that higher frequency ones appear sequentially.

Next, the data stored at each coordinate position in the matrix is divided by the quantization width for each frequency component, thereby performing linear quantization according to each frequency component (c). Huffman coding is performed on the resulting value as variable length coding. At this time, with respect to the DC component DC, a difference value between the DC component of the neighboring block and the DC component is represented by a group number (the number of additional bits) and additional bits, and the group number is Huffman-coded, and the obtained code word The additional bits are combined to form encoded data (d1, d2, e1, e
2).

[0009] Coefficients that are also valid for the AC component AC (values are not "0") are represented by group numbers and additional bits. Therefore, the AC component AC scans from a low frequency component to a high frequency component called a zigzag scan, and the continuous number of invalid (value is “0”) components (zero run number) and the succeeding valid component Group of values
Then, two-dimensional Huffman coding is performed on the basis of the loop number and the obtained code word and additional bits are combined to obtain coded data.

The Huffman coding is based on the peak of the frequency of occurrence in the data distribution of each of the DC component AC and the AC component AC per frame image. This is performed by encoding the data in a form in which bits are allocated so that the number of bits is increased in the vicinity and the number of bits is increased toward the periphery to obtain a code word. The above is the basic part of this method.

With only the basic part, the code amount is not constant for each image because Huffman coding, which is variable length coding, is used. Then, the present inventors applied the following method as a method of controlling the code amount, as disclosed in Japanese Patent Application No. 2-13 / 1990.
No. 7222.

That is, in a compression method combining orthogonal transform and variable length coding, in order to control the amount of generated codes, an image signal stored in a memory is divided into blocks, and each of the divided blocks is subjected to orthogonal processing. After performing the conversion, this conversion output is quantized with a provisional quantization width,
This quantized output is subjected to variable-length encoding, the generated code amount for each block and the total generated code amount of the entire image are calculated, and then the provisional quantization width, the total generated code amount, and the purpose and A new quantization width is predicted from the total code amount to be performed (first pass). Then, the image signal of the image memory is subjected to block division, orthogonal transform, quantization, and variable length encoding using the new quantization width, and the generated code amount and the total generated code amount for each block in the first pass are performed. Calculate the allocated code amount for each block from the target total code amount, and if the generated code amount of each block exceeds the allocated code amount of each block, terminate variable-length coding on the way. Is repeated (second pass). Thus, the code amount is controlled so that the total generated code amount of the entire image does not exceed the target set code amount.

[0013]

As described above, in applications such as image recording and transmission / reception,
It is desired that image data can be compressed with high efficiency.
There is the above-mentioned international standard scheme as a compression scheme that satisfies such demands. In this scheme, a technique that combines orthogonal transformation and variable length coding for each block as shown in the example shows high compression of image data. Although it can be performed efficiently, there is a drawback that the processing time is long because the compression processing procedure is complicated. In general, the processing time for data compression is proportional to the number of elements in an image. Therefore, the method proposed in Japanese Patent Application No. 2-137222 for obtaining a particularly high resolution requires a very large code amount. However, since two passes are used for encoding, there is a disadvantage that the processing time is further increased. In an image recording apparatus or a transmission apparatus, the processing time of data compression needs to be as short as possible from the viewpoint of operability and power consumption.

Accordingly, the present invention has been made in view of such a problem, and an object of the present invention is to encode a large amount of image data in a short processing time by performing parallel processing. An object of the present invention is to provide an encoding device and a decoding device for image data which can be used.

[0015]

In order to solve the above-mentioned problems, an encoding apparatus according to a first configuration of the present invention comprises: a plurality of blocking circuits for dividing image data into blocks;
A plurality of orthogonal transform circuits for performing orthogonal transform on each of the divided blocks; a plurality of quantizers for quantizing the orthogonal transform output for each frequency component; and a plurality of variable circuits for performing variable-length encoding on the quantized output. A long encoding circuit, a buffer circuit for arranging the outputs of the plurality of variable length encoding circuits into a series of bit strings, and an output circuit for outputting the output of the buffer circuit for each byte.

The encoding apparatus according to the second configuration of the present invention comprises a plurality of blocking circuits for dividing image data into blocks, and a plurality of orthogonal transforms for performing an orthogonal transform for each of the divided blocks. Circuit, a plurality of quantization circuits for quantizing the orthogonal transform output for each frequency component, a plurality of variable-length encoding circuits for variable-length encoding the quantized output, and a code amount generated in the encoding. A plurality of code amount calculation circuits, a quantization width prediction circuit for predicting an optimum quantization width from the code amounts calculated by the plurality of code amount calculation circuits, and an output of the plurality of variable length coding circuits. And an output circuit that outputs the output of the buffer circuit for each byte.

Further, a decoding device according to a third configuration of the present invention comprises a plurality of variable length code decoding circuits for decoding quantized values of DC components and AC components which have been subjected to variable length coding, and A plurality of inverse quantization circuits for inversely quantizing the obtained DC component and AC component, and a block determination circuit for obtaining a block to be inversely quantized by each inverse quantization circuit from the decoded DC component and AC component, A plurality of inverse orthogonal transform means for performing an inverse orthogonal transform on the inversely quantized DC component and AC component for each block.

[0018]

According to the present invention, up to variable-length coding of image data is processed in parallel by a plurality of coding circuits, and the obtained data is output in a predetermined format. The processing speed is improved, and the encoding is performed in two passes, so that the data can be kept within a fixed code amount. Further, since the processing after the inverse quantization is processed in parallel by a plurality of decoding circuits, the processing speed in decoding can be improved.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the basic concept of the present invention will be described. The basic idea of the present invention is to improve the processing speed by combining a plurality of encoding devices that function independently and operating them in parallel. For example, the encoding circuits may be configured as an integrated circuit (IC), and the number of encoding circuits may be appropriately used depending on the configuration of a device that requires the encoding device. A small-scale device that gives priority to low cost uses only one coding circuit, and a large-scale device or a device that emphasizes performance uses many coding circuit ICs.

When a plurality of encoding circuits are used, the following problems arise. In other words, in the compression method proposed by the international standard, variable-length codes for quantized DC or AC components are sequentially arranged without any gaps, and are re-separated every 8 bits (1 byte) to encode data. And
That is, variable-length codes are arranged without gaps in the separated bytes, and some of them are divided and incorporated into the next byte (see FIG. 4A).

On the other hand, if the divided images are each encoded by a plurality of encoding circuits, and the output data for each byte are simply connected together, the byte delimiter does not coincide with the end of the code. In this case, extra bits are generated as shown in FIG. If it is left as it is, an extra bit string is interpreted as an incorrect code at the time of decoding, and normal encoding cannot be performed. Further, in the compression method proposed by the international standard, a special code for separating encoded data is inserted as means for enabling such division.
However, the special sign to indicate this break is
This is a redundant code that is not directly related to the image. In addition, in order to make the existence of this special code recognizable, the data needs to be delimited in units of bytes, so that more redundant codes must be used.

In the present invention, in consideration of the above points, the encoded data output from each encoding circuit is output as a serial bit string, and after connecting these, a delimiter for each byte is performed. As a result, the correct code data without waste is obtained.
Data can be obtained by parallel processing.

The first embodiment of the present invention will be described below with reference to the drawings. This embodiment is an example of parallel processing by two sets of encoding circuits, and FIG. 1 shows a circuit configuration diagram for implementing this. In the figure, the encoding device of the present invention comprises an image memory 1 constituted by a random access memory RAM, an encoding circuit 2, an encoding circuit 3, a code memory 4, a code memory 5, and a code output circuit 6. The encoding circuit 2 is DC
A T circuit 21, a quantization circuit 22, and a Huffman coding circuit 23 are provided. The coding circuit 3 has the same configuration as the coding circuit 2 and includes a DCT 31, a quantization circuit 32, and a Huffman coding circuit 33. The code memories 4 and 5 are constituted by fast-in first-out (FIFO) memories.

Next, the operation timing at the time of encoding will be described with reference to FIG. The image memory 1 is divided into areas A and B, and areas corresponding to the left half A and the right half B of the divided image shown in FIG. 3 are recorded. These memory areas are configured so that signals can be read out independently of each other.

At the start of encoding, area A in image memory 1
, The signal A1 of the first to eighth lines and the signal B1 of the same first to eighth lines are read from the area B, and are input to the encoding circuits 2 and 3, respectively. At this time, the signal is sequentially read out for each block of 8 × 8 pixels by the memory address control at the time of reading.

The read signal A1 is converted by the DCT circuit 21 into DCT coefficients. The converted coefficients are linearly quantized in a quantization circuit 22 by a quantization width determined for each corresponding frequency component. The quantized value is next input to the Huffman encoding circuit 23. Here, as for the DC component, the difference value of the DC component of the previous block is represented by a group number and additional bits, and the group number is Huffman-coded. The AC component is subjected to zigzag scanning, and two-dimensional Huffman coding is performed from the continuous number of invalid components (zero run) and the group number of the value of the valid component that follows. The code word and additional bits obtained for both the DC and AC components are combined to form encoded data. The obtained encoded data is written from the encoding circuit 2 to the code memory 4 in a bit unit as a continuous serial signal. here
An end-of-block (EOB) code is added to a block in which the 64th (AC maximum frequency) coefficient value does not exist.

On the other hand, the encoding circuit 3
In the DCT circuit 31,
Data obtained by encoding in the quantization circuit 32 and the Huffman encoding circuit 33 is written in the code memory 5.

The data recorded in the code memories 4 and 5 are read into the code output circuit 6. At this time, the reading is performed alternately, and the reading of the code memory 4 is performed first. After this reading is completed, the code memory 5 is read. In the code output circuit 6, these coded data are connected and processed as a series of bit strings. That is, the data is sequentially divided every 8 bits (1 byte), and if necessary, a marker code (control code) is inserted, bit stuffing (bit 1 is placed at the remaining position) and byte stuffing ( When a certain byte becomes "FF", "00" is inserted next), and the data is output as coded data.

At this time, in the code output circuit 6, the code related to the DC component at the boundary between the area A and the area B is replaced with the code corresponding to the difference value between the DC component of the previous block and the difference from 0. As can be seen from FIG.
While the coded data is waiting to be read from the code memory 5, the signal of the signal A2 (9th to 16th lines in the area A) is read out from the image memory 1 in block order, and the coding circuit 2 And the encoding process as described above is performed. The encoded data of A2 is written as the encoding memory 4 becomes available. Similarly, the encoding of the signal B2 is also processed in the encoding circuit 3 as the encoding memory 5 becomes available, and data is written to the encoding memory 5. As described above, the encoding processing of the signals of the areas A and B is sequentially performed in parallel, and a large amount of data can be efficiently processed at high speed.
Data is encoded.

Next, a second embodiment of the present invention will be described. In this embodiment, the code amount control is performed in addition to the parallel processing as shown in the first embodiment. In addition, a code decoding process will be described.

FIG. 5 shows a configuration diagram of an encoding (decoding) device in this embodiment. Here, 1 is an image memory, 4 and 5 are code memories, and 6 is a code output circuit, which have the same functions as those in the previous embodiment with the same numbers.
Reference numerals 7 and 8 denote encoding (decoding) circuits, respectively, and reference numeral 9 denotes a control circuit. The encoding circuits 7 and 8 respectively include a DCT circuit 71, 81, a quantization circuit 72, 82, a Huffman encoding circuit 73,
83, truncation circuits 74 and 87, Huffman decoding circuits 75 and 85, block counting circuits 76 and 86, inverse quantization circuits 77 and 84, IDCT
(Inverse DCT) circuits 78 and 88 are provided.

The encoding operation timing in the above configuration will be described with reference to FIG. First, in the first pass, signals in the A region and the B region are simultaneously read sequentially from the image memory 1 for each block and input to the encoding circuits 7 and 8 shown in FIG. The input signal A1 is converted by the DCT circuit 71 into DCT coefficients. The converted coefficient is quantized by the quantization circuit 72 with a provisional quantization width. The quantized value is then converted to a Huffman coding circuit.
The DC component and the AC component are input to 73 and Huffman coding is performed. The value of the code amount for each block generated here is obtained and output to the control circuit 9.

The control circuit 9 determines the code amount for each block and the code amount for each block and stores them. On the other hand, the encoding circuit 8 performs exactly the same processing on the signal B1. The code amount for each block obtained as a result is output to the control circuit 9, and the code amount for each block and the total code amount are stored. Here, the values of both A and B are summed as the total code amount. The above operation is sequentially performed in parallel with the signals A2, B2, A3, B3. When the above processing is completed for all the images, the control circuit 9 predicts the optimum value of the quantization width from the obtained total code amount and the target code amount value. That is, since there is a statistically strong correlation between the quantization width and the code amount, the quantization width is corrected based on the statistical correlation to bring the code amount closer to the target value. The obtained correction coefficient for the quantization width is output from the control circuit 9 to the encoding circuits 7 and 8.

Subsequently, a second pass of encoding is performed. The signal A1 is read again from the image memory 1 and input to the encoding circuit 7. The input signal is converted by the DCT circuit 71 into DCT coefficients. The converted coefficient is linearly quantized by the quantization circuit 72. At this time, the quantization width corrected by the correction coefficient given from the control circuit 9 is used. The quantized DCT coefficients are input to the Huffman coding circuit 73. Here, the difference between the DC component of the previous block and the DC number is represented by a group number and additional bits, and the group number is Huffman coded. The AC component is subjected to a zigzag scan, and the group numbers of the zero run value and the effective component value are subjected to two-dimensional Huffman coding. The obtained encoded data, together with the additional bits, is input to a code truncation circuit 74, which controls the code amount allocated to the block. Here, the code amount allocated to the block is obtained by multiplying the ratio of the target code amount to the total code amount in the first pass by the stored code amount generated in the block in the first pass in the control circuit 9. Required by The obtained block allocation code amount is supplied to the code truncation circuit 74, and is compared with the code amount of the coded data of the block. If the actual code amount is within the allocated code amount, the encoded data is output to the code memory 4 with the EOB code added as it is. However, if the 64th coefficient value is not 0, EOB is excluded.

On the other hand, when the actual code amount exceeds the allocated code amount, the high-frequency component is truncated so that the code amount falls within the allocated amount. That is, the encoded data (Huffman code and additional bits) up to the allocated code amount is output to the code memory 4 and the EOB is added. Subsequent encoded data is discarded without being output.

While the above operation is being performed, exactly the same encoding operation is performed on the signal B 1 in the encoding circuit 8, and the encoded data is written into the code memory 5. The signals from the code memories 4 and 5 are read out in the same manner as described in the first embodiment.
Reading of 1 has priority. Then B
, A2, B2,...
The data is read out, and processing such as insertion of a marker code, bit stuffing, byte stuffing, etc. is performed to obtain final encoded data. At this time, as in the first embodiment, in the code output circuit 6, the code related to the DC component at the boundary between the area A and the area B is the code corresponding to the difference value between the difference from 0 and the DC component of the previous block. Is replaced by

As described above, even when the code amount control including two passes is performed, the first pass is performed completely in parallel, and the second pass is sequentially performed in parallel after waiting for the reading of the code memories 4 and 5. The encoding can be performed at high speed.

It should be noted that the coding circuit 7,
8, of course, by stopping the function of encoding truncation,
The operation in which the code amount control is not performed as shown in the first embodiment can be used without any problem.

Next, the decoding operation in the encoding (decoding) apparatus of FIG. 5 will be described with reference to FIG. The input encoded data is simultaneously output to the Huffman decoding circuits 75 and 85.
Is input to In the decoding circuit 7, the Huffman decoding circuit 75
In the Huffman code, decoding of the Huffman code is performed sequentially from the beginning of the data, and the difference value and AC component of the quantized DC component,
Further, by the EOB code or the non-zero 64th coefficient value,
End of block can be detected. Here, each time the end of the block appears, the number of blocks is counted in the block counting circuit 76, and the number of the decoded data from the beginning is determined. Here, in accordance with the image division shown in FIG.
Only the data is sent to the subsequent inverse quantization circuit 77. Here, restoration of the DC component and inverse quantization (conversion to a representative value) of the DC and AC components are performed. The representative value is further sent to the IDCT circuit 78, converted into an image signal, and written into the area A of the image memory 1. The data corresponding to the area B is discarded thereafter without being sent to the inverse quantization circuit 77. Therefore, the processing for the data in the area B is only decoding of the Huffman code,
Thereafter, the processing time can be shortened as compared with the case where inverse quantization and IDCT are performed.

On the other hand, in the decoding circuit 8, Huffman decoding is similarly performed in the Huffman decoding circuit 85, and only data corresponding to the area B is counted and selected by the block counting circuit 86. Thereafter, DC component restoration and representative value conversion in the inverse quantization circuit 87 and conversion in the IDCT circuit 88 are performed.
The data is written to the area B of the image memory 1. When the above process is performed for all screens, the decoding processing for all screens ends. As described above, by performing the decoding processing in parallel also at the time of decoding, the processing can be performed at high speed.

As described above, the present invention has a remarkable effect of improving the speed of image data compression processing by combining a plurality of encoding circuits and operating them in parallel.

In the embodiment, the parallel operation of two sets of encoding circuits has been described. However, the present invention is not limited to this, and three or more encoding circuits may be operated in parallel according to the principle of the present invention. Is possible. The orthogonal transform may be a Fourier transform, an Hadamard transform, or the like, in addition to the DCT. As the variable-length coding, arithmetic coding other than Huffman coding may be used.

[0043]

As described in detail above, according to the present invention, an image data encoding apparatus and decoding apparatus capable of encoding a large amount of image data in a short processing time. An apparatus can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an encoding device according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the encoding device shown in FIG. 1;

FIG. 3 is a diagram showing an array of image data to be encoded.

FIGS. 4A and 4B are diagrams showing a configuration of code data.

FIG. 5 is a circuit configuration diagram of an encoding / decoding device according to a second embodiment of the present invention.

FIG. 6 is an operation timing chart of the encoding device shown in FIG. 5;

FIG. 7 is an operation timing chart at the time of decoding by the decoding device shown in FIG. 5;

FIG. 8 is an operation transition diagram of a conventional compression method.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 image memory, 2 3 coding circuit, 4 5 code memory, 6 code output circuit, 7 coding (decoding) circuit,
21, 31,... DCT, 22, 32, quantization circuit, 23,
33 ... Huffman coding circuit.

Claims (3)

(57) [Claims] A plurality of block circuits for dividing image data into blocks; a plurality of orthogonal transform circuits for performing orthogonal transform on each of the divided blocks; and a quantization of the orthogonal transform output for each frequency component A plurality of quantization circuits for performing variable length coding on the quantized output; a buffer circuit for arranging the outputs of the plurality of variable length coding circuits into a series of bit strings; And an output circuit for outputting the output of the image data for each byte. 2. A plurality of block circuits for dividing image data into blocks, a plurality of orthogonal transform circuits for performing orthogonal transform for each of the divided blocks, and a quantization of the orthogonal transform output for each frequency component A plurality of quantization circuits for performing variable length coding on the quantized output; a plurality of code amount calculation circuits for calculating the amount of code generated in the coding; and a plurality of code amounts A quantization width prediction circuit for predicting an optimal quantization width from the code amount calculated by the calculation circuit; a buffer circuit for arranging outputs of the plurality of variable length coding circuits into a series of bit strings; and an output of the buffer circuit. And an output circuit for outputting the image data for each byte. 3. A plurality of variable-length code decoding circuits for decoding quantized values of variable-length-coded DC components and AC components, and a plurality of variable-length code decoding circuits for inversely quantizing the decoded DC components and AC components. An inverse quantization circuit, a block determination circuit for obtaining a block to be inversely quantized by each inverse quantization circuit from the decoded DC component and AC component, and a block for the inversely quantized DC component and AC component for each block. An image data decoding apparatus comprising a plurality of inverse orthogonal transform means for performing an inverse orthogonal transform.