JP2853736B2 - Cluster number conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel type information processing apparatus having a cluster configuration, and more particularly to a cluster number conversion circuit for converting a logical cluster number into a physical cluster number.

[0002]

2. Description of the Related Art In a parallel type information processing apparatus having a cluster configuration as shown in FIG. 4, a processor element (hereinafter abbreviated as PE) in the apparatus is designated by a cluster number and a PE number. As software of the parallel type information processing apparatus, there is a demand to determine a cluster number that can be handled irrespective of the number of physical clusters in order to reduce a change due to a difference between apparatuses. There has been a request that PEs belonging to different clusters, such as / cluster 10 (7) PE7, be treated as if they belong to the same cluster.

[0003] Therefore, the cluster number is distinguished into a logical cluster number seen from software and a physical cluster number indicating an actual cluster, and a physical cluster number to which the PE belongs is determined from the logical cluster number and the PE number. A conversion table is prepared in each cluster control device. Further, in software, an operating system (hereinafter abbreviated as OS) has a demand to change the appearance of a cluster from an application program in order to manage the entire system. Therefore, different logical cluster numbers are used for the OS and the application program. You are using

Therefore, conventionally, a cluster number conversion circuit as shown in FIG. 3 has been used. The operation of the conventional cluster number conversion circuit will be described with reference to the drawings. FIG. 3 shows a cluster number conversion circuit of the parallel type information processing apparatus having the configuration of FIG. In FIG. 3, 1 is a PE number register, 2
Is a logical cluster number register, and 8 is a conversion table memory.

For this cluster number conversion circuit, the OS uses "0" to "15" as the logical cluster number, and the application program uses "16" to "31" as the logical cluster number.
The PE number is "0" for both OS and application
To "15". Therefore, the logical cluster number is 5
The PE number is represented by 4 bits.

First, a logical cluster number and a PE number to be converted are given to a cluster number register 2 and a PE number register 1 from a cluster controller (not shown). Next, the conversion table memory 8 is accessed with a 9-bit signal 302 obtained by combining the output 101 of the PE number register 1 and the output 301 of the cluster number register 2 to obtain a corresponding physical cluster number 303.

[0007]

In the conventional cluster number conversion circuit, since each PE has a conversion entry for the OS and a conversion entry for the application, the capacity of the conversion table memory becomes large. was there.

The problem of the present invention is that since all the PEs in the device can be seen as the OS, the conversion information of each PE is not required.
Focusing on the fact that it is sufficient to know only the relationship between the logical cluster and the physical cluster, the conversion table entry used by the OS is degenerated so that it is determined only by the logical cluster number regardless of the PE number. An object of the present invention is to provide a cluster number conversion circuit that can reduce the capacity of the conversion table memory.

[0009]

According to the present invention, there is provided a cluster number conversion circuit used in a parallel type information processing apparatus having a cluster configuration, comprising: a logical cluster number register;
A processor element number register, a first conversion table memory for outputting a physical cluster number with an address obtained by combining an output of the logical cluster number register and an output of the processor element number register as an address, and an output of the logical cluster number register. A second translation table memory for outputting a physical cluster number as an address;
A physical cluster number selection circuit for selecting an output of the first translation table memory and an output of the second translation table memory according to a value of one or a plurality of bits at a predetermined position of the address logical cluster number; Thus, a cluster number conversion circuit characterized by being configured as described above is obtained.

Further, according to the present invention, there is provided a cluster number conversion circuit, wherein the first conversion table memory is used for an application and the second conversion table memory is used for an operating system.

According to the present invention, the logical cluster number register, the processor element number register, and the output of the processor element number register are determined by the value of one or more bits at a predetermined position of the logical cluster number. A processor element number degeneration circuit for selecting one of predetermined constants; and a conversion table for outputting a physical cluster number as an address using a value obtained by combining the output of the logical cluster number register and the output of the processor element number degeneration circuit. A cluster number conversion circuit characterized by comprising a memory is obtained.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings. Hereinafter, a first embodiment of the present invention will be described with reference to FIG. In the cluster number conversion circuit of FIG. 1, 1 is a processor element number register (hereinafter, referred to as a PE number register), 2 is a logical cluster number register, 3 is a first conversion table memory used for application cluster number conversion, Reference numeral 4 denotes a second conversion table memory used for cluster number conversion for the OS, and reference numeral 5 denotes a physical class number selection circuit. In this embodiment, the OS uses “0” to “15” as the logical cluster number, the application program uses “16” to “31”, and the PE number uses “0” to “15” for both the OS and the application. use.

Therefore, it is assumed that the logical cluster number is represented by 5 bits and the PE number is represented by 4 bits, and whether the logical cluster number is OS or application can be determined by the value of the most significant bit of the logical cluster number.

First, a logical cluster number and a PE number to be converted are given to a logical cluster number register 2 and a PE number register 1 from a cluster controller (not shown). Then, the output 101 of the PE number register 1 and the lower 4 bits 10 of the output of the logical cluster number register 2
The first conversion table memory 3 is accessed with the 8-bit signal 104 obtained by combining the first and third data with the first physical cluster number 105. At the same time, the lower 4 bits 103 of the output of the logical cluster number register 2 access the second conversion table memory 4 to obtain the corresponding second physical cluster number 106. Then, the physical cluster number selection circuit 5
Receives the first physical cluster number 105 and the second physical cluster number 106 as inputs, and registers the logical cluster number register 2
If the value 102 of the most significant bit of the output of “1” is “1”, the cluster number of the application is converted, and if it is “0”, the cluster number of the OS is converted. The output 107 is the physical cluster number 106.

Next, a second embodiment of the present invention will be described with reference to FIG. In the cluster number conversion circuit of FIG. 2, 1 is a PE number register, 2 is a logical cluster number register, 6 is a PE number degeneration circuit, and 7 is a cluster number conversion table memory. In the present embodiment,
The OS uses “0” to “15” as logical cluster numbers, the application program uses “16” to “31”, and the PE numbers are “1” to “1” for both OS and application.
Use “15”. Therefore, also in the present embodiment, the logical cluster number is represented by 5 bits, and the PE number is represented by 4 bits, and it is possible to determine whether the logical cluster number belongs to the OS or the application by the value of the most significant bit of the logical cluster number.

First, a logical cluster number and a PE number to be converted are given to a cluster number register 2 and a PE number register 1 from a cluster control device (not shown). The output 101 of the PE number register 1 is a fixed value "0"
Is supplied to the PE number degeneration circuit 6. If the value of the most significant bit 102 of the output of the cluster number register 2 is “0”, the PE number degenerating circuit 6 outputs 4 bits “0”,
If "1", the output 101 of the PE number register 1 is output. Then, the lower 4 bits 1 of the cluster number register 2
The conversion table memory 7 is accessed with an 8-bit signal 204 obtained by combining the output data 03 and the output 106 of the PE number degeneration circuit 6 to obtain a corresponding physical cluster number 205.

When the OS is operating, since the most significant bit of the cluster number register is "0", the address of the conversion table memory is "0000 ₍₂₎ "-"the lower 4 bits of the logical cluster number". . Therefore, at the time of OS operation, regardless of the PE number given from the cluster control device,
Only the 16 entries from the youngest number in the conversion memory table will be accessed. In the case of an application program, the address of the conversion table memory is “PE number” − “lower 4 bits of logical cluster number” and the PE number is “1” to “15”. ~ 255 entries will be accessed.

In any of the above embodiments,
Whether the logical cluster number is OS or application is determined by the value of the most significant bit of the logical cluster number. Of course, this is determined whether the values of the plurality of bits of the logical cluster number are specific values. Can also be determined.

[0019]

As described above, according to the present invention, the translation table memory is divided into an OS for accessing only by the logical cluster number and an application for accessing by combining the PE number and the logical cluster number. Thus, an effect is obtained that the required capacity of the conversion table memory can be reduced by half as compared with the conventional case.

According to the present invention, the conversion table memory is accessed as if the PE number is "0" regardless of the actual PE number during the OS operation. The effect that the memory capacity can be reduced by half can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing another embodiment of the present invention.

FIG. 3 is a diagram showing a conventional cluster number conversion circuit.

FIG. 4 is a diagram showing an embodiment of a parallel type information processing apparatus having a cluster configuration.

[Explanation of symbols]

 Reference Signs List 1 PE number register 2 Logical cluster number register 3 First conversion table memory 4 Second conversion table memory 5 Physical cluster number selection circuit 6 PE number degeneration circuit 7 Cluster number conversion table memory

Claims (3)

(57) [Claims] 1. A cluster number conversion circuit used in a parallel type information processing device having a cluster configuration, comprising: a logical cluster number register, a processor element number register, an output of the logical cluster number register, and the processor element number register. A first translation table memory for outputting a physical cluster number using a value obtained by combining the outputs of the logical cluster number as an address, a second translation table memory for outputting a physical cluster number using an output of the logical cluster number register as an address, A physical cluster number selection circuit for selecting an output of the first conversion table memory and an output of the second conversion table memory according to a value of one or a plurality of bits at a predetermined position of a number And a cluster number conversion circuit. 2. The cluster number conversion circuit according to claim 1, wherein said first conversion table memory is used for an application, and said second conversion table memory is used for an operating system. 3. An output of the processor element number register and a constant of a predetermined constant according to a value of one or more bits at a predetermined position of a logical cluster number register, a processor element number register, and a predetermined position of the logical cluster number. A processor element number reduction circuit for selecting one of them; and a conversion table memory for outputting a physical cluster number as an address using a value obtained by combining an output of the logical cluster number register and an output of the processor element number reduction circuit. A cluster number conversion circuit, comprising: