JP2836240B2 - Method for manufacturing c-MOS thin film semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a c-MOS type thin film semiconductor device used for driving various devices such as an image sensor and a liquid crystal display, for example, an inverter circuit and the like. The present invention relates to an improvement in a manufacturing method capable of obtaining a c-MOS type thin film semiconductor device which has no variation in noise margin between a LOW input side and a HIGH input side and can be operated with a normal 24V power supply.

[Conventional technology]

This type of c-MOS type thin film semiconductor device is shown in FIGS.
As shown in the figure, a glass substrate (a), and n-MOS type semiconductors (n) and p-type semiconductors provided on the glass substrate (a), respectively.
The n-MOS semiconductor (n) and the p-MOS semiconductor (p) are a thin polysilicon film (b) acting as an active layer, A source electrode (S) / drain electrode (D) provided to be connected to both ends of the silicon film (b), and a gate electrode provided on the polysilicon film (b) via the gate insulating film (c). G) are known to constitute each main part.

When an inverter circuit is constituted by the c-MOS type thin film semiconductor device, as shown in FIG.
The MOS type semiconductor (p) side is connected to a power supply which is a high voltage (V _DD ) side, while the n-MOS type semiconductor (n) side is connected to a low voltage (V _SS =
0) side and negative (LOW input) or positive (HIGH input) to the gate electrode (G) (G) of each semiconductor (p) (n)
The corresponding output voltage (V _OUT ) is obtained by applying the input voltage (V _IN ).

That is, when a negative input voltage (V _IN ) is applied to each of the gate electrodes (G) and (G), a channel is formed only on the p-MOS type semiconductor (p) side and the p-MOS type semiconductor (p) is formed. Is ON
In the state, the n-MOS type semiconductor (n) is in the OFF state, and the output voltage (ie, HIGH output) equal to the power supply voltage (V _DD ).
On the other hand, when a positive input voltage (V _IN ) is applied to the gate electrodes (G) and (G), a channel is formed only on the n-MOS type semiconductor (n) side, and the n-MOS type semiconductor (n ) Is in the ON state, the p-MOS type semiconductor (p) is in the OFF state, and an output voltage (that is, LOW output) equal to the low voltage (V _SS = 0) is obtained. “LOW input → HIGH output”, “HIGH” Input → LOW
The output functioned as an inverter circuit.

FIG. 10 shows the input (V _IN ) and output (V _OUT ) of the c-MOS type thin film semiconductor device applied as the inverter circuit.
Is a graph showing the relationship with V _INV shown in this figure.
Is the inversion voltage of the inverter, V _{TH (p)} is the threshold voltage of the p-MOS type semiconductor (p), V _{TH (n)} is the threshold voltage of the n-MOS type semiconductor (n), Further, these relationships are shown on a graph.

By the way, in recent years, a method of manufacturing a MOS thin film semiconductor device has been developed in which channel mobility is increased by increasing the crystal grain size of a polysilicon film used as an active layer.

That is, in this manufacturing method, as shown in FIG. 11A, inert ions such as silicon are implanted into an amorphous silicon film (b ') formed on a glass substrate (a) by an ion implantation method. Then, after partially destroying the silicon microcrystal nuclei (b ″) existing in the film (b ′) to reduce the residual nucleus density (see FIG. 11B), the amorphous silicon film (b ′) ′) Is heated to about 550 ° C. to 600 ° C., and the crystal is grown using the silicon microcrystal nuclei (b ″) remaining in the film (b ′) as growth nuclei to form a polycrystal as shown in FIG. This is a method of forming a silicon film.

In this method, since the collision between the growth nuclei during the crystal growth is reduced by the smaller number of the growth nuclei, the crystal growth of each growth nucleus is promoted, and it is necessary to obtain a polysilicon film having a large crystal grain size. As a result, in the thin film semiconductor device using the polysilicon film as an active layer, the crystal grains (f) are formed as shown in FIG.
This method can increase channel mobility because carrier scattering at the interface is reduced.

[Problems to be solved by the invention]

By the way, by applying this polysilicon film forming method, c
-When a MOS thin film semiconductor device is manufactured, the channel mobility of the n-MOS semiconductor (n) and the p-MOS semiconductor (p) can be increased, and the threshold of the n-MOS semiconductor (n) can be achieved. While the value V _{TH (n)} has the advantage of being low,
There is a disadvantage that the threshold value V _{TH (p) of the} p-MOS type semiconductor ( _p) is increased.

Note that the threshold value V _{TH (n) of} the n-MOS type semiconductor (n) is lower, whereas the threshold value V _{TH (p) of the} p-MOS type semiconductor (p) is lower.
The present invention presumes that the reason for the increase in the density is caused by defect levels remaining in the polysilicon film.

That is, when inactive ions such as silicon are implanted into the amorphous silicon film to partially destroy silicon microcrystal nuclei, lattice defects occur in the amorphous silicon film, and the defects remain in the film even after crystallization annealing. It seems to have survived.

Then, in the n-MOS type semiconductor (n) whose carriers are free electrons, the free electrons are hard to be trapped by the above-mentioned defect, and as a result, the threshold value V _{TH (n)} is lowered.
In a p-MOS semiconductor (p) in which carriers are holes (holes), the holes are easily trapped by the defect, and as a result, the threshold voltage V of the p-MOS semiconductor (p) is reduced.
_{Infers that TH (p)} will be high.

Here, FIG. 13 shows the injection amount of inert ions (Si ⁺ ) and p
FIG. 4 is a graph showing the relationship between the threshold voltage V _{TH (p)} of the MOS type semiconductor (p) and the threshold as the injection amount increases (that is, as the breakdown level of silicon microcrystal nuclei increases). It can be confirmed that the value V _{TH (p)} has increased (however, the absolute value).

As an example, the injection amount of the above inert ion (Si ⁺ ) is set to 2
The threshold values of the n-MOS type semiconductor (n) and the p-MOS type semiconductor (p) of the c-MOS type thin film semiconductor device obtained by setting to × 10 ¹⁵ ions / cm ² are V _{TH (n )} = 8 V and V _{TH (p)} = −18 V.

Then, the n-MOS type semiconductor (n) and p
If the absolute value of the threshold value of the -MOS type semiconductor (p) is greatly different from 8 or 18, there is a problem that the following problems are caused.

That is, in order for the inverter circuit to operate properly, the power supply voltage (V _DD ) and the threshold values of the n-MOS type semiconductor (n) and the p-MOS type semiconductor (p) have the following relational expressions. It took me.

V _DD ≧ V _{TH (n)} −V _{TH (p)} … Then, when the above threshold value is substituted into this equation to find the power supply voltage (V _DD ), V _DD ≧ 8 − (− 18) = 26V.

For this reason, there has been a problem that the inverter circuit cannot be operated with a normal 24V power supply.

The inverted voltage V _INV of this inverter circuit is n-MO
Gain coefficient ratio between S-type semiconductor (n) and p-MOS type semiconductor (p), when β _n / β _p = 1, V _INV = (V _DD + V _{TH (n)} + V _{TH (p)} ) / 2 ... It is represented by

Then, when the above threshold value and the power supply voltage value are substituted into this equation to obtain an inverted voltage V _INV , V _INV = [26 + 8 + (− 18)] / 2 = 8VV0.3V _DD (where V _DD = 26V).

For this reason, as shown in FIG. 14, there is a disadvantage that the noise margin on the LOW input side is smaller than that on the HIGH input side, and there has been a problem that the output signal tends to be erroneous.

The present invention has been made in view of the above problems, and the subject thereof is, for example, that when applied to an inverter circuit or the like, there is no variation in noise margin between the LOW input side and the HIGH input side, and An object of the present invention is to provide a manufacturing method capable of obtaining a c-MOS thin film semiconductor device operable with a normal 24 V power supply.

[Means for solving the problem]

That is, according to the present invention, an inert ion is implanted into an amorphous silicon film provided on a substrate by an ion implantation method, and a part of silicon microcrystal nuclei existing in the amorphous silicon film is destroyed by the ions to form a residual nucleus. Assuming a method of manufacturing a c-MOS type thin film semiconductor device in which the density is reduced and the amorphous silicon film is heated to grow into a polysilicon film for an active layer, an n-MOS type semiconductor formation region of the amorphous silicon film is provided. In order to reduce the residual nucleus density by implanting inert ions, no inert ions for destroying the silicon microcrystal nuclei are implanted in the p-MOS type semiconductor formation region. .

In such technical means, an insulating substrate such as a glass substrate, a quartz substrate, and a ceramics substrate can be applied as the substrate as in the related art.

Next, as a means for implanting inert ions only in the n-MOS type semiconductor formation region of the amorphous silicon film, a mask made of photoresist or SiO _{2 and} selectively exposed only in the formation region is used. A method in which an inert ion is ion-implanted through a mask formed on a silicon film can be applied.

As the inert ions implanted into the n-MOS type semiconductor formation region in the amorphous silicon film and destroying a part of the silicon microcrystal nuclei existing in the film, the implanted ions after the implantation are It is necessary that the ions do not affect the semiconductor characteristics of the silicon film. For example, ions such as silicon ions (Si ⁺ ), germanium ions (Ge ⁺ ), carbon ions (C ⁺ ), and argon ions ( Ar ⁺ ), rare gas ions such as xenon ion (Xe ⁺ ) and krypton ion (Kr ⁺ ), or fluorine ions (F ⁺ ), chlorine ions (Cl ⁺ ), and bromide ions (Br ⁺ )
And the above compound ions such as (SiF ⁺ ).

On the other hand, furnace annealing (furnace annealing), laser annealing, lamp annealing, and the like can be applied as an annealing means for heat-treating an amorphous silicon film to grow a crystal on polysilicon.

The structure of the c-MOS type thin film semiconductor device in this technical means is arbitrary. For example, as shown in FIG. 5A, a substrate (1) and a polysilicon film provided on the substrate (1) are provided. (2), source / drain electrodes (S) and (D) provided at both ends of the polysilicon film (2), and a gate electrode (G) provided via an insulating film (3). A self-aligned planar structure type in which the formation region of the source / drain electrodes (S) and (D) is regulated using the gate electrode (G) as a mask, or a substrate as shown in FIG. 5 (B). (1) a source electrode (S) and a drain electrode (D) provided on the substrate (1);
FIG. 5C shows a non-self-aligned coplanar structure type comprising a polysilicon film (2) provided on this surface and a gate electrode (G) provided via an insulating film (3). As shown in FIG. 1, a substrate (1), a polysilicon film (2) uniformly formed on the substrate (1), and a source / drain electrode (S) provided on the polysilicon film (2). (D) and a non-self-aligned planar structure type composed of a gate electrode (G) provided with an insulating film (3) interposed therebetween; a substrate (1) as shown in FIG. 5 (D); A gate electrode (G) provided on the substrate (1), a polysilicon film (2) formed via an insulating film (3), and a source electrode (G) provided on the polysilicon film (2). Inverted stagger structure type composed of drain electrodes (S) and (D), or FIG. Substrate as shown in E) (1)
And a gate electrode (G) provided on the substrate (1)
And a source / drain electrode (S) / (D) provided via an insulating film (3) and a polysilicon film (2) formed on this surface. is there.

[Action]

According to the technical means as described above, while inactive ions are implanted into the n-MOS type semiconductor formation region of the amorphous silicon film to reduce the residual nucleus density, the p-MOS type semiconductor formation region is Since no inactive ions for destroying the silicon microcrystal nucleus have been implanted, n-M is added to the polysilicon film in the p-MOS type semiconductor formation region.
Since the number of lattice defects is extremely reduced as compared with the OS type semiconductor formation region, holes are less likely to be trapped in the polysilicon film of the p-MOS type semiconductor, thereby lowering the threshold value of the p-MOS type semiconductor. On the other hand, since the polysilicon film of the n-MOS type semiconductor is formed of polysilicon having a large crystal grain size, the channel mobility can be increased and the threshold value can be reduced. In addition, it is possible to make the threshold value of the p-MOS semiconductor equal to the absolute value of the threshold value of the n-MOS semiconductor.

〔Example〕

Hereinafter, an embodiment in which a c-MOS type thin film semiconductor device according to the present invention is applied to an “inverter circuit” will be described in detail with reference to the drawings. As shown in FIGS. 3 to 3, a glass substrate (1) and an n-MO formed on the glass substrate (1)
Common to the S-type semiconductor (n) and the p-MOS type semiconductor (p) and the input side connected to the gate electrode (G) (G) of each semiconductor (n) (p) via the aluminum wiring part (7) The main part of the electrode (8) and the output-side common electrode (9) connected to the drain electrodes (D) and (D) of the semiconductors (n) and (p) via the aluminum wiring part (7) are also formed. It is configured.

The n-MOS type semiconductor (n) is formed on a glass substrate (1), and its grains are dendritic and have an average particle size of 1%.
An active layer polysilicon film (2n) made of polysilicon having a thickness of about 3 .mu.m; n.sup. ⁺ Source / drain electrodes (S) and (D) provided at both ends of the polysilicon film (2n); A gate insulating film (3) of SiO ₂ covering the film (2n), a gate electrode (G) formed of an n ⁺ polysilicon film provided on the gate insulating film (3), and the entire surface thereof; An SiO ₂ interlayer insulating film (4) covering the source, drain and source electrodes (S) and (D), and a gate electrode (G)
And a wiring section (7) connected to the
A p-MOS type semiconductor (p) is formed on a glass substrate (1), and has a polysilicon film (2p) for an active layer having an average grain diameter of 0.1 to 0.5 μm;
The p ⁺ source / drain electrodes (S) and (D) provided at both ends of p) cover the polysilicon film (2p).
SiO ₂ gate insulating film (3) and this gate insulating film (3)
A gate electrode (G) formed of a p ⁺ polysilicon film provided thereon, an SiO ₂ interlayer insulating film (4) covering the entire surface thereof, source / drain electrodes (S) (D), and And a wiring section (7) connected to the gate electrode (G).

Incidentally, the polysilicon film (2n) for the active layer of the n-MOS type semiconductor (n) is obtained by crystallization annealing in a state in which Si ⁺ ions are implanted into the amorphous silicon film to reduce the residual nucleus density. On the other hand, the polysilicon film (2p) for the active layer of the p-MOS type semiconductor (p) does not implant Si ⁺ ions into the amorphous silicon film, and thus does not generate lattice defects in the amorphous silicon film. The threshold value V _{TH (p)} of the p-MOS type semiconductor (p) is −8 V as is apparent from the graph of FIG. ) Is adjusted so that its absolute value is equal to the threshold value V _{TH (n)} = 8V.

Then, in the c-MOS type thin film semiconductor device according to this embodiment, similarly to the conventional inverter circuit, a negative input voltage (V _IN ) is applied from the input side common electrode (8) to each gate electrode (G) (G). When the voltage is applied, a channel is formed only on the p-MOS type semiconductor (p) side, the p-MOS type semiconductor (p) is turned on, the n-MOS type semiconductor (n) is turned off, and the power supply voltage (V _DD ) Is obtained from the output-side common electrode (9), while the gate electrode (G)
When a positive input voltage (V _IN ) is applied to (G), a channel is formed only on the n-MOS type semiconductor (n) side, and the n-MOS type semiconductor (n) is turned on and the p-MOS type semiconductor is turned on. (P) is in the OFF state, and the voltage equal to the low voltage (V _SS = 0) (ie, L
OW output) is obtained from the output-side common electrode (9).

At this time, in the c-MOS type thin film semiconductor device according to this embodiment, the threshold value V _{TH (p) of} the p-MOS type semiconductor _(p) is −8 V, and the threshold value of the n-MOS type semiconductor (n) is Since the value V _{TH (n)} is adjusted so that its absolute value is equal to 8 V, when these values are substituted into the above equation to determine the power supply voltage (V _DD ), V _DD ≧ _{TH ( n)} −V _{TH (p)} ≧ 8 − (− 8) = 16V, which has the advantage that this inverter circuit can be operated with a normally used 24V power supply, while substituting these values into the above equation Then, when the inversion voltage V _INV of this inverter circuit is obtained, V _INV = (V _DD + _{TH (n)} + V _{TH (p)} ) / 2 = [24 + 8 + (− 8)] / 2 = 24/2 = 12V = 0.5V _DD (where V _DD = 24V), and there is no variation in the noise margin between the LOW input side and the HIGH input side, so that there is an advantage that a highly accurate output signal is required.

"Manufacturing Process of c-MOS Thin Film Semiconductor Device" Hereinafter, a method of manufacturing the c-MOS thin film semiconductor device according to this embodiment will be described. First, the glass substrate (1)
After forming an amorphous silicon film having a thickness of 500 に て by a low pressure CVD method, the amorphous silicon film is patterned by dry etching using CF ₄ gas to form a p-MOS type as shown in FIG. 4 (A). Semiconductor (p) and n-MOS
Amorphous silicon film (2 ') for type semiconductor (n)
(2 ″) are formed respectively.

Next, as shown in FIG. 4 (B), the amorphous silicon film (2 ') for the p-MOS type semiconductor (p) is covered with a resist film (r), and n exposed in this state. −MO
Amorphous silicon film (2 ") for S-type semiconductor (n)
²⁸ Si ⁺ ions were implanted into the amorphous silicon film (2 ″) to destroy the silicon microcrystal nuclei present in the amorphous silicon film (2 ″) and reduce the residual nucleus density. The implantation energy of ²⁸ Si ⁺ ions was 36 KeV. And the dose is 2 × 10 ¹⁵ ions /
It was cm ^2.

Then, the resist film (r) is removed, and a crystallization annealing treatment is performed at 600 ° C. for 72 hours in a nitrogen atmosphere to convert each of the amorphous silicon films (2 ′) and (2 ″) into a polysilicon film (2p) ( 2n), a 1000Å thick SiO ₂ film is formed on this surface by a low pressure CVD method, and an annealing treatment is performed at 600 ° C. for 5 hours under a nitrogen atmosphere to densify the film. 4 (C) to form a gate insulating film (3) as shown in Fig. 4. The polysilicon film (2n) for the n-MOS type semiconductor (n) has a dendritic grain shape and an average grain size. Polysilicon with a diameter of 1 to 3 μm, while p
-The polysilicon film (2p) for the MOS type semiconductor (p) has an average grain diameter of 0.1 to 0.5 [mu] m and has few lattice defects in the film.

Next, a 3,000 mm thick polysilicon film is decompressed on this surface.
The film is formed by the CVD method, and the polysilicon film is patterned by dry etching using CF ₄ gas to form an n-MO.
After forming the gate electrodes (G) and (G) for the S-type semiconductor (n) and the p-MOS type semiconductor (p), respectively (see FIG. 4D),
The p-MOS type forming region of the semiconductor (p) is covered with a resist film (r), implanting p ⁺ ions by an ion implantation method as shown in FIG. 4 in this state (E), n ⁺ a A gate electrode (G) and an n ⁺ source electrode (S) and a drain electrode (D) self-aligned with the gate electrode (G) were formed. The implantation conditions were as follows: implanted ions: ³¹ p ⁺ , implanted energy: 110 KeV, and dose: 4 × 10 ¹⁵ ions / cm ² . Further, instead of p ⁺ ions, for example, As ⁺ , Sb ⁺ ions, or the like can be applied.

Next, while removing the resist film (r), the n-MO
After coating the S-shape forming region of the semiconductor (n) by a resist film (r), FIG. 4 by implanting B ⁺ ions at an ion implantation method as shown in (F), p ⁺ gate electrode (G) Then, a source electrode (S) and a drain electrode (D) of p ⁺ self-aligned with the gate electrode (G) were formed. The implantation conditions were as follows: implanted ions: B ⁺ , implanted energy: 40 KeV, dose: 4
× 10 ¹⁵ ions / cm ² . Further, in place of B ⁺ ions, for example, BF ₂ ⁺ ions or the like can be applied.

Next, the resist film (r) is removed, and the pressure is reduced.
4th layer of SiO ₂ interlayer insulating film (4) with thickness of 7000mm by CVD method
After the film is formed as shown in FIG. 7G, the film is heated at 600 ° C., 24 ° C. in a nitrogen atmosphere to activate dopants such as p ⁺ ions and B ⁺ ions.
After annealing for a long time, a contact hole (40) for wiring was opened in the interlayer insulating film (4) by RIE etching (see FIG. 4H).

Then, an Al-Si film having a thickness of 1 μm is formed on this surface by a sputtering method, and is patterned with a phosphoric acid-based etchant to form an aluminum wiring portion (7). After sintering in a forming gas, a hydrogen plasma treatment was performed at 350 ° C. for 4 hours using Ar / H ₂ gas to obtain a c-MOS type thin film semiconductor device as shown in FIG. 4 (I). .

〔The invention's effect〕

According to the present invention, the n-M type is formed in the polysilicon film in the p-MOS type semiconductor formation region.
Since the number of lattice defects is extremely reduced as compared with the OS type semiconductor formation region, holes are less likely to be trapped in the polysilicon film of the p-MOS type semiconductor, thereby lowering the threshold value of the p-MOS type semiconductor. On the other hand, since the polysilicon film of the n-MOS type semiconductor is formed of polysilicon having a large crystal grain size, the channel mobility can be increased and the threshold value can be reduced. In addition, it is possible to make the threshold value of the p-MOS semiconductor equal to the absolute value of the threshold value of the n-MOS semiconductor.

Therefore, when, for example, an inverter circuit is formed by using the c-MOS thin film semiconductor device, the operation of a normal 24 V power supply becomes possible by lowering each threshold value, and the absolute values of the threshold values become uniform. LOW input side and HIG
This has the effect that the noise margin on the H input side has no variation and a highly accurate output signal is required.

[Brief description of the drawings]

1 to 4 show an embodiment of the present invention. FIG. 1 is a schematic perspective view of a c-MOS type thin film semiconductor device according to the embodiment, FIG. 2 is a plan view thereof, and FIG. FIG. 1 is a sectional view taken along the line III-III of FIG. 1, and FIGS. 4 (A) to 4 (I) are process explanatory views showing the steps of manufacturing the c-MOS type thin film semiconductor device, and FIGS.
(E) shows a structural sectional view of a c-MOS type thin film semiconductor device to which the present invention is applied, and FIGS. 6 to 8 show a conventional c-MOS type thin film semiconductor device. 6 is a schematic perspective view, FIG. 7 is a plan view thereof, FIG. 8 is a sectional view taken along the line VIII-VIII of FIG. 6, and FIG. 9 is an "inverter circuit" constituted by the c-MOS type thin film semiconductor device. Circuit diagram of the tenth
FIG. 14 and FIG. 14 are graphs showing the relationship between the input (V _IN ) and the output (V _OUT ) of the “inverter circuit”, and FIG. 11 (A) to FIG.
(C) is a process explanatory view showing a process of forming a polysilicon film having a coarse gray diameter, FIG. 12 is a partially enlarged view of the polysilicon film applied to the thin film semiconductor device, and FIG. 13 is an inert ion FIG. 4 is a graph showing a relationship between the amount of (Si ⁺ ) implanted and the threshold value V _{TH (p)} of a p-MOS type semiconductor (p). [Description of Symbols] (1) Glass substrate (2n) (2p) Polysilicon film for active layer (n) n-MOS semiconductor (p) p-MOS semiconductor (G) Gate electrode (S): Source electrode (D): Drain electrode

Continuation of front page (72) Inventor Noriji Kato 2274 Hongo, Ebina-shi, Kanagawa Fuji Xerox Co., Ltd. Ebina Works (56) References JP-A-3-280434 (JP, A) JP-A-3-286521 ( JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/336 H01L 29/786

Claims (1)

(57) [Claims] An inert ion is implanted into an amorphous silicon film provided on a substrate by an ion implantation method, and a part of the silicon microcrystal nuclei existing in the amorphous silicon film is destroyed by the ions to leave the remaining nuclei. A method for manufacturing a c-MOS type thin film semiconductor device in which the density is reduced and the amorphous silicon film is heated to grow into a polysilicon film for an active layer, wherein the n-MOS type semiconductor formation region of the amorphous silicon film has A c-MOS type thin film characterized in that inactive ions are implanted to reduce the residual nucleus density, while no inactive ions for destroying the silicon microcrystal nuclei are implanted in the p-MOS type semiconductor formation region. A method for manufacturing a semiconductor device.