JP2824360B2 - Semiconductor device for current detection - Google Patents
Semiconductor device for current detectionInfo
- Publication number
- JP2824360B2 JP2824360B2 JP4115942A JP11594292A JP2824360B2 JP 2824360 B2 JP2824360 B2 JP 2824360B2 JP 4115942 A JP4115942 A JP 4115942A JP 11594292 A JP11594292 A JP 11594292A JP 2824360 B2 JP2824360 B2 JP 2824360B2
- Authority
- JP
- Japan
- Prior art keywords
- chip resistor
- electrode portion
- semiconductor device
- current detection
- resistance value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半田付けによって回
路接合されたチップ抵抗体を含む電流検出用半導体装置
に関し、特にチップ抵抗体の半田付け接続抵抗値の変化
(ドリフト)に対する影響を無くして高精度化を実現した
電流検出用半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current detecting semiconductor device including a chip resistor which is joined to a circuit by soldering, and more particularly to a change in a soldering connection resistance value of the chip resistor.
The present invention relates to a current detection semiconductor device that has achieved high precision without any influence on (drift).
【０００２】[0002]
【従来の技術】図４は従来の電流検出用半導体装置を示
す平面図であり、図において、１はトランジスタ等のパ
ワー素子(図示せず)が接続されたリードフレーム、２は
リードフレーム１上に半田付けにより接合された半導体
素子即ち制御ＩＣである。３は両端の電極部3a及び3bを
介してリードフレーム１間に半田付けされたチップ抵抗
体であり、制御ＩＣ２と協動して電流検出用抵抗体とし
て機能する。４はリードフレーム１と制御ＩＣ２とを電
気的に接続する金線のワイヤである。2. Description of the Related Art FIG. 4 is a plan view showing a conventional semiconductor device for current detection. In FIG. 4, reference numeral 1 denotes a lead frame to which a power element such as a transistor is connected (not shown); A semiconductor element, that is, a control IC, which is joined by soldering. Reference numeral 3 denotes a chip resistor soldered between the lead frames 1 via the electrode portions 3a and 3b at both ends, and functions as a current detecting resistor in cooperation with the control IC 2. Reference numeral 4 denotes a gold wire for electrically connecting the lead frame 1 and the control IC 2.
【０００３】図５は図４の電流検出用半導体装置の具体
的構成例を示す回路図であり、Ｒはチップ抵抗体３の抵
抗値である。５はパワー素子として機能するトランジス
タであり、エミッタがチップ抵抗体３の一端に接続さ
れ、ベースが制御ＩＣ２に接続されている。６はトラン
ジスタ５のコレクタに接続された電流検出用の高電位側
入力端子、７はチップ抵抗体３の他端に接続された電流
検出用の低電位側入力端子、８はトランジスタ５のベー
スに接続された制御端子である。FIG. 5 is a circuit diagram showing a specific configuration example of the current detecting semiconductor device of FIG. 4, where R is the resistance value of the chip resistor 3. Reference numeral 5 denotes a transistor functioning as a power element. The emitter is connected to one end of the chip resistor 3, and the base is connected to the control IC 2. Reference numeral 6 denotes a high-potential-side input terminal for current detection connected to the collector of the transistor 5, 7 denotes a low-potential-side input terminal for current detection connected to the other end of the chip resistor 3, and 8 denotes a base of the transistor 5. Control terminal connected.
【０００４】次に、図４を参照しながら、図５に示した
従来の電流検出用半導体装置の動作について説明する。
まず、リードフレーム１上に制御ＩＣ２及びチップ抵抗
体３を半田付けにより接合し、続いて、リードフレーム
１と制御ＩＣ２とをワイヤ４でボンディグし、制御ＩＣ
２とチップ抵抗体３とを電気的に接続する。Next, the operation of the conventional semiconductor device for current detection shown in FIG. 5 will be described with reference to FIG.
First, the control IC 2 and the chip resistor 3 are joined on the lead frame 1 by soldering, and then the lead frame 1 and the control IC 2 are bonded with the wires 4 to form a control IC.
2 and the chip resistor 3 are electrically connected.
【０００５】このように一体成型により組立てられた電
流検出用半導体装置において、制御端子８又は制御ＩＣ
２から制御信号を印加してトランジスタ５をオンさせる
と、検出対象となる電流は、高電位側入力端子６からト
ランジスタ５及びチップ抵抗体３を介して、低電位側入
力端子７に流れる。従って、制御ＩＣ２は、チップ抵抗
体３の両端間の電圧値に基づいて、入力端子６から供給
された電流を検出することができる。In the semiconductor device for current detection assembled by integral molding as described above, the control terminal 8 or the control IC
When the transistor 5 is turned on by applying a control signal from the second, a current to be detected flows from the high potential side input terminal 6 to the low potential side input terminal 7 via the transistor 5 and the chip resistor 3. Therefore, the control IC 2 can detect the current supplied from the input terminal 6 based on the voltage value between both ends of the chip resistor 3.
【０００６】ところで、電流検出用のチップ抵抗体３の
抵抗値Ｒは、通常30ｍΩ程度の低い値に設定されている
が、半田疲労や各部品間の応力疲労等により、リードフ
レーム１との間の接触抵抗値が変化することがある。
又、例えば検出電流の許容差が±５％の電流検出用半導
体装置の場合、30ｍΩの抵抗値Ｒに対する許容変化量
(ドリフト量)は１．５ｍΩ以下となる。The resistance value R of the chip resistor 3 for current detection is usually set to a low value of about 30 mΩ. May change in the contact resistance.
Further, for example, in the case of a current detecting semiconductor device having a tolerance of ± 5% of a detection current, an allowable change amount with respect to a resistance value R of 30 mΩ.
(Drift amount) is 1.5 mΩ or less.
【０００７】従って、上記のような半田付けによるチッ
プ抵抗体３の接合構造においては、ワイヤ４が半田付け
部分を介して制御ＩＣ２及びチップ抵抗体３を接続して
いるので、チップ抵抗体３を用いた電流検出は、正規の
抵抗値Ｒと半田付け部分の接触抵抗値のドリフト量とを
含めた抵抗値に基づいて行われることになる。Therefore, in the bonding structure of the chip resistor 3 by soldering as described above, since the wire 4 connects the control IC 2 and the chip resistor 3 via the soldered portion, the chip resistor 3 is connected. The used current detection is performed based on the resistance value including the regular resistance value R and the drift amount of the contact resistance value of the soldered portion.
【０００８】[0008]
【発明が解決しようとする課題】従来の電流検出用半導
体装置は以上のように、チップ抵抗体３をリードフレー
ム１に半田付けにより接続しているのみなので、半田付
け接続抵抗値のドリフト量の影響を顕著に受け、製品と
しての初期の歩留りが悪いうえ、長期間の使用に対して
電流検出レベルが変動して満足した特性が得られず、高
精度化を実現することができないという問題点があっ
た。As described above, since the conventional semiconductor device for current detection only connects the chip resistor 3 to the lead frame 1 by soldering, the drift amount of the soldering connection resistance value is reduced. The problem is that the product is significantly affected, the initial yield as a product is poor, and the current detection level fluctuates over a long period of use, so that satisfactory characteristics cannot be obtained and high accuracy cannot be realized. was there.
【０００９】この発明は上記のような問題点を解決する
ためになされたもので、チップ抵抗体の半田付け接続部
の抵抗値が変化しても検出精度を損なうことのない高精
度の電流検出用半導体装置を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has a high accuracy in current detection without deteriorating the detection accuracy even when the resistance value of a solder connection portion of a chip resistor changes. It is an object to obtain a semiconductor device for use.
【００１０】[0010]
【課題を解決するための手段】この発明の請求項１に係
る電流検出用半導体装置は、制御ＩＣとチップ抵抗体の
電極部とをワイヤボンディングにより接続したものであ
る。According to a first aspect of the present invention, there is provided a current detecting semiconductor device in which a control IC and an electrode portion of a chip resistor are connected by wire bonding.
【００１１】又、この発明の請求項２に係る電流検出用
半導体装置は、チップ抵抗体を、第１及び第２の電極部
間に形成された中間電極部と、第１及び第２の電極部間
に形成された第１のチップ抵抗体と、第１の電極部と中
間電極部に形成された第２のチップ抵抗体、及び、中間
電極部と第２の電極部との間に形成された第３のチップ
抵抗体からなる並列抵抗体とにより構成し、制御ＩＣと
中間電極部及び第３の電極部とをワイヤボンディングに
より接続したものである。According to a second aspect of the present invention, there is provided a semiconductor device for current detection, comprising a chip resistor, an intermediate electrode portion formed between the first and second electrode portions, and a first and second electrode portion. A first chip resistor formed between the portions, a second chip resistor formed on the first electrode portion and the intermediate electrode portion, and a first chip resistor formed between the intermediate electrode portion and the second electrode portion. The control IC is connected to the intermediate electrode portion and the third electrode portion by wire bonding.
【００１２】[0012]
【作用】この発明の請求項１においては、チップ抵抗体
と制御ＩＣとの回路接合を半田付け及びワイヤボンディ
ングの併用で行い、チップ抵抗体とリードフレームとの
半田付け接触抵抗値のドリフト量の影響を軽減すること
により、高精度に且つ安定にチップ抵抗体を形成する。According to the first aspect of the present invention, the circuit connection between the chip resistor and the control IC is performed by using both soldering and wire bonding, and the drift amount of the contact resistance of soldering between the chip resistor and the lead frame is reduced. By reducing the influence, the chip resistor is formed with high accuracy and stability.
【００１３】又、この発明の請求項２においては、第２
及び第３のチップ抵抗体からなる並列抵抗体を並設する
ことにより、第１のチップ抵抗体の抵抗値を大きく設定
できるようにし、半田付け接触抵抗値のドリフト量の影
響を更に軽減する。According to a second aspect of the present invention, the second
In addition, by providing the parallel resistor composed of the third chip resistor in parallel, the resistance value of the first chip resistor can be set to be large, and the influence of the drift amount of the soldering contact resistance value is further reduced.
【００１４】[0014]
実施例１．以下、この発明の実施例１を図について説明
する。図１はこの発明の実施例１を示す平面図であり、
１〜４は前述と同様のものである。この場合、制御ＩＣ
２とチップ抵抗体３とを接続するワイヤ４は、チップ抵
抗体３の電極部３ａ及び３ｂ上に直接ボンディングされ
ている。Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing Embodiment 1 of the present invention,
1 to 4 are the same as described above. In this case, the control IC
A wire 4 connecting the chip resistor 2 and the chip resistor 3 is directly bonded on the electrode portions 3a and 3b of the chip resistor 3.
【００１５】図１に示したこの発明の実施例１の動作に
ついては、前述と同様なのでここでは説明しない。しか
し、制御ＩＣ２とチップ抵抗体３との回路接合は、半田
付けのみならず、ワイヤ４を介しているので、半田付け
接触抵抗値のドリフトの影響を軽減することができる。
従って、チップ抵抗体３の抵抗値Ｒに基づいて高精度に
電流検出を行うことができる。The operation of the first embodiment of the present invention shown in FIG. 1 is the same as that described above and will not be described here. However, since the circuit connection between the control IC 2 and the chip resistor 3 is performed not only by soldering but also via the wire 4, the influence of the drift of the soldering contact resistance value can be reduced.
Therefore, current detection can be performed with high accuracy based on the resistance value R of the chip resistor 3.
【００１６】実施例２．尚、上記実施例では、従来と同
様の30ｍΩ程度のチップ抵抗体３を用いたが、チップ抵
抗体３と一体に並列抵抗体を形成した構造のチップ抵抗
体を用いてもよい。Embodiment 2 FIG. In the above embodiment, the chip resistor 3 of about 30 mΩ is used as in the prior art. However, a chip resistor having a structure in which a parallel resistor is formed integrally with the chip resistor 3 may be used.
【００１７】図２は並列抵抗体を併用したチップ抵抗体
を含むこの発明の実施例２を示す平面図である。30は並
列抵抗体併用型のチップ抵抗体であり、中間電極部３ｃ
を有し、電極部３ａと３ｂとの間のチップ抵抗体31と、
電極部３ａと中間電極部３ｃとの間のチップ抵抗体32
と、中間電極部３ｃと電極部３ｂとの間のチップ抵抗体
33とから構成されている。ここで、チップ抵抗体31は前
述のチップ抵抗体３に対応し、チップ抵抗体32及び33は
並列抵抗体を構成している。FIG. 2 is a plan view showing a second embodiment of the present invention including a chip resistor using a parallel resistor. Numeral 30 denotes a chip resistor which is used in combination with a parallel resistor.
A chip resistor 31 between the electrode portions 3a and 3b,
Chip resistor 32 between electrode portion 3a and intermediate electrode portion 3c
And a chip resistor between the intermediate electrode portion 3c and the electrode portion 3b
33. Here, the chip resistor 31 corresponds to the above-described chip resistor 3, and the chip resistors 32 and 33 constitute a parallel resistor.
【００１８】図３は図２の具体的回路構成例を示す回路
図であり、各チップ抵抗体31〜33の抵抗値は、それぞ
れ、R1、R2及びR3に設定されている。この場合、並列抵
抗値R2及びR3が追加されているので、半田付け接触抵抗
値のドリフトに直接影響されるチップ抵抗値R1を従来よ
り大きく設定することができる。従って、30ｍΩの場合
に±１．５ｍΩの初期許容抵抗値を要するのに対し、抵
抗値を大きくすれば、許容範囲を広げても±５％の検出
電流許容公差を得ることができる。FIG. 3 is a circuit diagram showing a specific example of the circuit configuration of FIG. 2. The resistance values of the chip resistors 31 to 33 are set to R1, R2 and R3, respectively. In this case, since the parallel resistance values R2 and R3 are added, the chip resistance value R1, which is directly affected by the drift of the soldering contact resistance value, can be set larger than before. Therefore, while an initial allowable resistance value of ± 1.5 mΩ is required in the case of 30 mΩ, if the resistance value is increased, a detection current allowable tolerance of ± 5% can be obtained even if the allowable range is widened.
【００１９】又、実施例２の構成においても、半田付け
接触抵抗値のドリフトの影響を受けにくくなる。更に、
チップ抵抗体30に対して抵抗値の調整用トリミングを行
う場合においても、抵抗値R1が大きいので、測定プロー
ブの接触抵抗値のバラツキを抑制することができる。Also in the configuration of the second embodiment, the influence of the drift of the soldering contact resistance value is reduced. Furthermore,
Even when the trimming for adjusting the resistance value is performed on the chip resistor 30, the variation in the contact resistance value of the measurement probe can be suppressed because the resistance value R1 is large.
【００２０】上記各実施例では、チップ抵抗体に接続さ
れる半導体素子が制御ＩＣ２の場合を示したが、他の半
導体素子又はパワー素子等の場合でも同等の効果を奏す
ることは言うまでもない。In each of the above embodiments, the case where the semiconductor element connected to the chip resistor is the control IC 2 has been described. However, it is needless to say that the same effect can be obtained when another semiconductor element or power element is used.
【００２１】[0021]
【発明の効果】以上のようにこの発明の請求項１によれ
ば、制御ＩＣとチップ抵抗体の電極部とをワイヤボンデ
ィングにより接続し、チップ抵抗体と制御ＩＣとの回路
接合を半田付け及びワイヤボンディングの併用で行い、
チップ抵抗体とリードフレームとの半田付け接触抵抗値
のドリフト量の影響を軽減するようにしたので、チップ
抵抗体の半田付け接続部の抵抗値が変化しても検出精度
を損なうことのない高精度の電流検出用半導体装置が得
られる効果がある。As described above, according to the first aspect of the present invention, the control IC and the electrode portion of the chip resistor are connected by wire bonding, and the circuit connection between the chip resistor and the control IC is soldered. Performed in combination with wire bonding,
The effect of the drift of the contact resistance of the chip resistor and the lead frame has been reduced, so that even if the resistance of the solder connection of the chip resistor changes, the detection accuracy will not be impaired. There is an effect that an accurate current detection semiconductor device can be obtained.
【００２２】又、この発明の請求項２によれば、チップ
抵抗体を、第１及び第２の電極部間に形成された中間電
極部と、第１及び第２の電極部間に形成された第１のチ
ップ抵抗体と、第１の電極部と中間電極部に形成された
第２のチップ抵抗体、及び、中間電極部と第２の電極部
との間に形成された第３のチップ抵抗体からなる並列抵
抗体とにより構成すると共に、制御ＩＣと中間電極部及
び第３の電極部とをワイヤボンディングにより接続し、
第１のチップ抵抗体の抵抗値を大きく設定できるように
したので、半田付け接触抵抗値のドリフト量の影響を更
に軽減することができ、チップ抵抗体の半田付け接続部
の抵抗値が変化しても検出精度を損なうことのない高精
度の電流検出用半導体装置が得られる効果がある。According to the second aspect of the present invention, the chip resistor is formed between the first and second electrode portions and the intermediate electrode portion formed between the first and second electrode portions. A first chip resistor, a second chip resistor formed on the first electrode portion and the intermediate electrode portion, and a third chip resistor formed between the intermediate electrode portion and the second electrode portion. A parallel resistor composed of a chip resistor, and a control IC connected to the intermediate electrode and the third electrode by wire bonding;
Since the resistance value of the first chip resistor can be set to a large value, the influence of the drift amount of the soldering contact resistance value can be further reduced, and the resistance value of the solder connection portion of the chip resistor changes. However, there is an effect that a highly accurate current detection semiconductor device without deteriorating the detection accuracy can be obtained.
【図１】この発明の実施例１を示す平面図である。FIG. 1 is a plan view showing a first embodiment of the present invention.
【図２】この発明の実施例２を示す平面図である。FIG. 2 is a plan view showing a second embodiment of the present invention.
【図３】この発明の実施例２の具体的回路構成例を示す
回路図である。FIG. 3 is a circuit diagram showing a specific example of a circuit configuration according to a second embodiment of the present invention;
【図４】従来の電流検出用半導体装置を示す平面図であ
る。FIG. 4 is a plan view showing a conventional semiconductor device for current detection.
【図５】従来の電流検出用半導体装置の具体的回路構成
例を示す回路図である。FIG. 5 is a circuit diagram showing a specific circuit configuration example of a conventional current detection semiconductor device.
１ リードフレーム ２ 制御ＩＣ(半導体素子) ３、３０〜３３ チップ抵抗体 ３ａ、３ｂ 電極部 ３ｃ 中間電極部 ４ ワイヤ DESCRIPTION OF SYMBOLS 1 Lead frame 2 Control IC (semiconductor element) 3, 30-33 Chip resistor 3a, 3b Electrode part 3c Intermediate electrode part 4 Wire
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) G01R 19/00 - 19/32 G01R 15/00 - 15/12 H01L 23/50──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. 6 , DB name) G01R 19/00-19/32 G01R 15/00-15/12 H01L 23/50
Claims (2)
付けされたチップ抵抗体と、このチップ抵抗体に電気的
に接続された半導体素子とを有する電流検出用半導体装
置において、 前記半導体素子と前記チップ抵抗体の電極部とをワイヤ
ボンディングにより接続したことを特徴とする電流検出
用半導体装置。1. A current detecting semiconductor device comprising: a chip resistor soldered on a lead frame via an electrode portion; and a semiconductor element electrically connected to the chip resistor. A semiconductor device for current detection, wherein the electrode portion of the chip resistor is connected by wire bonding.
部を介して半田付けされたチップ抵抗体と、このチップ
抵抗体に電気的に接続された半導体素子とを有する電流
検出用半導体装置において、 前記チップ抵抗体は、 前記第１及び第２の電極部間に形成された中間電極部
と、 前記第１及び第２の電極部間に形成された第１のチップ
抵抗体と、 前記第１の電極部と前記中間電極部に形成された第２の
チップ抵抗体、及び、前記中間電極部と前記第２の電極
部との間に形成された第３のチップ抵抗体からなる並列
抵抗体と、 を備え、 前記半導体素子と前記中間電極部及び前記第３の電極部
とをワイヤボンディングにより接続したことを特徴とす
る電流検出用半導体装置。2. A current detecting semiconductor device comprising: a chip resistor soldered on a lead frame via first and second electrode portions; and a semiconductor element electrically connected to the chip resistor. In the above, the chip resistor may include: an intermediate electrode portion formed between the first and second electrode portions; a first chip resistor formed between the first and second electrode portions; A second chip resistor formed between the first electrode portion and the intermediate electrode portion, and a third chip resistor formed between the intermediate electrode portion and the second electrode portion. And a resistor, wherein the semiconductor element is connected to the intermediate electrode portion and the third electrode portion by wire bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4115942A JP2824360B2 (en) | 1992-05-08 | 1992-05-08 | Semiconductor device for current detection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4115942A JP2824360B2 (en) | 1992-05-08 | 1992-05-08 | Semiconductor device for current detection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05312847A JPH05312847A (en) | 1993-11-26 |
| JP2824360B2 true JP2824360B2 (en) | 1998-11-11 |
Family
ID=14674992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4115942A Expired - Fee Related JP2824360B2 (en) | 1992-05-08 | 1992-05-08 | Semiconductor device for current detection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2824360B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19906276A1 (en) | 1999-02-15 | 2000-09-21 | Heusler Isabellenhuette | Method and current measuring module for current monitoring in a power supply system |
| JP6344163B2 (en) | 2014-09-03 | 2018-06-20 | 株式会社デンソー | Shunt resistor |
| JP2019021944A (en) * | 2018-11-07 | 2019-02-07 | ラピスセミコンダクタ株式会社 | Semiconductor device and measuring device |
-
1992
- 1992-05-08 JP JP4115942A patent/JP2824360B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05312847A (en) | 1993-11-26 |
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