JP2823614B2 - Gradation display method and liquid crystal display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of gradation display.

[Prior Art] As a gray scale display method in a conventional liquid crystal display device, as a first method, there is a frame thinning method as described in an HD66840 LVIC application note manufactured by Hitachi. There is a pulse width modulation system as described in -149393.

In the first method, the frame thinning method, m frames are defined as one cycle for displaying one dot of liquid crystal, on display is performed in n frames during the period, and the remaining (mn) is displayed.
This is a method of visually realizing gradation display by performing off display in a frame. The value n / m obtained by dividing the value of n by m is called a thinning rate. When this value is 0, the display luminance level is 0%. When it is 1, the display luminance level is 10%.
It becomes 0%.

The frame thinning method will be described with reference to FIGS. FIG. 2 is a block diagram of a liquid crystal display system that performs 8-gradation display using 3-bit display data, FIG. 3 is a block diagram of a frame thinning circuit, and FIG. 4 is a diagram showing an example of frame thinning data. It is.

In FIG. 2, the 3-bit display data 14 is converted into frame thinning data FD15 by the frame thinning circuit 4 shown in FIG. In accordance with the FD 15, the liquid crystal display pulse Poff (one horizontal period off-level pulse) or Pon (one horizontal period on-level pulse) is output from the X drive circuit 2 to the liquid crystal pulse 1.

The frame thinning circuit 4 shown in FIG. 3 has eight kinds of thinning circuits 25 to 32, and thinning data output therefrom.
One of 33 to 40 is selected by the selection circuit 41 according to the 3-bit display data 14 and output as the FD 15. Each of the thinning circuits 25 to 32 generates thinned data according to the thinning rate by using the first line clock 16, the line clock 17, and the data latch clock 19. Hitachi HD66840 LV
In the IC, in order to prevent flicker on the liquid crystal panel 1 screen, a method is adopted in which all the dots constituting the liquid crystal panel 1 are not thinned out at the same timing, and n lines out of m lines are thinned out in units of horizontal m lines. And the first line clock
The thinning data is generated by 16 and the line clock 17.

FIG. 4 shows thinning data of a thinning rate of 4/5 of Hitachi HD66840 LVIC. The shaded area indicates the display ON. At a thinning rate of 4/5, the horizontal 5 lines are set as one unit, and the horizontal 4 lines are set to the display ON, and the display ON and the display OFF are moved for each frame. Display is realized.

Next, the pulse width modulation method, which is the second method, will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 5 is a configuration example of a liquid crystal display device that performs three-gradation display using the pulse width of a voltage pulse applied to liquid crystal in one horizontal period. Two types of data of display information XA and XB for displaying one dot of liquid crystal in one horizontal period are provided by a data selector 1.
In 2, the data select signal 21 selects one of them, and the selected data is supplied to the X drive circuit 2 as one type of data XD. The X drive circuit 2 outputs the data XD from the data selector 12 to the data latch clock 19
Take in. This capture is repeated, and display data for one line is captured. Then, pulse clock 18
Then, a liquid crystal application pulse is output to the signal lines X1, X2,..., Xi of the liquid crystal panel 1. The pulse clock 18 is a clock for equally dividing the line clock 17 for each horizontal period into two. The Y drive circuit 3 converts the first line clock 16 to the line clock 17
And set Y1 to “high”, then line clock
Shift "high" from Y2 to Yj according to 17. The liquid crystal panel 1 is a matrix-type panel having i rows and j columns.
Liquid crystal application pulses X1, X2,..., Xi output from the drive circuit 2
, Yj of the Y drive circuit 3 is applied to the liquid crystal cell of the line which is "high" for display.

FIG. 6 is a diagram showing a liquid crystal application pulse output from the X drive circuit 2. During one horizontal period, the X-drive circuit 2 outputs one of the two types of display data XA and XB from the data selector 12.
One type of display data XD is selected and sent every 1/2 horizontal period, and one of four types of pulses, pulse 1 to pulse 4, is selected based on the data XD and output from the X drive circuit 2.

FIG. 7 shows the correspondence between the display data XD and the drive pulse output from the X drive circuit 2.

In FIG. 7, when the display data is (XA, XB) = (0, 0), the liquid crystal application pulse output from the X drive circuit 2 is pulse 1, and the display is off. (XA, XB) = (1,
In the case of 1), the liquid crystal application pulse becomes pulse 4, and the display is turned on. Also, the liquid crystal application pulses of (XA, XB) = (0, 1) and (1, 0) are pulse 2 and pulse 3, respectively, and the display is a halftone display of luminance between off and on. The display luminance (transmittance) of the liquid crystal depends on the effective value of the voltage applied to the liquid crystal. Since the pulse clock 18 is obtained by equally dividing the line clock 17 into two, the "H" period of the pulses 2 and 3 is equal, and the effective values of the pulses 2 and 3 are equal. For this reason, the display luminance of the liquid crystal display by the pulse 2 and the pulse 3 is equal, and as a result, the intermediate luminance between the OFF display and the ON display is obtained, and the three gradation display can be realized.

Therefore, the liquid crystal display device shown in FIG.
By changing the effective value of the voltage applied to the liquid crystal panel 1 by the combination of the above, it is possible to realize gradation display.

[Problem to be Solved by the Invention] In the frame thinning method of the prior art, when the thinning cycle, that is, the value of m, is increased, flickering or display flow in which the thinning timing can be visually recognized occurs, and the display quality of gradation display is increased. Is decreasing. Therefore, the practical number of gradations is around 10 gradations, and for example, multi-gradation display such as 16 gradations and 32 gradations cannot be performed.

On the other hand, in the conventional pulse width modulation method, when the display area of the halftone display is large in the X direction (the horizontal direction of the screen), 1
There is a problem that noise is generated due to the rising or falling edge of the pulse that changes simultaneously during the horizontal period, and the display luminance is reduced.

Further, when the display area of the halftone display is large in the Y direction (the vertical direction of the screen), there is a problem that the frequency component of the liquid crystal application pulse is increased, the display luminance is reduced, and crosstalk is increased.

An object of the present invention is to use a voltage pulse having a pulse width obtained by dividing one horizontal period into two, and to increase the display area of the halftone display in the X direction and the Y direction without lowering the display luminance and further improving the display quality. An object of the present invention is to provide a liquid crystal display device capable of performing multi-gradation display without lowering.

[Means for Solving the Problems] In order to achieve the above object, a gradation display method according to the present invention uses one line data taken into an X drive circuit as Y data.
In a gray scale display method of a matrix type display pulse displayed on a horizontal line sequentially instructed by a drive circuit, a frame thinning for controlling on / off of a display dot in a frame unit and a pulse of a pulse applied to each X drive line in one horizontal period are performed. In conjunction with pulse width modulation that modulates the width, the frame thinning is thinned out in a skewed dot pattern in each frame, and the skewed dot pattern to be thinned out is shifted each time the frame changes. It is.

In this method, preferably, the display corresponding to the first and second pulses applied within one horizontal cycle to each X drive line is preferably performed so as to reduce the number of changes of the pulse applied to each X drive line. Swap data.

Alternatively, each of the X drive lines is controlled such that the number of positive direction changes and the number of negative direction changes of the pulses applied to all the X drive lines are substantially the same.
The display data corresponding to the first and second pulses sequentially applied to the drive line within one horizontal cycle is exchanged.

In addition, the liquid crystal display device according to the present invention has a display data of 1
A display comprising one dot in a liquid crystal display device including an X drive circuit for taking in lines and outputting the data to a liquid crystal panel, and a Y drive circuit for sequentially designating horizontal lines on which data output from the X drive circuit is to be displayed. Frame thinning means for generating frame thinning data for controlling display dots on / off in frame units in accordance with the lower data portion of data, and a first line memory for storing one line of the upper data portion of the display data constituting one dot When,
A second line memory for storing one line of frame thinning data output from the frame thinning circuit, one line of higher-order data in the first line memory, and frame thinning data in the second line memory And 1
Means for sequentially supplying the data to the X drive circuit within a horizontal period, and inputting the frame thinning data and the high-order data corresponding to the dot in accordance with the position of the dot in a frame before supplying the data to the X drive circuit at the latest. Replacement means.

In this apparatus, the frame thinning means thins out, for example, 2N lines in the Y direction and m dots in the X direction (N and m are integers) as one unit.

[Operation] In the present invention, a frame thinning method and a pulse width modulation method are used in combination for a multi-gradation display, and measures are taken so as not to lower the display luminance. That is, in the frame thinning method, frame thinning data is generated in accordance with lower-order data of display data of a plurality of bits per dot.

Further, pulse width modulation control is performed based on the frame thinning data and the upper data of the two types of display data. Regarding this control, a phase inversion circuit that modulates the phase of a liquid crystal application voltage pulse for realizing halftone display with respect to adjacent dots in the X direction is provided.
The phase of the liquid crystal additional voltage pulse is modulated. In order to give display data to the X drive circuit twice within one horizontal period,
It is necessary to perform reading at twice the speed of writing, and for that purpose, first and second line memories are provided. Preferably, two first and second line memories are provided, respectively, in order to execute writing and reading simultaneously.

The phase inversion circuit rearranges 2-bit data sent for 1-dot display with respect to adjacent X-direction and Y-direction dots, and a liquid crystal corresponding to the rearranged 2-bit display data. The applied pulse is applied to the liquid crystal panel via the X drive circuit. By rearranging the data, the phase of the liquid crystal application pulse is inverted, and the noise due to the rise and the noise due to the fall are canceled out, so that a so-called canceling effect is used to prevent a decrease in display luminance due to an increase in the halftone display area.

The frame thinning circuit performs thinning processing in a skewed dot pattern. For example, vertical line thinning is performed with 2N horizontal lines and m dots vertically as one unit (where N is an integer and m is a thinning cycle). This makes it possible to effectively use the canceling effect due to the phase inversion.

Embodiment A liquid crystal display system according to an embodiment of the present invention will be described below with reference to FIG. This system displays 16 gradations by receiving input data of 4 bits per display dot.

FIG. 1 is a block diagram showing an embodiment of the present invention, wherein reference numerals 13 and 14 denote high-order display data and low-order 3 bit display data, respectively, and 4 denotes conversion of low-order 3 bit display data 14 into frame thinning data FD15. 5 and 6 are line memories 1 for storing upper display data 13.
A, 2A, 7 and 8 are line memories 1B and 2B for storing one line of the frame thinning data 15. 10 is the data select signals 20 and 21 by the pulse clock 18 and the line clock 17.
The data select signal 20 is a signal that repeats “high” and “low” in accordance with the line clock 17, and the data select signal 21 has a frequency twice as high as that of the line clock 17. This signal repeats “high” and “low” in accordance with the pulse clock 18. Reference numerals 11 and 12 denote data select circuits, 9 denotes a phase inversion circuit for rearranging two types of data, 1 denotes a liquid crystal panel, and 2 and 3 denote X and Y drive circuits for driving the liquid crystal panel 1, respectively.

In FIG. 1, the upper display data 13 is alternately fetched for each line into the line memory 1A or the line memory 2A, and is read from the line memory which has not been fetched. This reading is performed at twice the speed of writing, and the same data in the line memory
It is read out many times. The read data M1A or M2A is selected by the data select circuit 11 as MA. The same operation is performed on the frame thinning data 15 by the line memory 1B and the line memory 2B, and the data MB is selected by the data select circuit 11.

The phase inversion circuit 9 rearranges the data MA and MB sent from the data selection circuit 11 in dot units in the X direction (screen horizontal direction) and outputs the data as drive data XA and XB of the X drive circuit 2. The dots to be rearranged differ depending on the line and each dot position. For example, the rearrangement of data of the phase inversion circuit 9 is performed as shown in FIG.
The dots indicated by "-" are output as X drive data XA and XB without rearranging the input data MA and MB.
For dots indicated by “○”, input data MA, MB
And outputs as X drive data XA, XB. That is, in the phase inversion circuit 9, when the input data (MA, MB) = (0, 1) or (1, 0), the data is rearranged by dots indicated by “○”, and XA, Output to XB. If (MA, MB) = (0,0) or (1,1),
Even if the data is rearranged, the data becomes the same, so that it is output to XA and XB as it is. Of course, for convenience of processing, rearrangement may be performed in these cases. The data select circuit 12 selects one of XA and XB from the data select signal 21 for equally dividing one line into two, and outputs XA and XB as XD24.

FIG. 9 shows output data (XA, XB) for each dot when input data (MA, MB) = (0, 1).

The X drive circuit 2 is similar to the prior art shown in FIG.
Higher-order data for one line display with data latch clock 19
XD (= XA) is taken in, and display information indicated by XD (= XA) is output from X1 to Xi at the falling edge of the pulse clock 18 thereafter. Further, while the X drive circuit 2 is outputting display information of the upper data XD (= XA), the data latch clock 19
To capture the lower-order data XD (= XB) for one line, and output the display information indicated by XD (= XB) from X1 to Xi at the falling edge of the pulse clock 18 applied from the X drive circuit 2. The display information X1 to Xi is applied to the liquid crystal on one line of the output Y1 to Yj of the Y drive circuit 3 which is "high" at that time, and a light quantity proportional to the display information is transmitted. still,
The Y drive circuit 3 takes in the first line clock 16 and the line clock 17, sets Y1 to “high”, and then sequentially shifts “high” to Y2 to Yj by the line clock 17.

In the liquid crystal display circuit of FIG. 1 described above, display data of (higher-order display data, frame thinning data) = (0, 1) is input and displayed in the i-th row and the j-th column as shown in FIG. When halftone display is performed (here, i and j are assumed to be 6), the X drive circuit 2 outputs a display pulse shown in FIG.

According to FIG. 11, the output pulses of adjacent X dots are different, and when the pulse of a certain dot rises, the pulse of the adjacent dot falls at the same time. in this way,
The rising edge and the falling edge of the display pulse of adjacent dots cancel each other's noise, and the effect of eliminating or reducing the decrease in luminance in the liquid crystal display, that is, the effect of canceling out is produced.

In addition, by combining the display pulse of one line and the display pulse of the next line or the display pulse of the previous line in a certain X dot into one, the rising or falling of the display pulse in one line is eliminated, and during one frame period, Of the display pulse is reduced by half. This has the effect of reducing the frequency component by half, and consequently reducing the crosstalk generated in the liquid crystal pulse 1.

 Next, the frame thinning circuit 4 will be described.

The circuit configuration of the frame thinning circuit 4 is the same as that of the prior art shown in FIG. 3, and is a selection for selecting one of eight types of thinning circuits 25 to 32 and eight types of thinning data 33 to 40 output from these circuits. The circuit 41. As described above, the thinning circuit 25
Each of ~ 32 is the first line clock 16, line clock
17, thinned data is generated by the data latch clock 19 in accordance with each thinning rate.

FIG. 12 shows thinning data in a skewed dot pattern according to the present invention (for example, a case of a thinning rate of 4/5 is shown) (a hatched portion indicates "1" (display ON)). Unlike the thinning-out data of the prior art shown in FIG. 4, two lines in the screen Y direction (vertical direction) and m dots in the X direction (horizontal direction) (where m is m of the thinning cycle m frames) are set to one. This is thinning data in units. One unit of thinned data in the Y direction, that is, two lines are the same data. In order to prevent flickering on one screen of the liquid crystal panel, the thinned data is shifted for every two lines in the Y direction.

FIG. 20 shows a circuit example of the thinning circuit for generating the thinning data shown in FIG. This circuit corresponds to one thinning circuit included in the frame thinning circuit as shown in FIG.

This thinning circuit comprises a quinary frame counter 201 for counting the first line clock 16 and a first line clock 16
A quinary line counter 202 that loads the value of the frame counter 201 and counts the 1/2 frequency divided output of the line clock 17 using this value as an initial value, and a frequency divider 2 that performs this frequency division
05, a quinary data counter 203 that loads the output value of the line counter 202 with the line clock, counts the data latch clock using this value as an initial value, and a predetermined value corresponding to the output value of the data counter 203. And a bit halftone signal generating circuit 204 for outputting a dot pattern. Frame counter 201 and data counter 203
The decimal counter corresponds to the value (frame period) of the denominator of the thinning rate 4/5, and can be changed depending on the thinning rate. The line counter 202 is a quinary counter, which corresponds to the fact that there are five different line patterns in 10 lines in the thinning-out pattern in FIG. 12, and that dividing the line clock by two is equivalent to two lines. This corresponds to the change of the line pattern in units. The line patterns are '01111', '10111', '11011' in this example,
'11101' and '11110'. The content of this line pattern differs depending on the thinning rate. Bit halftone signal generation circuit
204 generates a different line pattern corresponding to the output value of the data counter 203, and can be constituted by a decoder or a memory table.

According to this thinning circuit, in one frame, 2
The phase of the line pattern shifts by one dot in the horizontal direction for each line, and also shifts by one dot for each frame. Accordingly, a thinning pattern in a skewed dot pattern as shown in FIG. 12 is generated.

In this thinning circuit configuration, the selector 41 shown in FIG.
Will output parallel data. Therefore, a line memory having a plurality of bits is used.
If the line memory is to input serial data, it is necessary to perform parallel-to-serial conversion.

The details of each block in FIG. 1 have been described above. Next, a display example by the liquid crystal display system of FIG. 1 will be described with reference to FIGS. As a display example, a 6 × 6 dot liquid crystal is used, the X driving electrodes are X1 to X6 from the left side, and the Y driving electrodes are Y1 to Y6 from the upper side.

FIG. 13 shows a case where the upper display data MA13 is “0” and the frame thinning data MB15 is data with a thinning rate of 1/3.
The X drive pulse and the display luminance level (16.7%) are shown.
“X” in the upper display data MA and the frame thinning data MB indicates “0” in the display off state, and “○” indicates “1” in the display on state. In addition, the numbers of the X driving pulses mean the pulses 1 to 4 shown in FIG. 7, respectively.

In FIG. 13, since the upper display data MA is all “0”, the X driving pulse is pulse 1 for the dot whose frame thinning data MB is “0”, and the frame thinning data MB is “1”. The X drive pulse becomes pulse 2 or pulse 3 via the phase inversion circuit 9 of the operation shown in FIG. Therefore, the luminance level of the entire screen is 16.7% for each frame.

FIG. 14 shows the waveform of the X drive pulse shown in FIG. The first frame is a combination of “Pulse 2, Pulse 3” or “Pulse 3, Pulse 2” for every two lines in the Y direction, and the display pulses in the order of “X1 → X2 → X3” and “X4 → X5 → X6” Is applied to each X electrode. The two frames are “X3 → X1 → X2” and “X6 → X4 →
A display pulse is applied to each X electrode in the order of “X5”, and in the third frame, a display pulse is applied to each X electrode in the order of “X2 → X3 → X1” and “X5 → X6 → X4”. Since the frame thinning data MB in FIG. 13 has a thinning rate of 1/3, the fourth and subsequent frames are repeated from the first frame to the third frame. In two lines Y1 and Y2 of the first frame, X1
“Pulse 2 and pulse 3” are applied to the electrodes, and “pulse 3 and pulse 2” are applied to the X4 electrode, and the change points of the pulses are offset between the two electrodes. Similarly, in two lines Y3 and Y4, “Pulse 3, pulse 2” is applied to the X2 electrode, and “pulse 2, pulse 3” is applied to the X5 electrode. Are offsetting each other. In the two lines Y5 and Y6, the X3 electrode and the X6 electrode cancel each other at the pulse change point between the electrodes.

Similarly, in the second and subsequent frames, the changing points of the pulses are canceled by the two electrodes, and this effect prevents the brightness reduction phenomenon due to the enlargement of the display area.

FIG. 15 shows the X drive pulse and the display luminance level (66.7) when the upper display data MA are all “1” and the frame thinning data MB is thinning data of 1/3 thinning rate.
%). Since the higher-order display data MA are all “1”, the X driving pulse is pulse 4 for the dot of which the frame thinning data MB is “1”, and the dot of which the frame thinning data MB is “0”. , The X drive pulse becomes pulse 2 or pulse 3 via the phase inversion circuit 9 of the operation shown in FIG. Therefore, the luminance level of the entire screen is 66.7% for each frame. FIG. 16 shows the waveform of the X drive pulse in FIG. As in the case of FIG. 14, X1
And X4, X2 and X5, and X3 and X6 cancel out the changing points of the pulse. Further, the change points that are not offset between the two electrodes (for example, the rising change points of the first frame, the X2 electrode, and the Y3 line) are the change points of the X electrodes other than the paired electrodes (in this case, the X5 electrode) ( In this case, the change points are offset by the falling change point at the X4 electrode, that is, the number of rising changes and the number of falling changes in each line are the same, thereby canceling the changing points of the pulse, The phenomenon of luminance reduction due to the enlargement of the display area is prevented.

As described above, the thinning method of the frame thinning circuit 4 shown in FIG. 1 uses two lines in the screen Y direction and m dots in the X direction as shown in FIG. 12, but the screen Y direction has four lines, six lines,
8 lines ... 2N lines, 1 x m dots in X direction
The same can be considered for a unit (N is an integer).

Also, without controlling the screen in the Y direction, the m dots in the X
As a unit, a method of thinning out n dots (vertical lines) out of m dots in the X direction (m lines in the vertical direction) can be similarly considered, and will be described with reference to FIGS. 17 to 19.

FIG. 17 shows frame thinning data of each frame, taking a thinning rate of 4/5 as an example, and a hatched portion indicates "1" in a display ON state.

FIG. 18 shows that the upper display data MA is all “0”, and the frame thinning data MB is all lines in the screen Y direction and 3 in the X direction.
The X driving pulse and the display luminance level (16.7
%). As in Fig. 13, upper display data
Since MA is all "0", the X drive pulse is pulse 1 for a dot whose frame thinning data MB is "0", and is shown in FIG. 8 for a dot of "1". The pulse for X driving becomes pulse 2 or pulse 3 via the phase inversion circuit 9 of the operation. Therefore, the display luminance level is 16.7% for each frame. FIG. 19 shows the waveform of the X drive pulse.

In FIG. 19, the first frame is a pulse 2 at the X1 electrode.
A pulse is applied in the order of → pulse 3 → pulse 2 → pulse 3 and a pulse is applied to the X4 electrode in the order of pulse 3 → pulse 2 → pulse 3 → pulse 2; a pulse change point between the two electrodes Are offsetting each other. Other X2, X3, X5, X
Pulse 1 is applied to all six electrodes. Similarly,
In the second frame, the changing points of the pulses are offset each other between the electrodes X2 and X5, and in the third frame, the changing points of the pulses are offset between the electrodes X3 and X6.

As described above, the X drive pulse and the luminance level have been described by taking the thinning rate 1/3 as an example. However, the same can be said for the other thinning rates. A reduction in display luminance due to enlargement is prevented, and a multi-gradation display with stable display luminance is possible.

Further, in the above embodiment, only the liquid crystal panel has been described, but the present invention is applicable to other flat display panels such as plasma and EL. Further, in the case of colorization, pseudo multicoloring can be realized by applying the present invention corresponding to each color of red, blue and green.

[Effects of the Invention] According to the present invention, it is possible to perform a gradation display at a fine stage which cannot be realized by the frame thinning method, and therefore, there is a great effect in displaying a multi-gradation. For example, in order to obtain a gradation display with a luminance level of 10%, if the frame thinning method is simply used, a thinning rate of 1/10 with poor display quality must be used. By setting the data to “0” and realizing the frame thinning data at a thinning rate of 1/5, a gradation display with good display quality is possible.

Also, by using a method of thinning out 2N lines in the screen Y direction and m dots in the X direction as one unit, the effect of canceling the changing point of the X drive pulse can be effectively utilized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a 16-gradation display system according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional frame-thinning gradation display system, FIG. FIG. 5 is an explanatory view of frame thinning data of the prior art, FIG. 5 is a block diagram of a pulse width modulation gray scale display system of the prior art, FIGS. 6 and 7 are explanatory views of display pulses of pulse width modulation, FIG. FIG. 11 to FIG. 11 are explanatory diagrams of the phase inversion circuit in FIG. 1, FIG. 12 to FIG. 16 are explanatory diagrams in the case where the thinning method is two lines in the Y direction and m dots in the X direction are one unit in the present invention. 17 to 19 are explanatory diagrams in the case where the thinning method is set to all the lines in the Y direction and m dots in the X direction as one unit in the present invention, and FIG. 20 performs thinning control in both XY directions in a diagonal dot pattern. It is a block diagram of a circuit example. DESCRIPTION OF SYMBOLS 1 ... Liquid crystal panel, 2 ... X drive circuit, 3 ... Y drive circuit, 4 ... Frame thinning circuit, 5-8 ... Line memory, 9 ... Phase inversion circuit, 10 ... Data selector signal generation circuit , 11, 12… Data selector, 13, 14… Upper and lower display data, 15… Frame culling data, 16… Top line clock, 17… Line clock, 18… Pulse clock, 19… Data Latch clock.

Continuing on the front page (72) Inventor Satoshi Onuma 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Video Engineering Co., Ltd. (56) References JP-A-54-53922 (JP, A) JP-A-3-125188 (JP, A) JP-A-2-205890 (JP, A) JP-A-2-1977893 ( JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G09G 3/00-3/38 G02F 1/133

Claims (5)

(57) [Claims] 1. A gray scale display method of a matrix type display panel for displaying one line data taken into an X drive circuit on horizontal lines sequentially designated by a Y drive circuit, on / off control of display dots in frame units. Frame thinning and pulse width modulation that modulates the width of a pulse applied to each X drive line in one horizontal period are used together. The frame thinning is performed in each frame in a skewed dot pattern, and the frame is thinned. A gradation display method characterized in that the skewed dot pattern to be thinned out is shifted every time it changes. 2. The display data corresponding to the first and second pulses applied within one horizontal cycle to each X drive line so as to reduce the number of changes of the pulse applied to each X drive line. 2. The gradation display method according to claim 1, wherein the display is replaced. 3. The method according to claim 1, wherein the number of positive-direction changes and the number of negative-direction changes of pulses applied to all X drive lines are substantially the same.
2. The gradation display method according to claim 1, wherein display data corresponding to the first and second pulses sequentially applied to the drive line within one horizontal cycle is exchanged. 4. A liquid crystal display comprising: an X drive circuit for fetching display data for one line and outputting the data to a liquid crystal panel; and a Y drive circuit for sequentially designating horizontal lines on which data output by the X drive circuit are to be displayed. In the apparatus, frame thinning means for generating frame thinning data for controlling display dots on / off in units of frames in accordance with the lower data portion of the display data constituting one dot; A first line memory for storing one line, a second line memory for storing one line of frame thinning data output from the frame thinning circuit, and one line of upper data in the first line memory; A method of sequentially giving frame thinning data in the second line memory to the X drive circuit within one horizontal period. And a means for exchanging the frame thinning data and the high-order data corresponding to the dot in accordance with the position of the dot in the frame at the latest before giving it to the X drive circuit. Liquid crystal display. 5. The liquid crystal display device according to claim 4, wherein said frame thinning means thins out 2N lines in the Y direction and m dots in the X direction (N and m are integers) as one unit.