JP2820068B2 - Image data synthesis display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data synthesizing and displaying apparatus, and more particularly to an image data synthesizing and displaying apparatus for displaying data of a frame memory together with other data such as an external video.

[0002]

2. Description of the Related Art Conventionally, this type of image data synthesizing and displaying apparatus has been disclosed in, for example, Japanese Patent Publication No. 89-15116,
As shown in No. 681, video data and sub-screen data input from the outside are superimposed and displayed on data written in the frame memory.

FIG. 8 is a block diagram showing a configuration example of a conventional image data synthesizing and displaying apparatus. In FIG. 8, a drawing processor 1 performs graphic drawing on a frame memory 2. In this case, if a window is to be displayed, window drawing is also performed in superposition with graphic drawing. On the other hand, the external video I / F 33 receiving the external video 101
Performs the drawing by superimposing the contents of the external video 101 on the frame memory 2 with the graphic drawing at the control timing of the drawing processor 1. The frame memory 2 reads out the drawing content to the display device 4 as a digital video 103 in TV synchronization. The display device 4 is a digital video 1
03 is displayed.

In addition, this type of image data synthesizing and displaying apparatus generally has a dedicated frame memory other than a frame memory for superimposing and displaying window display data and externally input video display data. These window data and external input video data are drawn in the dedicated frame memory, and these data may be switched and displayed.

For example, JP-A-59-222888 and JP-A-58-177635 disclose frame memory section image data and external input video and window display image data corresponding to X and Y addresses on a screen. There is a description example of technology for switching and displaying. FIG. 9 shows Japanese Patent Application Laid-Open No. 59-2228.
FIG. 1 is a block diagram showing an example of an image data synthesizing and displaying apparatus according to JP-A-88-88 and JP-A-58-177635.

In FIG. 9, upon receiving a drawing command 102 from the CPU 6, the drawing processor 1 performs graphic drawing on the frame memory 2. On the other hand, the window drawing data or the external video 121 is input to the window or external video display frame memory 25 to perform drawing. The CPU unit 6 includes an X register 8 and a Y register 9.
XY coordinates on the screen are set as display start points. The frame memory unit 2 stores the frame memory unit image data 107
Is output to the read-out switching unit 37 in TV synchronization.

When the value of the X register 8 matches the value of the X counter 10 and the value of the Y register 9 matches the value of the Y counter 11, the window or external video display frame memory 25 stores the image for window display. The data or external input video 120 is read out in synchronization with the TV, and the switching unit 3
7 is output.

The switching section 37 normally outputs the frame memory section image data 107 as a digital video 103. When the value of the X register 8 matches the value of the X counter 10 and the value of the Y register 9 matches the value of the Y counter 11, the window display image data or the external input video 120 is output as the digital video 103. I do.

On the window or on the external video display frame memory 25, a portion corresponding to one horizontal line
Window display image data or external input video 12
When the output of 0 ends, the switching unit continues to output the frame memory unit image data 107 as the digital video 103 until the next time the value of the display start position of the X register 8 matches the value of the X counter 10.

[0010]

However, in the conventional image data synthesizing and displaying apparatus shown in FIG. 8, the image is directly drawn on the frame memory 2 under the control of the drawing processor 1. Therefore, a circuit for controlling timing for graphic drawing and controlling an external video drawing position is required.
In addition, a program for changing window drawing performed by the basic OS and adding control due to addition of hardware is required. In the case of performing the superimposed display by changing the drawing method in the frame memory 2 as described above, there is a problem that the standard hardware and the graphic interface equipped with the software must be significantly changed.

When moving the displayed window display data to another place on the display screen, graphic drawing is performed again at the position where the window display data was drawn on the frame memory 2 before the movement. There is a need. Particularly, when the window is moved frequently, there is a problem that the load on the drawing processor 1 increases.

On the other hand, in the image data synthesizing display apparatus shown in FIG. 9, the X and Y coordinates on the screen are designated to simply switch between the frame memory section image data 107 and the window display image data or the external input video 120. Do. Generally, when performing high-definition display of a display device, it is necessary to increase the video frequency, which is the ON / OFF repetition frequency for each pixel of display. In this case, parallel processing of a plurality of pixels is required internally.

However, in the image data synthesizing and displaying apparatus shown in FIG. 9, since the X and Y coordinates on the screen are simply switched to each other, when parallel processing of a plurality of pixels is performed, one pixel It is difficult to specify the display position for each. Therefore, there is a problem that the window cannot be moved smoothly. Further, for the same reason, when the window display frame memory is applied to the cursor display, there is a problem that an accurate position cannot be displayed.

According to the present invention, the video frequency is increased for high-definition display of a display device, and a display position can be specified for each pixel even when parallel processing of a plurality of pixels is performed internally. It is an object of the present invention to provide a simple image data synthesizing display device.

[0015]

To achieve the above object, an image data synthesizing and displaying apparatus according to the present invention comprises an X counter (10) for counting a pixel clock and a Y counter (11) for counting a horizontal synchronizing signal. X register (8) for setting the start position of window display on the X axis of the display screen, Y register (9) for setting the start position of window display on the Y axis of the display screen, X register and Y register
The CPU (6) for setting the numerical values stored in the registers, the memory (5) for storing the image data of the window display, and the numerical values stored in the X counter, the Y counter, the X register, and the Y register are stored in the memory. Address generating means (14) for generating an address for simultaneously reading image data of N pixels (N is a natural number of 2 or more), and N pixels based on the position of the X axis specified by the numerical value held in the X register Output control means (1) for outputting image data of
5) image synthesizing means (12) for inputting image data of one frame every N pixels and inputting image data of N pixels output by the output control means and synthesizing the respective image data; And a parallel / serial conversion means (13) for sequentially converting the image data for each N pixels synthesized by the image synthesis means to one pixel image data and outputting the image data, and matching the numerical values held in the X register and the Y register. It is characterized in that the image data stored in the memory is superimposed on the image data of one frame at the coordinate position by specifying a position in units of one pixel, and a window display of the superimposed image data for each pixel is enabled.

Further, the above-mentioned image data synthesizing and displaying apparatus has a frame memory (2) for storing one frame of image data, and reads out the image data for every N pixels of one frame from the frame memory. It is preferable to use a bitmap memory for cursor display, store image data of an input video input from the outside in the memory, and superimpose the image data of the input video on image data of one frame to display a window.

The output control means (15) includes a multiplexer (20) for selecting and outputting input bits of the window display image data (106), and a MUL control signal (118) for selecting the multiplexer. ) And a pixel clock (10).
D / FF (22) that latches input image data (122) according to 9) and outputs latched image data (123)
And two input ports, and one of the image data (12
It is preferable to include a selector (23) for selecting and outputting either 2) or the other image data (123), and an SEL control unit (24) for controlling a selector selecting operation.

[0018]

Therefore, according to the image data synthesizing and displaying apparatus of the present invention, the pixel clock is counted, the horizontal synchronizing signal is counted, and the start position of the window display is indicated by X on the display screen.
The start position of the window display is set on the Y axis of the display screen. The CPU sets a numerical value as a start position of the window display, stores the image data of the window display in the memory, and converts the image data of N pixels stored in the memory from the numerical values held in the X and Y counters and the X and Y registers, respectively. An address for reading at the same time is generated. Controlling and inputting the output of the image data of N pixels based on the position of the X axis specified by the numerical value held in the X register, inputting the image data in one frame every N pixels,
The respective image data are combined. Therefore, the image data stored in the memory can be superimposed on the image data of one frame at the coordinate position coincident with the numerical values held in the X register and the Y register in units of one pixel.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an image data synthesizing and displaying apparatus according to the present invention. 1 to 7 show an embodiment of an image data synthesizing and displaying apparatus according to the present invention.

In the following description, the writing of the original image data into the frame memory is simply referred to as “drawing”. Of the drawing of the image data by the drawing processor, the drawing other than the drawing of the window data and the drawing of the external video data is referred to as “drawing”.
"Graphic drawing" is used to identify both.

The image data synthesizing and displaying apparatus of the embodiment is shown in FIG.
As shown by a dashed line in FIG. 2, the present invention can be broadly divided into characteristic components of the present invention and other components. The latter of these two classes,
CPU unit 6, drawing processor 1, frame memory unit 2, X register 8, Y
It comprises a register 9, an X counter 10, a Y counter 11, and a display device 4. In the former, the window display frame memory 5, the image data synthesizing unit 12, the P /
It comprises an S unit 13, an address generation unit 14, and a window output control unit 15.

In each of the above components, the drawing processor 1 is an image processing unit that performs graphic drawing on the frame memory unit 2. The frame memory 2 is a storage unit for storing image data including a color palette. The image data stored here is stored in the frame memory image data 1
07 is output to the image data synthesizing unit 12.

The CPU unit 6 is a central processing unit that outputs the drawing command 102 to the drawing processor 1 and sets XY coordinates on the screen as a display start point in the X register 8 and the Y register 9.

The X register 8 and the Y register 9 count and store the display start point of the window image data 105 on the display screen on the display device 4 as XY coordinate points. The value stored in these registers is C
Set by PU6. The X counter 10 counts the pixel clock 109, and the Y counter 11 counts the horizontal synchronization signal 110.

The window display frame memory 5 is a temporary storage memory for storing image data for window display. The image data stored in the window display frame memory 5 is window image data 105. Reading of the stored image data at a predetermined position of the window image data 105 is based on the signal of the read address 111. The read image data is output as window display image data 106.

The image data synthesizing section 12 is an image processing section for synthesizing the frame memory section image data 107 and the window display data 112 output from the window output control section 15. The synthesized image data is output as a parallel digital video signal 108. The image data synthesizing unit 12 reads out the image data 107 of the frame memory unit for four pixels at a time in the present embodiment from the frame memory unit 2 in synchronization with the TV.

The P / S unit 13 is a parallel / serial conversion circuit for converting the parallel digital video signal 108, which is a parallel signal, into a serial signal. The converted digital video signal is a digital video signal 103
Is output as

The address generator 14 generates an address signal obtained by dividing the image data for each frame displayed on the display device 4 by XY coordinates, and outputs the read address signal 11.
This is a circuit unit that outputs as 1. The output read address signal 111 is output from the X register 8 and the Y register 1
This is a start position based on the output value of 0, and is a signal synchronized with the output signals of the X counter and the Y counter.

The window output control unit 15 is an image data output control unit that receives the value of the window display image data 106 and the value of the X register 8 as input signals and outputs window display data 112. The window output control unit 15 outputs the window display data 112 for four pixels matching the display position of the window image to the image data synthesizing unit 12 based on the display start position specified by the X register 8 in pixel units. When the window display position is specified in units of one pixel, it is necessary to adjust where each bit of the window display data 112 is allocated. The window output control unit 15 has a function of performing this adjustment.

FIG. 2 is a block diagram showing one embodiment of a more detailed circuit configuration of the window output controller 15. The window output control unit A150 for processing pixel 0 to the window output control unit D153 for processing pixel 3 have the same circuit configuration. Here, the window output control unit A
The values from 150 to the window output control unit D153 indicate which pixel position on the screen corresponds to P, respectively.
X (n) (n = 0 to 3) is defined. Where 4
From the pixel onward, the value obtained by sequentially adding 4 to PX (n), that is, P
X (n) 10+... The window display image data 106 is 4-bit (W0 to W3) data for 4-pixel parallel processing.

The window output control unit A150 will be described. The MUL control unit 21 determines the value of SX113 and PX
The MUL control signal 118 is output from the value of (0) 114. The MUL control signal 118 is a signal for controlling which input bit is to be selected by the multiplexer 20 and output by the operation in the MUL control unit 21. The multiplexer 20 receives the window display image data 106, selects 1-bit image data in the window display image data 106 by control based on the MUL control signal 118, and sends the selected 1-bit image data to the D / FF 22 and the selector 23. Output image data. The D / FF 22 latches input image data in accordance with the pixel clock 109 and outputs the latched image data.

The SEL control unit 24 outputs one signal SX113
And the value of the other signal PX (0) 114 to output the SEL control signal 119. The SEL control signal 119 is SE
This signal is a signal for controlling which input image data of the image data input to the input ports A and B is to be selected and output by the selector 23 based on the processing result in the L control unit 24. The selector 23 receives the SEL control signal 119, selects the data of the port A or B, and outputs the 0th bit of the window display data 112.

Similarly, the window output control unit B15
1 is the first bit based on the signal PX (1) 115, the window output controller C152 is the second bit based on the signal PX (2) 116, and the window output controller D153 is the third bit based on the signal PX (3) 117. Each of the eye window display data 112 is output. The output data of the 0th to 3rd bits forms image data in units of 4 bits.

Next, the operation of the window output control section 15 will be described in detail. FIGS. 3 to 5 are diagrams showing the relationship between the display screen and the internal processing bits when the 4-pixel parallel processing is performed. Usually, in a display device of a TV scanning system,
As shown in FIGS. 3 to 5, display is started in the X direction from the left side of the screen. FIG. 3 shows the frame memory unit image data 10.
This is an example where only 7 is displayed. Numerals 0 to 3 in the drawing indicate bits of the frame memory unit image data 107. In the case of the four-pixel parallel processing, the frame memory unit 2 always reads four pixels (portion surrounded by a solid line in the drawing) at a time. Therefore, bits 0 to 3 of the same frame memory unit image data 107 are always allocated to pixel positions of 0 to 3 (or a value obtained by sequentially adding 4 to each) in the drawing.

Here, a value indicating the X coordinate of the display start position set in the X register 8 is defined as SX, and a value indicating the Y coordinate of the display start position set in the Y register 9 is similarly defined as ST. FIG. 4 shows a window display in FIG.
This is the case where the display start position SX is SX = 1. W0 to W3 indicate bits of the window display data 112. in this case,
The bit of W0 is assigned to the position of pixel 1 (or a value obtained by sequentially adding 4 to 1) on the display screen. Hereinafter, similarly, W1 and W2 are allocated. Pixel position 0 on the display screen
, The bit 0 of the frame memory unit image data 107 is displayed as it is, but the bit of W3 is allocated to the pixel position of the value obtained by sequentially adding 4 to the pixel position 0.

FIG. 5 shows a case where the window is displayed in FIG. 3 and the pixel position SX is SX = 3. In this case, the bit of W0 is allocated to the pixel position of the pixel position 3 (or the value obtained by sequentially adding 4 to 3) on the display screen. Further, the bits of the frame memory unit image data 107 are displayed as they are at the pixel positions 0, 1, and 2 on the display screen. The bits W1, W2, and W3 are respectively allocated.

As described above, when the window display position is specified in units of one pixel, the window display data 1
It is necessary to adjust where to allocate each of the 12 bits. The function of the window output control unit 15 performs this adjustment.

Next, a description will be given of a processing procedure for image data synthesis and display. In the case of the 4-pixel parallel processing, as described above with reference to FIG. 3, the display pixel position is repeatedly operated by sequentially adding 4 to the values of 0 to 3.
This indicates that considering the binary number, only the lower two bits need to be considered. The upper bits are used for repetition. Therefore, SX considers only the value of the lower two bits here.

The MUL control unit 21 calculates PX (n) (where n = 0 to 3) -SX + 4, ignores overflows of 3 bits or more, and outputs any one of 0 to 3 as the MUL control signal 118. Output the calculated value.
The multiplexer 20 receives the MUL control signal 118 having any value from 0 to 3 and selects and outputs one bit of the window display image data 106 from W0 to W3. When this operation is applied to FIG. 5, it is understood that W1 is selected at 0-34 = 1 at the display position of the 0th pixel.

Hereinafter, similarly, the first pixel, the second pixel, and the third pixel are selected. However, at the display position of the third pixel,
3-3 + 4 = 4, and an overflow bit is set. Since this is ignored, W0 is selected as a result.
Similarly, when this operation is applied to FIG. 4, it can be seen that W3 is selected at the display position of the 0th pixel, where 0-1 + 4 = 3. Hereinafter, similarly, the first pixel, the second pixel itself, and the third pixel are selected.

In this way, the multiplexer 20
The bit of the window display image data 106 is selected and output to the select 23 and the D / FF 22. on the other hand,
The selector 23 inputs the multiplexer output data 122 which is the output of the multiplexer 20 to the port A, and inputs the output D / FF output data 123 of the D / FF 22 to the port B.

The SEL control unit 24 determines that SX ≦ PX (n)
(Where n = 0 to 3) SEL to select port A
The control signal 119 is output. SX> PX (n)
(Where n = 0-3) SEL to select port B
The control signal 119 is output.

Therefore, when SX = 1 in FIG. 4, the window output control unit A150 has D / FF2 since 1> 0 because 1> 0.
The port B, which is the output of No. 2, is selected and output as the 0th bit (0th of the display pixel position) of the window display data 112. On the other hand, in the window output control unit B151,
Since 1 = 1, the port A which is the output of the multiplexer 20 is selected and output as the first bit of the window display data 112 (first display pixel position). Similarly, the window output control unit C152 and the window output control unit D153 also perform output.

The above procedure will be described with reference to a timing chart. 6 and 7 show the window output control unit 15.
5 is a timing chart showing the operation of FIG. 4 when SX = 1 in FIG. FIG. 6 shows the 4-bit window display image data 106 and the multiplexers 20, 20, 2 of the window output control units A, B, C, D in FIG.
The timing relationship between the data of each of 0, 20, and the D / FF 22 and the pixel clock 109 is shown. Also, the relationship between the timing at which the value held in the X register 8 matches the value held in the X counter 10 and the display position of the display screen is shown in the relationship between the number of bits of the window display data 112 selectively output by the selector 23. ing.

Here, the window display image data 10
6 at a time, WV0,
WV1,... Each bit of the 4-bit data is referred to as WV0-W0, WV0-W1,... Here, W0, W1, and W3 are the same as those already defined in FIGS. These window display image data 106 are stored in the window display frame memory 5 in synchronization with the rise of the pixel clock 109.
Read from.

In the window output control unit A150,
The multiplexer 20 selects WV0-W3. Upon receiving the multiplexer output data 122 as its output, D /
The FF 22 outputs D / FF output data 123 that is delayed from the multiplexer output data 122 by one cycle of the pixel clock 109. The selector 23 selects this output and outputs it as the 0th bit (0th of the display pixel position) of the window display data 112. On the other hand, in the window output control units B, C, and D151 to 153, the respective selectors 23 output the multiplexer output data 122
And outputs it as the corresponding bit of the window display data 112.

Accordingly, in the first output, the 0th display pixel position is not output, and the image data synthesizing section 12 outputs the frame memory section image data 107 as it is.
The first and subsequent display pixel positions are window display data 11
2 is output, and the image data synthesizing unit 12 displays this. Thus, the value of the window display frame memory 5 is displayed. FIG. 7 is obtained by rewriting FIG. 4 with the contents of FIG. The same processing is performed in the case of FIG.

In the image data synthesizing and displaying apparatus constituted by the above components, the CPU 6 outputs a drawing command 102 to the drawing processor 1. This drawing command 10
2, the drawing processor 1 performs graphic drawing in the frame memory unit 2 corresponding to the screen. When a window is displayed, the window drawing data 105 is also drawn in the window display frame memory 2. The frame memory unit 2 reads out the image data 107 of the frame memory unit for four pixels at a time in the X direction and outputs the image data 107 to the image data synthesizing unit 12 in synchronization with the TV.

On the other hand, the address generation unit 14
When the value of 0 matches the value of the X register 8 and the value of the Y counter 11 matches the value of the Y register 9, the read address 111 is output to the window display frame memory 5. The output of the read address 111 is performed until the display is completed in an amount corresponding to one horizontal line on the window display frame memory 5. For example, if the window size is 64 × 64 pixels on the display screen, 64
The read address 111 is generated and output until the window display image data 106 for pixels is output.

The window display frame memory 5 receives the read address 111 and outputs window display image data 106 for four pixels at a time in the X direction. The window output control unit 15 receives the window display image data 106 and the value of the X register 8, and outputs the window display data 112 of four pixels suitable for the display start position specified by the X register in pixel units. Data synthesis unit 12
Output to

The image data synthesizing section 12 synthesizes the frame memory section image data 107 and the window display data 112, and outputs a parallel digital video 108. The P / S unit 13 performs parallel / serial conversion of the parallel digital video 108 and
Is output and displayed on the display device 4.

In addition, in FIG.
Outputs the window drawing data 105, but it is also possible to generate the window drawing data 105 by an external video and process it in the same way. In this case, the external video image is displayed in the window of the display screen. Further, by changing the window display frame memory 5 to a cursor display bitmap memory, it is also possible to display the cursor in the same manner.

Although the above embodiment is an example of a preferred embodiment of the present invention, the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention. For example, in the present embodiment, the case of 4-pixel parallel processing has been described, but it is apparent that the present invention can be applied to parallel processing of any number of pixels by the same method.

[0054]

As is clear from the above description, the image data synthesizing and displaying apparatus of the present invention counts the pixel clock, counts the horizontal synchronizing signal, and determines the start position of the window display on the X axis of the display screen. Then, the start position of the window display is set on the Y axis of the display screen. The CPU sets a numerical value as a start position of the window display, stores the image data of the window display in the memory, and stores the image of N pixels stored in the memory from the numerical values held in the X and Y counters and the X and Y registers, respectively. Generate an address for reading data simultaneously. Controls and inputs the output of image data of N pixels based on the position of the X axis specified by the numerical value held in the X register, inputs image data in one frame for each N pixels, and outputs each image data. Is synthesized. The image data stored in the memory is superimposed on the image data of one frame at the coordinate position coincident with the numerical values held by the X register and the Y register by specifying the position in units of one pixel, so that the video frequency can be displayed with high definition. , And the display position can be designated for each pixel even when the parallel processing of a plurality of pixels is performed internally.

Therefore, even when the parallel processing of a plurality of pixels is performed internally, the window display can be smoothly moved. Further, when the window display memory is applied to the cursor display, an accurate one-pixel A cursor can be displayed at the position.

[Brief description of the drawings]

FIG. 1 is a circuit configuration block diagram showing an embodiment of an image data synthesizing and displaying apparatus according to the present invention.

FIG. 2 is a block diagram showing a more detailed circuit configuration example of a window output control unit 15 of FIG. 1;

FIG. 3 is a diagram illustrating a relationship between a display position on a display screen and internal processing bits with respect to a scanning direction, and illustrates a case where display is performed using only image data in a frame memory unit.

FIG. 4 shows a case where the window display start position is SX = 1 in the relationship of FIG. 3;

FIG. 5 shows a case where the window display start position is SX = 3 in the relationship of FIG. 3;

FIG. 6 is a timing chart of the window output control unit 15 of FIGS. 1 and 2;

FIG. 7 is a relationship diagram between a display screen and internal processing bits when a window display start position is SX = 1.

FIG. 8 is a circuit block diagram showing an example of a conventional image data synthesizing and displaying device.

FIG. 9 is a circuit block diagram showing another example of the conventional image data synthesizing and displaying device.

[Explanation of symbols]

 Reference Signs List 1 drawing processor 2 frame memory unit 4 display device 5 window display frame memory 6 CPU unit 8 X register 9 Y register 10 X counter 11 Y counter 12 image data synthesizing unit 13 P / S unit 14 address generating unit 20 multiplexer 21 MUL control Unit 22 D / FF 23 selector 24 SEL control unit 103 digital video 105 window drawing data 106 window display image data 107 frame memory unit image data 108 parallel digital video 109 pixel clock 110 horizontal synchronization signal 111 read address 112 window display data 113 SX 114 PX (0) 115 PX (1) 116 PX (2) 117 PX (3) 118 MUL control signal 119 SEL control signal 122 Multiplexer Output data 123 D / FF output data 150 Window output controller A 151 Window output controller B 152 Window output controller C 153 Window output controller D

Continued on the front page (51) Int.Cl. ⁶ Identification code FI G09G 5/36 530 G09G 5/36 530L

Claims (1)

(57) [Claims] An X counter for counting a pixel clock; a Y counter for counting a horizontal synchronization signal; and an X register for setting a start position of a window display on an X axis of a display screen. A Y register (9) for setting the start position of the window display on the Y axis of the display screen; a CPU (6) for setting values stored in the X register and the Y register; and storing image data of the window display. Memory (5) for simultaneously reading image data of N pixels (N is a natural number of 2 or more) stored in the memory from the numerical values held by the X counter, the Y counter, the X register, and the Y register. Address generating means (14) for generating an address of the image data of N pixels based on an X-axis position designated by a numerical value held in the X register. Output control means (15) for outputting the image data of each frame, and inputting the image data of one pixel every N pixels, and inputting the image data of N pixels output by the output control means, and synthesizing the respective image data. And a parallel / serial conversion unit (13) for sequentially converting the image data for each N pixels synthesized by the image synthesis unit into image data of one pixel and outputting the image data. The image data stored in the memory is superimposed on the image data of the one frame at the coordinate position coincident with the numerical values held by the register and the Y register in a pixel-by-pixel position, and the superimposed image for each pixel is superimposed. The data can be displayed in a window, and the output control means (15) outputs the image data for window display.
A multiplexer that selects and outputs the input bits of the data (106)
Lexer (20) and for selecting operation of the multiplexer
Control unit that outputs a MUL control signal (118)
(21) and the input image data by the pixel clock (109).
Data (122) and the latched image data (1
D / FF (22) that outputs 23) and two input ports
Image data (122) or the other image data (122).
Select to select and output any of image data (123)
(23) and SEL for controlling the selection operation of the selector
An image data synthesizing and displaying apparatus , comprising: a control unit (24) .