JP2720761B2 - Semiconductor integrated circuit test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (IC).
Related to a test device (tester) for testing the electrical characteristics of
The Rupa Tanmemori unit incorporated in the IC tester an IC tester having a function of self-diagnosis.

[0002]

2. Description of the Related Art A conventional IC tester supplies a power supply voltage and a predetermined input signal to an IC under test, and outputs an output signal supplied from the IC under test in response to these input signals in advance. Generally, the electrical characteristics of the IC under test are tested by comparing with the expected value stored in the pattern memory unit.

Referring to FIG. 3, which is a block diagram showing a configuration of a pattern memory section of a conventional IC tester and a main portion of a peripheral portion thereof, a conventional IC tester includes a control section 1, a timing generation section 2, a pattern control section 3, switching unit 4, pattern memory unit 5,
The control unit 1 is provided with a waveform forming / comparing unit 7 and a pin electronics unit 8, and a test program stored in a memory unit (not shown) is supplied via a data bus 11.
In response to the instruction of the test program, predetermined signals are supplied to the pattern control unit 3, the switching unit 4, the pattern memory unit 5, the waveform formation comparison unit 7, and the pin electronics unit 8 inside the IC tester. The timing generator 2 generates and supplies a basic timing signal that is used to generate a predetermined timing to the controller 1, the waveform forming / comparing unit 7, and the pattern controller 3. The pattern control unit 3 responds to the control signal 14 supplied from the control unit 1 and
The address data is generated at a predetermined cycle time on the basis of the timing supplied from. Referring to FIG. 4A showing an example of a test pattern in this conventional example, this test pattern is an IC under test.
, And corresponds to the input / output logical value of the IC under test, that is, a truth table. The pattern memory unit 5 supplies the stored test pattern to the waveform forming / comparing unit 7 under the control of the pattern control unit 3.

[0004] In the waveform forming and comparing unit 7 pattern Nme memory unit 5
The test pattern supplied from the controller 1 is formed into a waveform at a predetermined timing in response to an instruction from the control unit 1 and supplied to the pin electronics unit 8. Referring to Figure 4 showing an example of an output waveform of the pin electronics unit in the conventional example (b), the pin electronics unit 8 is the control signal of the control unit 1 amplifies the Te Sutopata down the voltage level of Tokoro <br/> constant Is supplied to the IC under test. The IC under test operates based on these signals, and the corresponding signals are supplied to the waveform forming / comparing unit 7 via the pin electronics unit 8. In the waveform forming / comparing unit 7, these output signals are used as the input / output logical values of the pattern memory unit 5 , that is, the expected values.
The test pattern is compared with a predetermined sampling timing, and the result is supplied to the control unit 1 where the quality of the IC under test is determined.

Referring again to FIG. 4A, the test pattern is 1 to 256 in the row direction corresponding to the number of pins of the IC under test.
Is divided, the address value 0 in the column direction, ..., X, X +
1,..., 1M are set, and a predetermined test pattern
Has been written. Referring also to FIG. 4B, for example, at pins m and n, addresses x, x +
.., X7 correspond to the pattern shown in FIG. 4A, and pin m corresponds to 1 (high level), 0 (low level), 1, 0,. Has 1,1,
Waveform signals of 0, 0, 1, 0, 0, 0 are output from the waveform forming / comparing unit 7.

[0006] On the other hand, as ICs become more highly integrated and multifunctional, IC testers for testing the electrical characteristics of these ICs have been increased in the number of pins and speed. The capacity of the test pattern used for the electrical characteristic test is required to be several millions in order to achieve high integration, multi-functionality and improved reliability of the IC. In order to cope with such a situation, the pattern memory section of the IC tester has come to have a capacity of several million patterns. Diagnosing the electrical characteristics such as the data retention and the speed characteristics of the pattern memory unit 5 of the IC tester is also important from the viewpoint of ensuring the reliability of the test. The diagnosis of the pattern memory unit is performed by, for example, checking the pass / fail by writing and reading a test pattern by the control unit 1 and an IC under test.
There is a method in which two pairs of test pins are short-circuited on a test board on which a test signal is mounted, a test signal is supplied from one pin, and the signal is received by the other pin to check the quality.

First, the self-diagnosis technique of the pattern memory unit by the former control unit will be described. The control unit 1 is a 16-bit or 32-bit computer. Here, a case will be described in which the capacity of the pattern memory unit 5 is 256 pins × 1 million pattern (hereinafter, referred to as 1M), and the data that can be processed at one time by the computer of the control unit 1 is 32 bits. Referring to Figure 6 showing a data storage area of the pattern memory, the pattern memory section 5 is made to correspond to the row direction of the memory 256 of the pin, when this 32 divides 1
The blocks become 131,072 blocks having 32 bits. With respect to these blocks, the computer of the control unit 1 writes test patterns in the pattern memory unit 5 while controlling the pattern control unit 3 and the switching unit 4, and then reads out the written test patterns to read out the written test patterns. Is determined.

Referring to FIG. 5 (a) showing a timing chart for explaining a write operation and FIG. 5 (b) showing a timing chart for explaining a read operation, the control unit 1 performs processing. According to the cycle (Fig. 5
(A) (A)) Address data for diagnosing the pattern memory unit 5, that is, address Am and column numbers B1, B2,
, B8, column numbers B1, B2 at address A (m + 1),
Are transmitted to the pattern control unit 3 ((b) in FIG. 5A). Further diagnosed pins,
That is, the switching unit 4 controls the switching so that the column numbers B1, B2,...
(A) (c)). The pattern control unit 3 addresses the pattern memory unit 5 with the supplied address data Am, A (m + 1),... ((D) in FIG. 5A). In this state, the control unit 1 controls the switching unit 4 while sequentially controlling 32 pins of text.
Write the stop patterns B1W, B2W,... From the data bus 11 to the pattern memory unit 5 up to the final address (FIG. 5).
(E) of (a)).

Further, the control unit 1 reads the test pattern written in the pattern memory unit 5 while controlling the pattern control unit 3 and the switching unit 4 again. In the read process, the control unit 1 supplies the address data to the pattern control unit 3 ((a) in FIG. 5B) and controls the switching unit 4 via the data bus 11 in the same manner as the write process described above. In addition to selecting the pins to be read, test patterns for 32 pins are sequentially read from the pattern memory unit 5 up to the final address ((b) to (d) in FIG. 5B).
The control unit 1 compares these read test patterns with the written test patterns and determines whether or not they match.

Another example using a technique similar to the above-mentioned conventional technique is described in Japanese Patent Application Laid-Open No. Sho 59-146499. Referring to FIG. 8, a memory test apparatus described in the same publication whose main part is shown in a block diagram in FIG. 8 is a test processor 1, a pattern generator 2, a timing generator 3, a fail memory 4, a comparator 5, and a multiplexer. 6, the test processor 1, the pattern generator 2, the timing generator 3, and the fail memory 4 are commonly connected via a bus (BUS), and the strobe STB of the timing generator is provided.
Is supplied to the pattern generator 2, the comparator 5, and the fail memory 4. The output of the pattern generator 2 is supplied to the comparator 5 and the multiplexer 6, and the output of the comparator 5 is supplied to the multiplexer 6. The output of the multiplexer 6 is configured to be supplied to the fail memory 4.

This memory test apparatus includes a pattern generator 2
, An address A and an expected value B are generated at a test rate, the expected value B and the output of the comparator 5 are switched by the multiplexer 6, and the test pattern of the expected value B is written in the fail memory 4. Written test patterns are read in Tesutopurossa 1 through BUS, the expected value B Test
Self-diagnosis is performed in comparison with the topapattern .

Next, a case where the pattern memory unit 5 is diagnosed while outputting signals from the electronics unit 8 will be described. Referring to FIG. 7, which shows an example of a test pattern used for the self-diagnosis processing of the pattern memory unit by the pair of test pins, one surface of the pattern memory unit 5 of the IC tester is (number of pins) × (depth of the pattern). A pattern memory having a plurality of configured surfaces (in this example, three surfaces of pattern memories A, B, and C) is used.

A drive signal (DRV) as an output signal to be supplied to the pin electronics section 8 by combining these three test patterns and a pin electronics section 8 are provided.
, The logic of the expected value signal (CMP) for comparison with the output signal of the IC under test (not shown), that is, the high level is set to 1 and the low level is set to 0.

For example, when pattern memories A, B and C are 0, 0 and 1, respectively, DRV is 0 and CMP
Is masked (MASK). Also, the pattern memory A,
When B and C are 0, 0 and 0, respectively, DRV is high impedance (Hiz), and CMP is set to be an expected value of low (L) level. Diagnosis of the pattern memory unit 5 based on these signals is as follows.

That is, since the diagnosis is performed not on the IC to be inspected but on the pattern memory section 5, a pair of test pins provided for each block P of the pin electronics section 8 is used.
A short 16 is made on a test board (not shown), and one of the pins is set to the DRV mode and the other pin is set to the CMP mode so that the pin output in the DRV mode is supplied to the pin in the CMP mode. This signal is returned to the waveform forming and comparing unit 7 from the block P again, and Tesutopata down expectations created pre Ji order to match the logic of the DRV signal by three surfaces of the pattern memory of FIG. 7 described above The comparison is made in the waveform forming / comparing section 7 and the diagnosis of the pattern memory section 5 is made.

[0016]

The above-described conventional IC tester has the following drawbacks because it does not have a function of diagnosing the operation of the pattern memory unit. That is, IC
The self-diagnosis function of the pattern memory unit by the control unit inside the tester compares the processing bit width of the computer used for the control unit, that is, 16 bits and 32 bits, with the number of pins corresponding to the data width of the pattern memory unit. Then
The pattern memory section is much larger. Therefore, it must be divided into blocks in the row direction of the pattern memory section, that is, the pin direction by the processing bit width of the computer. The pattern memory shown in FIG. 6 has one surface (256 pins × 1).
Referring to the case of M), there are 8,387,328 blocks.

[0017] For each of these blocks, switching control for selecting the pin group, the test pattern write, there have needs to perform reading <br/> seen out and determined. Generally, the arithmetic processing of the computer used for the control unit, that is, the instruction processing time requires several micro hours to several tens of micro hours. The address is sent and the test
In order to process the button writing, the test pattern reading, the determination, and the like, the memory diagnostic processing time eventually requires tens of minutes to several hours, and the efficiency of the operation time of the IC tester decreases.

Further, in the diagnosis of the pattern memory unit or the file memory by the control unit, the processing time of the computer and the pattern generation cycle time of the IC tester are significantly different.

As described above, the processing time of a computer requires several micro-hours to several tens of micro-hours, whereas the pattern generation cycle time of an IC tester is, for example, 10 nanoseconds for an IC tester corresponding to an operating frequency of 100 MHz. Fast. It is the speed characteristic that poses a problem in the processing time of the pattern memory unit . Therefore, with the processing ability of a computer having such a low operating speed, it is not possible to diagnose the characteristic of the pattern memory unit corresponding to the actual operation time of the IC. There were serious disadvantages.

On the other hand, when the contents read from the pattern memory unit 5 are output from the electronics unit 8 and diagnosed with a pair of pins, the diagnosis corresponding to the actual operation time described above is possible. However, it is irrational to store the expected value, which is a reference for judging the quality of the diagnosis, in the pattern memory unit 5 to be diagnosed, because of the quality of the diagnosis result. Further, in the case of diagnosis of a memory pattern unit configured by a multi-sided memory shown in FIG. 7, since the types of test patterns used are increased, the time for storing these test patterns becomes longer, and the IC tester becomes longer. However, there is a disadvantage that the efficiency of the operation time is reduced. Further, there is a drawback that it is difficult to identify a faulty portion due to a path of a waveform forming / comparing section, a pin electronics section, and a pair of pattern memories.

SUMMARY OF THE INVENTION An object of the present invention is to provide an IC tester capable of reducing the processing time of the self-diagnosis of the pattern memory unit and performing the self-diagnosis according to the actual operation specifications. Is to do.

[0022]

IC testing device of the present invention SUMMARY OF THE INVENTION has at least the same number of tester pins and output pins of tested semiconductor devices, patterns built-out group Dzu a predetermined test program supplied from an external memory A test pattern previously stored in a memory unit is supplied to the semiconductor device under test via the tester pin to test the electrical characteristics of the semiconductor device under test, and also has a function of self-diagnosis of the pattern memory unit. From the built-in timing generator
The self-diagnosis test is performed by the supplied timing signal.
A test pattern generator for generating a pattern , wherein a number of memories corresponding to the tester pins are arranged in a row direction and a number of memories corresponding to a predetermined number of addresses are arranged in a column direction. , The test pattern
The self-signal output in response to a predetermined control signal from the generator.
Yourself data bus for transmitting the test pattern for diagnosis is arranged in the bit width of the number corresponding to the prior SL tester pin, wherein at the time of self-diagnosis with respect to the column direction of the memory specified by a given address, the data A test is performed at a test rate equivalent to the actual operation speed of the semiconductor device under test by writing the test pattern for the self-diagnosis at a time from the bus with the bit width and in synchronization with the timing signal. .

[0023]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, an IC tester according to the present invention includes a control unit 1, a timing generation unit 2, a pattern control unit 3, switching units 4 and 6, a pattern memory unit 5, a waveform forming / comparing unit 7, , Pin electronics section 8 and data bus 1
1 and 12.

A component different from the conventional IC test apparatus shown in FIG. 4 is a switching unit 4 for selectively supplying a test pattern to a pattern memory unit 5 in response to a control signal output from the control unit 1. When, the switching unit to selectively supply the waveform forming and comparing unit 7 in response to a control signal output Tesutopata emissions read from pattern memory unit 5 from the control unit 1 6
A memory data generator 9 for supplying a test pattern generated by a timing signal supplied from the timing generator 2 to the switching / determination unit 10 and the pattern memory unit 5 in response to a control signal output from the controller 1 , Tesutopata down your and switching unit is supplied from the memory data generator 9 6
Test pattern read from the pattern memory unit 5 supplied from the
The tongue and the timing of the timing generating portion 2 is compared while synchronizing with a predetermined timing generated on the basis of a switching-judgment unit 10 that supplies the determination result to the control unit 1, the test pattern of the memory data generator 9 And a data bus 12 for supplying the same to the pattern memory unit 5. The other components are the same as in the conventional example, and a description thereof will be omitted.

FIG. 2 shows a timing chart for explaining the operation of this embodiment, and a pattern memory section 5 which is the same as the conventional example.
Referring to FIG. 6 showing the data storage area of the memory, a diagnosis instruction signal 13 for the pattern memory unit 5 is supplied from the control unit 1 to the memory data generation unit 9, and the diagnosis start address data is transmitted to the pattern control unit 3. 14 (for example, A
m) is supplied. During the execution of the diagnostic processing, the control unit 1 cuts off the path between the data bus 11 and the pattern memory unit 5 by the switching unit 4 and cuts off the path between the pattern memory unit 5 and the waveform forming / comparing unit 6 by the switching unit 6. The switching control is performed so as to perform the switching.

The pattern emission control section 3 operates in synchronization with the memory data generator 9, the address in the pattern memory unit 5 in accordance with pattern generation cycle data Am, A (m + 1) ,
A (m + 2), the ... sequentially supplied (Fig. 2 (a) (i ~
C)). The memory data generator 9 generates a test pattern to be written to the pattern memory 5 in response to signals supplied from the controller 1 and the timing generator 2, and
2 to the pattern memory unit 5 via the line 2 (FIG. 2 (a)).
Of (d)). The data bus 12 has a bit width equal to the number of tester pins, and the pattern control unit 1 performs a test pattern corresponding to the address data Am, A (m + 1), A (m + 2) ,. Can be written into the pattern memory unit 5 at once with the width of the number of tester pins.

Next, in the reading process, the address data read by the control unit 1 is supplied to the pattern control unit 3 (FIG. 2).
(B) (a) (b)), the pattern control unit 3 supplies the read address data to the pattern memory unit 5. The test pattern read in response to the address data is switched by the switching unit 6 by the control signal of the control unit 1 and supplied to the switching / judgment unit 10. The switching / determining unit 10 generates a test generated by the memory data generating unit 9 and written in the pattern memory unit 5.
Topatan is stored, the stored test Topata
Pattern memory unit that will be supplied through the emission and switching-judgment unit 10
5 is compared with the test pattern read from No. 5 to judge the quality ((c) and (d) in FIG. 2B ). The determination result is supplied to the control unit 1 through the signal line 15.

[0028] As described above IC tester of the present invention, control
Address generation cycle of the control unit 1, IC tester test of
Timing generation that generates a timing signal that becomes a rate
Even at the highest test rate of section 2 , pattern memory section 5
The test pattern written in the read, it is possible to execute the quality determination.

Further, the number of logic ICs having a built-in memory is increasing, and accordingly, the logic I
The number of C testers having a memory test function is increasing. Of course, these IC testers can diagnose the pattern memory unit using the above-described memory test circuit, that is, the address, test pattern generation, and comparison functions. That is, by providing a data bus 11 for writing a test pattern to the pattern memory unit 5 in FIG. 1 and a path corresponding to a path for transmitting the test pattern read from the pattern memory unit 5 to the memory test circuits of these IC testers. It is possible.

In the present invention, the self-diagnosis of the pattern memory section has been described. However, the present invention can be easily applied to the self-diagnosis of a fail memory section (not shown) of the IC tester.

[0031]

As described above, the IC tester according to the present invention has a number of memories corresponding to the number of the tester pins in the row direction.
However, in the column direction, the number of memories corresponding to the predetermined number of addresses
Test but to write to pattern down memory portions arranged respectively
The pattern is synchronized with the timing signal of the timing generator.
A memory data generator for generating Te, these Tesutopata
The tester pin number for sending the down to pattern memory unit equal
A data bus having a new bit width, a switching unit for transmitting the test pattern read from the pattern memory unit to the switching / judgment unit, and comparing the test pattern read from this switching unit with the written test pattern to determine whether the test pattern is good or bad. further adding a switching-judgment unit for judging a conventional IC tester, was due you a self-diagnosis of the pattern memory section Unishi. Therefore, there is an effect that the characteristic self-diagnosis of the pattern memory unit can be performed in a short time and at a test rate under the same condition as the actual operation state of the IC.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2A is a timing chart for explaining a write operation in FIG. 1; 2B is a timing chart for explaining a read operation in FIG.

FIG. 3 is a block diagram showing a pattern memory section of a conventional IC tester and a main part of its periphery.

FIG. 4A is a diagram illustrating an example of a test pattern in a conventional example. (B) is a diagram showing an example of an output waveform of a pin electronics section in a conventional example.

FIG. 5A is a timing chart for explaining a write operation in FIG. 3; 4B is a timing chart for explaining the read operation in FIG.

FIG. 6 is a diagram showing a data storage area of a pattern memory unit in FIGS. 1 and 3;

FIG. 7 is a diagram showing an example of a test pattern used for self-diagnosis processing of a pattern memory unit using a pair of test pins in a conventional example.

FIG. 8 is a block diagram showing a main part of a test processor and its peripheral part in another example of the conventional IC tester.

[Explanation of symbols]

 Reference Signs List 1 control unit 2 timing generation unit 3 pattern control unit 4, 6 switching unit 5 pattern memory unit 7 waveform formation / comparison unit 8 pin electronics unit 9 memory data generation unit 10 switching / judgment unit 11, 12 data bus 13 diagnostic instruction signal 14 Diagnosis start address data 15 Timing signal

Claims (1)

(57) [Claims] [Claim 1] input and output pins of tested semiconductor device and has at least the same number of tester pins, the pre-stored test pattern in the pattern memory unit having a built-out group Dzu a predetermined test program supplied from the external memory tester pins in the addition to testing the electrical properties of the tested semiconductor device by supplying the tested semiconductor device, a semiconductor integrated circuit testing apparatus also includes a function of self-diagnosis of the pattern memory section via a built-in timing
The self-diagnosis is performed by a timing signal supplied from the generator.
A test pattern generator that generates a test pattern for
The number of memories corresponding to the tester pins in the row direction is
With respect to the pattern memory section in the column direction the number of memory corresponding to a predetermined number of addresses are respectively disposed, the Te
Output in response to a predetermined control signal from the stop pattern generator.
It said data bus for transmitting the test pattern for the self-diagnosis is provided by the bit width of the number corresponding to the prior SL tester pin, wherein at the time of self-diagnosis with respect to the column direction of the memory specified by a predetermined address, By writing the test pattern for self-diagnosis at once with the bit width and in synchronization with the timing signal from the data bus, a test is performed at a test rate equivalent to the actual operation speed of the semiconductor device under test. Semiconductor integrated circuit test equipment.