JP2652258B2 - CCD output circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD output circuit that detects a signal charge of a charge-coupled device (CCD) and converts it into an electronic signal that can be processed.

[Conventional technology]

Conventionally, as such a CCD output circuit, Japanese Patent Application No. 63-224761
There is something shown in the issue.

This relates to a CCD delay line having a buried channel CCD (BCCD) as a delay line body and a CCD output circuit for reproducing transferred signal charges into an original signal.

First, the structure of this conventional example will be described with reference to FIG.
N on the surface portion of the P-type semiconductor substrate 10 ^- ion implanted layer 11 in the form impurity formation, further buried in the area A in the drawing by the gate electrode is stacked for charge transfer through a gate oxide film A channel CCD (BCCD) is formed, and the area A constitutes a main part of the delay line.

An N ^{+ type} impurity layer 12 is formed at the end of the ion implantation layer 11, and a gate electrode is formed on the gate oxide film following the impurity layer 12.
13, 14, 15, and 16, an N ^{+ -type} impurity layer 17 is formed on the surface portion of the P-type semiconductor substrate 10 following the terminal portion of the gate electrode 16, and an output circuit described later is formed on the impurity layer 17. Connected. The gate electrodes 13, 14, 15, and 16 in the region B connected to the N ^{+ type} impurity layer 12 constitute a surface channel CCD (SCCD).

Next, the output circuit will be described. 18 and 19 is a differential amplifier, the connected N ⁺ form impurity layer 17 to the inverting input contact of the differential amplifier 18, the non-inverting bias voltage V _B of the input contacts to 3 volts is applied, and an inverting input contact output A switched-capacitor integrator is formed by connecting a capacitance element 20 and an analog switch 21 in parallel between the contacts. The differential amplifier 19 forms a buffer amplifier by connecting a non-inverting input contact and an output contact and connecting an output contact to an output terminal 22.

The output contact of the differential amplifier 18 and the non-inverting input contact of the differential amplifier 19 are connected via an analog switch 23, and a capacitive element is connected between the non-inverting input contact of the differential amplifier 19 and the ground contact.
24 are connected, and the analog switch 23 and the capacitive element 24 constitute a sample and hold circuit.

Also, gate electrodes 25 to constitute the terminal portion of the BCCD
The clock signals φ ₂ , φ ₁ , φ _2A for charge transfer at the timing shown in FIG. ₂ are applied to 30, and the signals φ ₂ , φ ₁ are transfer clock signals by a two-phase driving method. φ _2A
Is a clock signal having positive and negative values in synchronism with the signals phi _2. A signal ZG of a constant voltage (zero volt) is always applied to the gate electrode 31, and the potential under the gate electrode 31 is set to a constant potential level corresponding to zero volt.

Further, the N ^{+ -type} impurity layer 12 in the B region remains in a floating state, a signal DG of a constant voltage (3.5 volts) is applied to the gate electrode 13, and a signal of a constant voltage (2 volts) is applied to the gate electrode 16. OG is applied. Also, the gate electrode 14
Signal shifted by 90 ° out of phase relative to the clock signal phi ₁ to phi
_1A , a signal φ _2B having the same phase as the clock signal φ ₂ but slightly deformed waveform is applied to the gate electrode 15 in order to transfer the signal charge more quickly. With these signals,
Under the gate electrodes 31, 13, and 16, potential barriers having depths proportional to the respective applied voltages are set, and the other gate electrodes 2
Under 5,26,27,28,29,30,14,15, potential levels whose depths change by respective clock signals are set.

Next, the operation of the conventional example will be described with reference to the potential profiles shown in FIGS. 3 (a) to 3 (f) according to the respective drive signals shown in FIG. The potential profiles in FIGS. 3A to 3F are shown corresponding to each gate electrode.

First, in order to read each signal charge transferred at a predetermined period τ in synchronization with the transfer clock signals φ ₁ and φ ₂ , unnecessary charges of the capacitive element 20 connected to the differential amplifier 18 at the beginning of each period are removed. At the same time, the potential of the floating diffusion 17 is initialized. For example, at time t ₁ in a certain period, by conducting the analog switch 21 to "H" level to reset RST, a differential amplifier 18
Set both the non-inverting input contact and the inverting input contact to the voltage V _B (3 volts). As a result, 3 volts is also applied to the floating diffusion 17, and then the reset signal RST is returned to the "L" level to shut off the analog switch 21, thereby lowering the potential level below the floating diffusion 17 to 3 volts. Can be initialized to the level corresponding to. At the time of this initialization
As shown in the t ₁ 3 (a), most signal charge q ₁ located on the output side is transferred to the lower gate electrodes 14 and 15, the next signal charge q ₂ are transferred to the lower gate electrode 30, Next signal charge q ₃
Is transferred below the gate electrode 26.

Then, at time t _2, the clock signal phi _1A and phi _2B is "L" level, the clock signal phi _2A is negative "L" level, the Potesharu below the gate electrode 29,30,14,15 since shallower, the signal charges q ₁ are transferred to the floating diffusion 17, the signal charges q ₂ is the gate electrode
31, 13 and below the impurity layer 12. Then, the signal charges q ₁ is charged the capacitor 20, the output signal of the differential amplifier 18
SC ₁ changes as shown.

Then, at time t _3, the signal charges q ₂ under gate electrode 14 is transferred by the clock signal phi _1A becomes "H" level, the clock signal phi _2B becomes "H" level at further time points t ₄ As a result, the signal charge q ₂ is transferred below the gate electrode 15 and at the same time, the BCCD is synchronized with the clock signals φ ₁ and φ _2.
To transfer the next one stage signal charge q ₃ of coming is more transferred to the lower gate electrode 29, 30.

Holds the output signal SC ₁ of the differential amplifier 18 at the said time point the capacitor 24 by the sample-hold signal SH becomes "H" level between more time t ₃ ~t _4, in proportion to the holding signal An output signal SO is generated at an output terminal 22 via a differential amplifier 19.

Thus reading of the signal charges q ₁ being transferred to the bottom gate electrodes 14 and 15 is completed in the process at time t ₁ ~t _4.

Then, at time t _5, a predetermined potential floating diffusion 17 while discarding similarly unwanted charges of the capacitor 20 and the time t ₁ by which the "H" level reset signal RST to conduct analog switch 21 It is set to set the readable state of the next signal charge q _2. Further transferred viewed signal charges q ₂ to the lower gate electrode 15 by the time t ₅ the signal phi _1A to "L" level, the signal charge q by further signal phi _2B the "L" level at time t ₆ Transfer ₂ below floating diffusion 16.

Then, the signal charges q _2, which is transferred to the floating diffusion 17 at time t ₆ is detected by the differential amplifier 18, the charge quantity corresponding to the signal charge q ₂ is charged with a predetermined time constant to the capacitor 20 holds a charge charging the capacitor 24 by the sample and hold signal SH at the time t ₇ the completed becomes "H" level is proportional to the voltage SC _1, 1 to the output terminal 22 via a differential amplifier 19 The signal SO for the stage is output. In this way, the reading processing of the next signal charge q ₂ is completed.

The signal charges that were below the gate electrode 26 at time t ₁
q ₃ is the same as the read processing that is transferred to the bottom gate electrode 30 during the period of time t ₁ ~t ₆ is made.

Such an operation is repeated in synchronization with the cycles of the clock signals φ ₁ and φ ₂ of the BCCD, and outputs a delayed signal for each stage.

[Problems to be solved by the invention]

Thereafter such a conventional CCD output circuit, which at the time t ₄ when shown in FIG. 3 (d), transferred signal charges q ₂ to the potential well below the gate electrodes 14 and 15 of the SCCD, Figure 3 by generating a potential barrier below the gate electrode 14 as shown in (c), so that to separate the signal charge q ₂ from BCCD. However, as shown by the dotted line in the drawing (c), when the potential barrier under the gate electrode 14 is generated, to be transferred all the signal charges q ₂ precisely under the gate electrode 15 to the potential well As a result, there was a phenomenon that some of the charges flowed back to the impurity layer 12 side.

This phenomenon similarly occurs for signal charges sequentially transferred, and improvement in transfer accuracy has been desired.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a CCD output circuit having excellent conversion accuracy. Another object of the present invention is to provide a CCD delay line with good characteristics by providing a CCD output circuit having a selected conversion accuracy.

[Means for solving the problem]

In order to achieve such an object, according to the present invention, in a CCD output circuit that detects a signal charge of a charge-coupled device and converts the signal charge into an electric signal capable of signal processing, the charge-coupled device is configured by a buried channel CCD, Embedded channel CCD
At the end of the device, a floating diffusion composed of a predetermined impurity is formed through a gate portion set to a predetermined fixed gate voltage, and a switched capacitor integrator for detecting an injection charge of the floating diffusion is provided. A signal charge transferred from the charge-coupled device to the floating diffusion by a switched capacitor integrator,
In that case, the gate voltage is determined by the floating operation determined by the reset operation of the switched capacitor integrator.
The voltage of the diffusion is not exceeded.

[Action]

According to the CCD output circuit of the present invention having such a configuration, the impurity layer and the SCCD that connect the conventional BCCD and the SCCD are removed, and the signal charge transferred from the BCCD is removed by the floating diffusion and the switched capacitor integrator. Since the detection is performed, the reverse development of the signal charge as in the related art is eliminated, and the signal can be reproduced with high accuracy.

Further, if the potential of the floating diffusion is reset by the reference voltage of the switched capacitor integrator, the potential of the floating diffusion can be set very accurately. Can be set to a constant level difference with extremely high accuracy. As a result, the signal charge can be controlled with high precision so as not to flow back to the BCCD side by simply setting the potential of the floating diffusion at the same time as resetting the switched capacitor integrator. SCCD for separating diffusion
Is unnecessary, and the structure can be simplified.

Further, it is possible to provide a highly accurate delay line using BCCD as a delay line main body.

〔Example〕

An embodiment of a CCD output circuit according to the present invention will be described below with reference to the drawings. A delay line having a BCCD as a delay line body will be described as an example.

First, the structure will be described with reference to FIG. In FIG.
N on the surface portion of the P-type semiconductor substrate 10 ^- ion implantation layer 11 in the form impurity is formed, further, buried gate electrodes of the charge transfer through the gate oxide film becomes a body portion of the delay line by being stacked Channel CCD (BCCD) is formed. still,
FIG. 1 shows gate electrodes 25, 26, 27, 28, 29 and 30 as a part of the output portion of the BCCD, and drive signals φ ₁ , φ ₂ and φ _2A for transferring signal charges are applied. It has become so. Here, the drive signals φ ₁ and φ ₂ are transfer clock signals in a two-phase drive system, and the signal φ _2A is a clock signal that takes positive and negative values in synchronization with the signal φ ₂ . Further, following the gate electrode 30, a gate electrode 16 to which a constant DC voltage OG is applied is laminated, and an N ^{+ -type} impurity layer 17 is formed on the surface of the P-type semiconductor substrate 10 following the gate electrode 16. It is buried, and an output circuit described later is connected to the impurity layer 17.
In this embodiment, the voltage OG is set to zero volt.

Next, the output circuit will be described. 18 and 19 is a differential amplifier, the connected N ⁺ form impurity layer 17 to the inverting input contact of the differential amplifier 18, the non-inverting predetermined input contact bias voltage V _B is applied to the inverting input contact and output contact A switched capacitor integrator is formed by connecting a capacitance element 20 and an analog switch 21 in parallel with each other.

The differential amplifier 19 has a non-inverting input contact and an output contact connected,
And the output contact is connected to the output terminal 22 so that the buffer
Make up the amplifier.

The output contact of the differential amplifier 18 and the non-inverting input contact of the differential amplifier 19 are connected via an analog switch 23, and a capacitive element is connected between the non-inverting input contact of the differential amplifier 19 and the ground contact.
24 are connected, and the analog switch 23 and the capacitive element 24 constitute a sample and hold circuit.

Next, the operation of this embodiment will be described with reference to the potential profiles of FIGS. 1 (a) and 1 (b) shown in accordance with the respective drive signals of FIG. The potential profiles in FIGS. 1A and 1B are shown corresponding to each gate electrode.

First, in order to read each signal charge transferred at a predetermined period in synchronization with the transfer clock signals φ ₁ and φ ₂ , each period τ
First, unnecessary charges of the capacitive element 20 connected to the differential amplifier 18 are discarded, and the potential of the floating diffusion 17 is initialized. For example, at time t ₁ in a certain period, by conducting the analog switch 21 to "H" level reset signal RST, both the voltage V _B noninverting input contact and an inverting input contact of the differential amplifier 18 ( 3
Volts). As a result, 3 volts is also applied to the floating diffusion 17, and then the reset signal RST is returned to "L" level to set the analog switch 21
, The potential level under the floating diffusion 17 can be initialized to a level corresponding to 3 volts.

As shown in this the time t ₁ of the initialization 1 (a), most signal charge q ₁ located on the output side is transferred to the lower gate electrode 30, the next signal charge q ₂ is the gate electrode 26 The relationship will be transferred down.

Then, at time t _2, the signal phi ₁ is "H" level, phi ₂
There "L" level, the clock signal phi _2A is negative "L" level, as shown in Fig. 1 (b), since the potential under the gate electrode 29, 30 is shallow, the signal charges q ₁ Is transferred across the potential barrier under the gate electrode 16 to the floating diffusion 17 and the signal charge q ₂
Is transferred below the gate electrode 28. As a result, the signal charge q ₁
Is filled in the capacitive element 20, and the output signal _{SC1 of the} differential amplifier 18 is
Changes as shown in FIG.

Then, at time t _3, the output signal SC ₁ of the differential amplifier 18 at the said time point by sample and hold signal SH becomes "L" level held in the capacitor 24 is proportional to the holding signal output The signal SO is generated at the output terminal 22 via the differential amplifier 19.

Then, again it starts the same operation as the time t ₁ at time t _4, then reads processing transferred by coming signal charges,
Similarly, by repeating the processing of the period τ, the signal charges sequentially transferred are read. As described above, according to this embodiment, the impurity layer and the SCCD connecting the conventional BCCD and the SCCD are removed, and the signal charge transferred from the BCCD is detected by the floating diffusion and the switched capacitor integrator. Therefore, it is possible to detect signals with high accuracy by eliminating the backflow phenomenon of signal charges as in the related art.

Further, since the to set the voltage of the floating diffusion 17 to the reference voltage V _B by resetting the switched-capacitor integrator can very accurately realized, combined with fixing the gate voltage OG to V _B> OG relationship , the potential level below the floating diffusion 17 L ₁₇ and the potential level under the gate electrode 16 L
_{The 16} level differences (L ₁₇ −L ₁₆ ) can be made constant.
As a result, by holding the signal charge at this level difference,
The signal charge does not need to flow back to the BCCD side.
For separating CD and floating diffusion
SCCD is not required, and the structure can be simplified, and at the same time, control is greatly simplified.

〔The invention's effect〕

As described above, according to the present invention, the conventional BCCD
The impurity layer connecting the SCCD and the SCCD are removed, and the signal charge transferred from the BCCD is detected by the floating diffusion and the switched capacitor integrator. Enables accurate signal reproduction.

Further, if the potential of the floating diffusion is reset by the reference voltage of the switched capacitor integrator, the potential of the floating diffusion can be set very accurately. Can be set to a constant level difference with extremely high accuracy. As a result, the signal charge can be controlled with high precision so as not to flow back to the BCCD side by simply setting the potential of the floating diffusion at the same time as resetting the switched capacitor integrator. SCCD for separating diffusion
Is unnecessary, and the structure can be simplified.

Further, it is possible to provide a highly accurate delay line using BCCD as a delay line main body.

Further, this CCD output circuit not only exerts excellent effects by being provided in a transfer path composed of a BCCD, but can also be applied to output circuits of other types of charge-coupled devices.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration diagram of an embodiment of the present invention and a potential profile for explaining the operation, FIG. 2 is a timing chart for explaining the operation of the embodiment; FIG. FIG. 4 is a timing chart for explaining the operation of the conventional example, and FIG. 4 is a view showing a potential profile for explaining the operation of the example. Reference numerals in the drawing: 10: semiconductor substrate 11: N ^- type impurity layer 16, 25 to 30: gate electrode 12; impurity layer 17; floating diffusion 18, 19: differential amplifier 20, 24: capacitive element 21, 23: Analog switch 22: Output terminal

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-73643 (JP, A) JP-A-2-165642 (JP, A) JP-A-2-220451 (JP, A)

Claims (1)

(57) [Claims] 1. A CCD output circuit for detecting a signal charge of a charge-coupled device and converting the signal charge into an electric signal capable of signal processing, wherein the charge-coupled device is constituted by a buried channel CCD, and a terminal of the buried channel CCD is provided. Forming a floating diffusion made of a predetermined impurity through a gate portion set to a predetermined fixed gate voltage, and providing a switched capacitor integrator for detecting an injected charge of the floating diffusion; A signal charge transferred from the charge-coupled device to the floating diffusion is detected by a switched-capacitor integrator. In this case, the gate voltage is determined by the floating operation determined by the reset operation of the switched-capacitor integrator. Do not exceed the diffusion voltage A CCD output circuit.