JP2641996B2 - Data retention method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data holding method, and more particularly, to holding data in a memory such as an EEPROM or a battery-backed-up RAM even when the power is turned off. Data held in memory
The present invention relates to a data holding method for an apparatus provided with a microprocessor for controlling a device using a data.

[0002]

2. Description of the Related Art Devices controlled by a microprocessor,
In particular, in the case of information equipment, EE
In some cases, the data is written and stored in a PROM or a RAM backed up by a battery, and the device is controlled based on the information. Some of the written information does not change, but some of the information changes at any time depending on the operation status of the device or by operation.

[0003] Information written to an EEPROM or a battery-backed RAM is an important factor in controlling equipment, and therefore, in some devices, not only writing and holding information but also (1) Information is written in a plurality of locations, and (2) information held in the plurality of locations is read out, for example, when the apparatus is powered on, and an error in the held information is detected by comparison. There is also a method of correcting an error in held information by a method such as a majority decision in addition to detection.

[0004]

Generally, memory access by a microprocessor is performed sequentially. However, except for a device having a power control function or a reset control function, the power is turned off and reset regardless of the operation of the microprocessor. For this reason, the power may be turned off or reset while the processor is writing information to the EEPROM or the battery-backed RAM. At this time, the following problem occurs. That is, (1) when there is a multi-digit counter for recording the operation status of the device, writing of all digits is not completed, resulting in an error in the counter value. For example, as shown in FIG. 9A, when the counter value is changed from 199 to 200, if the writing is performed in order from the upper digit, the power is turned off when the writing of “2” to the uppermost digit is completed. In this case, the counter value becomes 299. Also, if writing is performed in order from the lower digit, if the power is turned off when the writing of the lower two digits “00” is completed, the counter value returns to “100”.

(2) When the same information is written in a plurality of locations, writing to all the written locations is not completed, resulting in data errors at the time of checking the reading of the held information at power-on. For example, as shown in FIG. 9B, when the control information value “9” is changed to “0”, when there are three write locations (first to third storage locations M1 to M3), the first If the power is turned off immediately after writing “1” to the write location M1, the value of the first write location M1 is “0” and the second and third write locations are checked at the next power-on information check. Since the values of M2 and M3 do not match at "9", data errors occur.

Further, when data is restored by majority decision, the data is restored to the value "9" before the change. Also,
In the case of a multi-digit counter as in (1), an error also occurs in the counter value.

Accordingly, it is an object of the present invention to provide a device which is reset or turned off while a microprocessor for controlling a device is performing a sequence of writing information to an EEPROM or a battery-backed RAM. It is still another object of the present invention to provide a data holding method capable of preventing an error from occurring in data written in an EEPROM or a battery-backed RAM.

Another object of the present invention is to provide an EEPROM or battery that is capable of resetting or powering down the device.
No additional hardware is required to prevent errors in the data written to the backed-up RAM,
A data holding method that can be handled only by software is provided.

[0009]

FIG. 1 is a diagram illustrating the principle of the present invention. Reference numeral 11 denotes a memory for storing retained data such as an EEPROM or a battery-backed RAM;
Is a microprocessor (MPU).

In the memory 11, reference numeral 11a denotes a holding data storage area for storing holding data, and 11b denotes an information recording area for writing and restoring data in the storage area. In the microprocessor 12, when power is turned on or reset is released, the microprocessor 12 determines whether or not the contents of the information recording area 11b have been cleared, and clears the information.
If not, use the check data to store
Information recording area contents for checking validity of data in
The discriminating unit 12b determines that the data in the information recording area has been cleared.
If the data is valid and the data is valid, it is a holding data restoring unit that writes the holding data in the information recording area to the storage area 11a and restores it.

[0011]

In the memory for holding data even when the power is turned off, an information recording area 11b for writing and restoring data in the storage area separately from the held data storage area 11a. (1) The storage area is stored in the information recording area 11b.
The data holding address and the holding data are written.
Then, check data for checking the validity of the data
(2) After a while, the stored data is stored in the storage area 11a.
And (3) storing the data in the storage area 11a.
(4) Check the information recording area 11b.
Clear the data (5) Then, except for the check data
Clear the data of Then, when turning on the power or resetting
At the time of reset, the information recording area of the microprocessor 12
The content determination unit 12a refers to the information recording area 11b and
If the data in the recording area has not been cleared,
Validity of data in information recording area using data
Is checked, and if valid, the held data restoring unit 12b
The stored data stored in the information recording area is stored in the storage area 1
1a, the information is written after the write processing of the held data is completed.
The data in the information recording area 11b is cleared.

[0012]

EXAMPLES overall configuration diagram 2 shows an embodiment diagram according to the present invention, cut Kamire - it is applied to a printer control unit for controlling The printer mechanism unit. Since the control of the printer itself is not related to the present invention, the details of the control method and control information are omitted.

Reference numeral 11 denotes a battery-backed RAM of an 8-bit CMOS static configuration, which stores stored data for storing device control information and operation status (hereinafter referred to as "control information") as described later. It has an area and an information recording area for writing and restoring data in the storage area. Reference numeral 12 denotes an 8-bit microprocessor that executes printer control and performs a storage process and a restoration process of control information (holding data) described later according to the present invention. 13 stores a control program 8
The bit-structured EPROM 14 is an I / O-LSI including an input / output port between the mechanism control element / external interface and a timer.

Reference numerals 15 and 16 denote RAM 11 and RO, respectively.
M13, I / O-LSI14 chip select signal * C
A RAM-CS control circuit and a CS control circuit for controlling S. 17 is a + 3.0V lithium battery, 18 is a power supply Vcc
Is a power supply control circuit that monitors the voltage of Vcc.
V, but when the voltage falls below 2.5 V, the microprocessor (MPU) 12 and the RAM-CS control circuit 15 send * RES
ET signal is issued, and the RAM-CS control circuit 15 and the RAM
The power supply VccRAM supplied to the power supply 11 is switched from Vcc to the battery 17.

The RAM-CS control circuit 15 includes a RAM 11
Power supply control circuit 1 by controlling the chip select signal * CS of
When 8 is issuing the * RESET signal, the voltage of * CS is set to the same voltage as the power supply VccRAM of the RAM 11. At this time, the RAM 11 enters the low power consumption mode, and the power supply Vcc
Holds the written data even while is disconnected.

Address arrangement and RAM memory map FIG. 3 is an explanatory view of the address arrangement of peripheral circuits and the memory allocation of the RAM as viewed from the microprocessor (MPU) 12. The RAM 11 has a holding data storage area 11a and information. A recording area 11b and an MPU work area 11c are provided.

The MPU work area 11c is a data register area and a stack area necessary for the microprocessor 12 to control the printer mechanism, and is cleared immediately after the reset of the microprocessor is released (リ セ ッ ト).
00 is written). The held data storage area 11a stores control information (held data), and includes first to third control information storage areas 11a-1, 11a-2, and 11a-3. , 11a-2 and 11a-3 are written with exactly the same control information. Information recording area 11b
Is for writing and restoring data in the held data storage area 11a, and is composed of 8 bytes. In the first to third control information storage areas 11a-1, 11a-2, 11a-3 and the information recording area 11b, an initial value previously defined in the ROM 13 is written by an initialization command from a higher order (area initialization). ).

First to third control information storage areas The first to third control information storage areas 11a-1, 11a-2, and 11a-3 are, as shown in FIG. It has 16 3-byte counters A to P for storing the life management of the printer and 16 1-byte control information A to P for storing parameters such as image recording of the printer. Writing of control information is consecutive 3 bytes or 1
Performed in byte units.

The information in the recording area information recording area 11b, the following de - data (1) the offset value from the first to the top of the third control information storage area 11a-1,11a-2,11a-3 (offset address ), The write address WAD, (2) the number of bytes in the write unit (the number of write bytes) BY
T, (3) Write data (hold data) DT1 to DT5 (4) Checksum value of write processing information (check data
C) CKD is written. In this embodiment, since the 3-byte unit write and the 1-byte unit write are mixed, the write processing information includes the "write byte number" BYT indicating the number of bytes of the write unit. However, when the write unit is always fixed to the 3-byte unit, or when the 1-byte unit write and the 3-byte unit write are each provided with the information recording area of the write processing information, the “write byte number” BYT is unnecessary. .

Overall operation (a) Write control of retained data First to third control information storage areas 11a-1, 11a-2,
3-byte data in the counter part B of 11a-3 is $ 012345
Will be described.

(1) Initially, $ 00 is written as an initial value to all data in the information recording area 11b (cleared state).

(2) In such a state, write data (hold data) is written to the data write area of the information recording area 11b.
Write “ $ 012345 ”. (3) Next, the write address is stored in the information recording area 11b.
(Offset address “$ 03” from the head of the control information storage areas 11a-1, 11a-2, and 11a-3) and the number of write bytes ($
03) is written.

(4) Also, check data is calculated and written in the information recording area 11b. The check data is obtained by subtracting a 7-byte hexadecimal value in the information recording area 11b from "FF" for each digit. In the case of FIG. 5, the check data is $ 90, but this check data is obtained by $ 90 = $ FF- $ 03- $ 03- $ 01- $ 23- $ 45- $ 00- $ 00.

(5) When the writing of the data to the information recording area 11b is completed, the 3-byte data is written to the counter B of the first control information storage area 11a-1. That is,
Write data # 01 to memory address $ 0743,
Write data # 23 to memory address $ 0744,
Write data # 45 to memory address $ 0745.

(6) Also, 3-byte data is written to the counter section B of the second control information storage area 11a-2. That is, data # 01 is written to memory address $ 0783, data # 23 is written to memory address $ 0784, and data $ 45 is written to memory address $ 0785.

(7) Further, 3-byte data is written in the counter section B of the third control information storage area 11a-3. That is,
Data # 01 is written to memory address $ 07C3,
Write data # 23 to memory address $ 07C4,
Data # 45 is written to memory address # 07C5.

(8) First to third control information storage areas 11a-1 to 11a-1
When the writing to 1a-3 is completed, the check data CKD in the information recording area 11b is cleared (write $ 00). (9) Next, the write address W of the information recording area 11b
AD and the number of bytes BYT to be written are cleared ($ 00 is written).

(10) Finally, the write data DT1 to DT5 in the information recording area 11b are cleared ($ 00 is written). As described above, the content of the information recording area 11b returns to the initial state, and the writing control of the held data is completed.

When the step (4) is completed, each data is stored in the information recording area 11b as shown in FIG. In each of the steps (1) to (10), the information recording area 1
The data stored in 1b is as shown in FIG. Therefore, when the power is turned off during the write sequence, the contents corresponding to steps (1) to (10) at the time when the power is turned off remain in the information recording area 11b.

The above description is for the case where 3-byte data is written into the storage area. However, when writing 1-byte data, the data is set in the information recording area 11b, and each of the storage areas 11a-1 to 11a is written. -3 is written, and the data in the information recording area is cleared. FIG. 7 shows a case where data is set in the information recording area 11b. However, the first
This is a case where 1-byte data # 88 is written in the control information section B of the third control information storage areas 11a-1, 11a-2, 11a-3.

(B) Restoration Control of Retained Data FIG. 8 is a flowchart of restoring control of retained data. After power-on or reset release, the microprocessor 12 and M
After initializing the PU work area (Step 10)
1) It is checked whether the storage contents of the information recording area 11b have been cleared (step 102). If the storage contents have been cleared, the state is (1) or (10) in FIG. There is no need to perform this, and the restoration control ends.

However, if it is not cleared, FIG.
Since the state is (2) to (9), restoration control is performed. First,
Data check (checksum comparison) of the information recording area 11b is performed (step 103). If the checksum is correct, the steps (4) to (7) in FIG.
While writing the held data to the third control information storage areas 11a-1, 11a-2, 11a-3, it can be considered that the power supply has been turned off. In this case, the correct recording data is stored in the information recording area 11b.
Since the data is stored, the first to third
The data held in the control information storage areas 11a-1, 11a-2, and 11a-3 are restored. That is,

The stored data stored in the information recording area 11b is written in the first control information storage area 11a-1 (step 104), and then the stored data is similarly stored in the second control information storage area 11a-2. The data is written (step 105), and the held data is also written in the third control information storage area 11a-3 (step 106).

Next, the check data is cleared ($ 0
0) is written (step 107), and then the write address WAD and the number of write bytes BYT of the information recording area 11b are cleared (step 108).

Finally, the write data DT1 to DT5 in the information recording area 11b are cleared (step 1).
09). On the other hand, if the checksum is not correct in step 103, it means that the power has been turned off during steps (2) to (3) and (8) to (9) in FIG. Since there is no guarantee that the data is correct, the contents of the information recording area are cleared and the restoration control ends.

The present invention has been described with reference to the embodiments.
The present invention can be variously modified in accordance with the gist of the present invention described in the claims, and the present invention does not exclude these.

[0037]

As described above, according to the present invention, the data writing / restoring in the storage area for storing the data separately from the storage area for the stored data in the memory for holding the data even when the power is cut off is performed. After providing an information recording area for storing the stored data in the information recording area, writing the retained data in the storage area, writing the retained data in the storage area, and then recording the information. Clear the data held in the area, refer to the information recording area at power-on or reset release, and if the data held in the information recording area is not cleared, store the data held in the information recording area. Since the data stored in the information recording area is cleared after the data is written into the information recording area, the data stored in the information recording area is cleared during the information writing sequence to the EEPROM or the battery-backed RAM. , Tsu even if doors or the power supply is cut off, EE
The data written to the PROM or the battery-backed RAM can be restored so as not to cause an error, and can be dealt with only by software without requiring additional hardware. According to the present invention, the information
In the recording area, an address for writing the retained data in the storage area and
After writing the retained data, check the validity of the data
Write the check data, and then store it.
Writes data to the storage area and stores it in the storage area
After writing the data, check the data in the information recording area.
And then delete data other than the check data.
Information storage area when power is turned on or reset is released
And the data in the information recording area is not cleared
In this case, check data is
Check the validity of the data, and if it is, record the information.
Write the retained data stored in the area to the storage area
After the write processing of the retained data is completed,
Since the data is cleared, the EEPROM
Or write information to battery-backed RAM
Reset or the power is turned off during the
Also, make sure that correct data without errors is
Restoring to battery-backed RAM
it can. Also, the data in the information recording area remains without being cleared.
If there is an error in the data,
EPROM or battery-backed RAM
Can not be written.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of address arrangement and RAM memory allocation.

FIG. 4 is a configuration diagram of a control information storage area.

FIG. 5 is an explanatory diagram of storage data in an information recording area according to the present invention.

FIG. 6 is a transition diagram of storage data in an information recording area during write control.

FIG. 7 is an explanatory diagram of storage data in an information recording area in the case of 1-byte data.

FIG. 8 is a flowchart of control for restoring held data.

FIG. 9 is an explanatory diagram of a conventional problem.

[Explanation of symbols]

 11. Memory for storing held data 11a: held data storage area 11b: information recording area 12: microprocessor (MPU) 12a: information recording area content discriminating unit 12b: held data Restoration section

Claims (1)

(57) [Claims] 1. A de during power down - holds the data in the memory, de held in the memory when the power is turned - de of the device for controlling the device by using the data - in data holding method, the memory Within the storage area of the stored data
Information writing for writing and repairing data in the area
A recording area is provided, and an address for writing data held in the storage area is provided in the information recording area.
After writing the data and the retained data, check the validity of the data.
Write the check data for writing to the storage area , then write the holding data to the storage area, write the holding data to the storage area , and then write the information recording area.
Clear the check data, then check data
Clear external data and refer to information recording area when power is turned on or reset is released
If the data in the information recording area has not been cleared,
Is to check the data in the information recording area using the check data.
Check the validity of the data , and if valid, hold the data stored in the information recording area.
Is written into the storage area, and after the write processing of the held data is completed, the data in the information recording area is written.
A data holding method characterized by clearing data.