JP2629626B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a multilevel output level type mask R.
The present invention relates to an OM and a method for manufacturing the OM.

[0002]

2. Description of the Related Art A conventional semiconductor memory device for storing multi-value information includes a plurality of MIS transistors (in this specification,
A source region of a general insulated gate field effect transistor is referred to as a MIS transistor) is commonly connected to zero potential (ground potential), a drain region and an output terminal are commonly connected, and a voltage is applied through a resistor. The transconductance (change in drain current with respect to change in gate voltage: (ΔI _SD / ΔV _G )) of the corresponding MIS transistor is changed according to the multi-valued information to be stored.

[0003] shows a circuit diagram of a multi-value information type mask ROM with a conventional N-channel MIS transistor _{T 1, T 2 ...... T i} ...... T n in Figure 5. N-type source regions S ₁ and S ₂
...... S _i ...... S _n while the common connection to zero potential at the common impurity regions of the source wiring layer F or N-type (GND) and a drain region D ₁ of the N-type, D ₂ ...... D _i ...... D _n and an output terminal Z are commonly connected by a drain wiring layer E, and a positive potential V _DD is applied via a resistor R.

[0004] Here, if for example, the multi-value is m levels, by means of creating a mutual conductance _{g 1, g 2 ...... g j} ...... g m m different, predetermined M in accordance with the information to be stored
Each of the IS transistors has a predetermined transconductance.

In the figure, MIS transistors T ₁ , T ₂ ...
The transconductance of T _i ... T _n is represented by g ₁ and g, respectively.
_m ... g _j ... g ₂ are shown.

FIG. 6 shows a means for forming the mutual conductance of the MIS transistor to a predetermined value.

FIG. 6A shows a method disclosed in Japanese Patent Publication No. 61-46065, in which a channel region 28 is defined by a field oxide film 2 provided on a P-type silicon substrate 1. An N-channel MIS transistor provided with a gate oxide film 3 and a polysilicon gate electrode 4 is formed thereon and stocked in this state, and a photoresist pattern 21 is formed according to an order from a customer, and this is used as a mask. By implanting boron 23 into the channel region 28 through the polysilicon gate electrode 4 and the gate oxide film 3 to form the P ⁺ -type region 24 on both sides, the effective channel width W is changed by each MIS transistor. This is to change the mutual conductance of each MIS transistor.

FIG. 6B shows a method disclosed in Japanese Patent Application Laid-Open No. 61-263263, in which, similarly to FIG. 6A, a photoresist pattern 21 is formed in accordance with an order from a customer. Using this as a mask, boron 23 is implanted into the channel region 28 through the polysilicon gate electrode 4 and the gate oxide film 3 to form the P ⁺ type region 24, thereby changing the effective channel width by each MIS transistor. Although the transconductance of each MIS transistor is changed, in FIG. 6B, a P ⁺ -type region 24 is formed in the center of the channel region 28, and the effective channel width (W ₁ + W ₂ ) on both sides is formed. Is changing.

As a result, the MIS transistors T ₁ and T ₂
… T _i … T _n gate electrodes G ₁ , G ₂ … G _i ……
When the gate electrode of _Gn whose address is selected is set to a high level H (plus potential), a drain current corresponding to the value of the mutual conductance of the MIS transistor flows, and one of the multi-level levels is applied to the output terminal Z. obtain. In this case, since the gate electrode of the MIS transistor whose address is not selected is set to the low level L (zero potential), no drain current flows even if the MIS transistor has any mutual conductance. This is equivalent to the case where only the MIS transistor whose address has just been selected exists, and the MIS transistor whose address has not been selected does not exist.

In this way, a semiconductor memory device having a multi-level output level has been obtained by forming MIS transistors having various types of mutual conductance.

[0011]

The conventional semiconductor memory device which stores multi-values by changing the mutual conductance as described above receives an order from a customer and then, based on the multi-value information requested by the customer. Since a MIS transistor having a different mutual conductance has to be manufactured, there is a problem that a longer turnaround time (TAT) is required until the product is completed as compared with a normal mask ROM or the like.

In the prior art shown in FIG. 6, the mutual conductance is changed by selectively ion-implanting impurities of the same conductivity type as the substrate through the polycrystalline silicon gate electrode and the gate insulating film to change the effective channel width. Therefore, after an order from the user, an extra step for selective ion implantation is required in addition to the formation of the contact hole and the wiring layer, and the TAT becomes longer.

Further, it is difficult to accurately change the transconductance of the MIS transistor to various predetermined values. For example, in FIG. 6, it is difficult to precisely control the ion implantation conditions and the activation heat treatment conditions to accurately change the effective channel width to various predetermined values. Therefore, there is a problem that each level of the multi-value becomes inaccurate and the number of the multi-value cannot be increased.

Accordingly, an object of the present invention is to provide a semiconductor memory device which can shorten the time from the request of a user (customer) to the completion of a product, and in which each level of many multi-values is accurate, and a method of manufacturing the same. That is.

[0015]

A feature of the present invention is that it has a plurality of MIS transistors arranged in a first direction and a plurality of source wiring layers to which different potentials are supplied. Semiconductor memory in which source regions of MIS transistors are connected to different source wiring layers, respectively
Device, wherein the plurality of source wiring layers are
Extending in the first direction with an interval, the first direction
The position of the contact hole in the second direction perpendicular to the
To connect the respective source regions
The semiconductor memory device selects the source wiring layer .

Another feature of the present invention is that a gate insulating film and a gate electrode are formed on a source region, a drain region, and a channel region, and a plurality of MIS transistors are formed with at least the source region covered with an insulating film. Thereafter, contact holes reaching the respective source regions are formed at a plurality of predetermined locations of the insulating film, and then different potentials are respectively supplied to the source regions of the plurality of MIS transistors through the contact holes. A method for manufacturing a semiconductor memory device for connecting source wiring layers,
And the plurality of MIS transistors are arranged in a first direction.
Formed before each supplying a different potential
The source wiring layers are spaced apart from each other by a predetermined distance.
Direction, and extends in a second direction perpendicular to the first direction.
By selecting the position of the contact hole to be
The source wiring layer to which each of the source regions is connected is
There is a method of manufacturing a semiconductor memory device to be selected .

Here, the respective portions of the plurality of MIS transistors are formed identically, that is, are formed of the same shape, the same material, and the same impurity concentration, so that the same mutual conductance (under the same voltage condition) is obtained. arbitrary preferred to have a case where the comparison).

[0018]

As described above, according to the present invention, the plurality of source wiring layers to which different potentials are supplied and the source regions of the plurality of MIS transistors are respectively connected to different source wiring layers. A multi-valued level can be obtained only by forming a contact hole and a wiring layer, which is the same as that of a binary mask ROM of a normal contact selection. Can be.

Since the multilevel value depends on the supply potential of the wiring layer and does not depend on the mutual conductance of the MIS transistor, a desired accurate multilevel output level can be obtained.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, T ₁ , T ₂ ... T _i
... _Tn are formed identically, that is, each part is configured to have the same shape, the same material, and the same impurity concentration, so that when compared under the same voltage application condition, the mutual conductance The MIS transistor is formed so that the characteristics of the MIS transistor are the same.
Further, each of _{G 1, G 2 ...... G i} ...... G n is a gate electrode of the MIS transistor _{T 1, T 2 ...... T i} ...... T n, D 1, D 2 ...... D i ...... D _n is the drain region of the MIS transistor _{T 1, T 2 ...... T i} ......... T n _{respectively, S 1, S 2 ...... S} i ...... S n respectively MI
That is the source region of the S transistor _{T 1, T 2 ...... T i} ......... T n.

Each drain region D ₁ ,
D ₂ ... D _i ... D _n are commonly connected and connected to an output terminal Z, and one end of a resistor R is connected thereto.
The other end of the resistor R is connected to a _VDD line that supplies a positive potential.

[0023] _{F 1, F 2 ...... F j} ...... F m are each the source wiring layers, the potentials V ₁ corresponding to the level of the _{multi-level, V 2 ...... V j ...... V} m is applied .

Then, based on the multi-value information requested by the customer (user), the respective source areas S ₁ , S ₂ ... S _i
......... S _n is the potential required is connected to the source wiring layer obtained.

[0025] In Figure 1, the potential V ₁ is applied the source region S ₁ of the MIS transistor T ₁ is connected to the source wiring layers F _1, connected to the source region S ₂ of the MIS transistor T ₂ is the source wiring layer F _m And the potential _Vm is applied,
Transistor T _i source region S _i is the source wiring layer F _j of
And the potential _Vj is applied to the MIS transistor T
_{An example is shown in which the n} source region _Sn is connected to the source wiring layer F ₂ and the potential V ₂ is applied.

Here, the MIS transistors T ₁ , T ₂ .
… T _i … T _n gate electrodes G ₁ , G ₂ … G _i … G
address selected gate electrodes of _n, for example, the gate electrode G _i to the high level H (plus potential) that M
IS transistor T _i is the drain current flows in the form a source region S ₁ and the drain region D ₁ and the conductive state of the other M
The gate electrode of the IS transistor is at a low level L (zero potential) because no address is selected, and no drain current flows between the source region and the drain region in an off state. Therefore, this is equivalent to the case where only the MIS transistor T _i whose address is selected exists and the other MIS transistor whose address is not selected does not exist.

[0027] Therefore, in this case, the potential of the source region S _i of the MIS transistor T _i from selectively connected source wiring layer F _j is obtained at the output terminal Z. The potential at the output terminal Z is substantially equivalent to the potential V _j from the source wiring layer F _j because hardly depends on the transconductance of the MIS transistor.

The substrate potential or the back gate potential is used at zero potential (ground potential).

FIGS. 2 to 4 are views showing a method of manufacturing the semiconductor memory device of FIG. 1 in the order of steps. FIG.
4 to 4, the illustration of the resistor R and the output terminal Z is omitted.

FIG. 2 shows a state in which a plurality of MIS transistors are formed and stocked until an order is received from a user. FIG. 2 (A) is a plan view, FIG. 2 (B) and FIG. ) Are BB part and C- part in FIG.
It is sectional drawing of the C section.

A field oxide film 2 is selectively formed on the main surface of a P-type silicon substrate 1, and an N-type source region (S ₁ , S ₂₎ is formed in an active region defined by the field oxide film _{2.
...... S i ......... S n) 5} , the channel region 8 and the N-type drain region _{(D 1, D 2 ...... D} i ...... D n) a plurality of MIS transistors having 6 T _1, T ₂ ...... T _i ............ T
_n are arranged in the Y direction.

A polysilicon gate electrode (G ₁ , G ₂ ... G _i ... G) is formed on the channel region 8 via the gate oxide film 3.
_n ) 4 is formed by patterning the polysilicon film. Also, a gate electrode lead portion 4A is formed by patterning, and the gate electrode is drawn in the X direction perpendicular to the Y direction (to the right in the plan view (A)) so that the address signal reaches the gate electrode on the channel region. Has become. Also, source and drain regions 5, 6
Is formed in a self-aligned manner by introducing an N-type impurity using the gate electrode 4 and the field oxide film 2 as a mask member.

And source and drain regions 5, 6,
The entirety including the gate electrode 4 and the lead portion 4A is covered with an interlayer insulating film 7 such as a silicon oxide film.

As described above, these MIS transistors have the same shape, material, and impurity concentration in each portion, and therefore have the same electrical characteristics such as mutual conductance under the same potential.

Next, in FIG. 3, after receiving an order from a user, a source contact hole 11 and a drain contact hole 12 are formed in the interlayer insulating film 7. In addition, FIG.
3 is a plan view, and FIG. 3B is a cross-sectional view taken along a line BB in FIG. 3A.

The drain region (D) of each MIS transistor
_1, the drain contact hole 12 reaching the _{D 2 ...... D i ...... D n} ) 6 is formed on the X _D of the same X-coordinate.

However, the source contact holes 11 reaching the source regions (S ₁ , S ₂ ... S _i ... S _n ) 5 of each MIS transistor have different X coordinates depending on the information to be stored requested by the user. Let it.

In this embodiment, the MIS transistor T ₁
Source contactor hole 11 reaching source region S ₁ of X
The source contactor hole 11 formed at the coordinate X ₁ and reaching the source region S ₂ of the MIS transistor T ₂ is located at the X coordinate X
formed in _m, the source region S _i of the MIS transistor T _i
Source contactor hole 11 reaching the form in X _j X coordinate, the source contactor hole 11 reaching the source region S _n of the MIS transistor T _n is formed in X ₂ of X coordinate.

Next, in FIG. 4, each wiring layer is formed.
FIG. 3A is a plan view, and FIG. 3B is a plan view of FIG.
It is sectional drawing of the -B part.

By depositing an aluminum film and patterning it, one drain wiring layer E extending over the drain region 6 and the gate electrode lead portion 4A via the insulating film 7 and the source region 5 are insulated. A plurality of source wiring layers F ₁ , F _2, ..., F _j, ..., F _m extending through the film 7 are formed.

The drain wiring layer E is extended Mashimashi by the drain contact hole 1 and the width center every Y direction X _D X coordinate
2, the drain region 6 of each MIS transistor is commonly connected.

Source wiring layers F ₁ , F ₂ ... F _j.
m is the width center of X ₁ , X ₂ ... X _j
...... placed X _m, there extends in the Y direction to each other with a predetermined interval. Then the circuit of Figure 1 connected to the respective source regions 5 through the _{X 1, X 2 ...... X j} ...... source contact hole 11 in the X _m are formed respective X coordinates.

Thereafter, a semiconductor memory device is completed by forming a passivation film and the like. However, since this is the same as other semiconductor devices, description thereof is omitted.

As described above, since the X-coordinates of the source contact holes are different depending on the information requested by the user, the patterns of the source wiring layer and the drain wiring layer can always be constant. In other words, the mask for forming each source wiring layer by patterning aluminum in the process of FIG. 4 does not need to be changed according to information requested by the user.

[0045]

As described above, according to the present invention, a source region of a plurality of MIS transistors and a plurality of source wiring layers to which a potential corresponding to a multi-value is applied are selected according to information to be stored. Connection, short turnaround time and accurate multilevel output level can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIGS. 2A and 2B are views showing a state in an intermediate step of the method of manufacturing the semiconductor memory device according to the embodiment of the present invention, wherein FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along the line BB of FIG. (C) is a cross-sectional view of the CC section of (A).

FIG. 3 is a diagram showing a state in a step after FIG. 2;
(A) is a plan view, and (B) is a cross-sectional view taken along the line BB of (A).

FIG. 4 is a view showing a state in a step after FIG. 3;
(A) is a plan view, and (B) is a cross-sectional view taken along the line BB of (A).

FIG. 5 is a circuit diagram showing a conventional semiconductor memory device.

6 is a diagram illustrating a method of changing the transconductance of the MIS transistor in FIG. 5, wherein (A) and (B) are cross-sectional views of respective prior arts.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4 Polysilicon gate electrode 4A Gate electrode lead-out part 5 N-type source region 6 Drain region 7 Interlayer insulating film 8, 28 Channel region 11 Source contact hole 12 Drain contact Hole 21 Photoresist pattern 23 Boron 24 P ⁺ -type region T ₁ , T ₂ … T _i … T _n MIS transistor G ₁ , G ₂ … G _i … _Gn gate electrode D ₁ , D ₂ … D _i ... D _n drain region S ₁ , S ₂ ... S _i ... _Sn source region E drain wiring layer F ₁ , F ₂ ... F _j ... F _m , F source wiring layer Z output terminal R resistance V potential X ₁ corresponding to the level of the _DD positive potential line _{V 1, V 2 ...... V j} ...... V m _{multilevel, X 2 ...... X j ...... X} m, X D X coordinate g _1, g _m ...... g _j ...... g ₂ transconductance , W _1, W ₂ effective channel width

Claims (4)

(57) [Claims] 1. A semiconductor device comprising: a plurality of MIS transistors arranged in a first direction; and a plurality of source wiring layers to which different potentials are supplied. The source regions of the plurality of MIS transistors are different from each other. A semiconductor memory device connected to a wiring layer , wherein the plurality of source
The line layers extend in the first direction at a predetermined distance from each other
And contours in a second direction perpendicular to the first direction.
By selecting the position of the contact hole,
A semiconductor memory device, wherein the source wiring layer connected to the source region is selected . 2. The semiconductor memory device according to claim 1, wherein respective portions of said plurality of MIS transistors are formed identically to each other. 3. A gate insulating film and a gate electrode on a source region, a drain region, and a channel region are formed, and a plurality of MIS transistors are formed with at least the source region covered with an insulating film. A contact hole reaching each of the source regions is formed at a plurality of predetermined portions of the film, and then a source wiring layer that supplies a different potential to each of the source regions of the plurality of MIS transistors is connected through the contact hole. A method of manufacturing a semiconductor memory device, comprising:
The S transistors are formed to be arranged in a first direction, and
The plurality of source wiring layers that supply different potentials are mutually connected.
Extending in the first direction at a predetermined interval,
The contact in a second direction perpendicular to the first direction
By choosing the location of the holes, each source
A method for manufacturing a semiconductor memory device, comprising selecting the source wiring layer connected to a region . 4. A method according to claim 1, wherein said plurality of MIS transistors include said source region, drain region, gate insulating film, gate electrode,
4. The method according to claim 3, wherein the portions including the channel region and the insulating film have the same shape, the same material, and the same impurity concentration.