JP2611643B2 - Synchronous data signal transceiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous data signal transmitting / receiving apparatus, and more particularly, to an X.100 system conforming to CCITT-X series recommendations. The present invention relates to an apparatus for transmitting and receiving a synchronous data signal in a 50-frame format.

[0002]

2. Description of the Related Art CCITT-X. At 50, FIG.
An 8-bit envelope is defined as shown in FIG. 6, and a plurality of 8-bit envelopes are used as shown in FIG. 6 to constitute a 20 multi-frame. Further, each configuration of each bearer channel # 1 to # 5 in the 20 multiframes is defined as shown in FIG.

The first bit of the 8-bit envelope shown in FIG. The framing bit f is for 50 frames, and the eighth bit is a status bit S. Then, a total of 6 bits of the remaining second to seventh bits are used as information bits.

[0004] The actual information speed is called a user rate, and the speed after envelope formation is called a bearer rate. In the multiplexing of the 8-bit envelope, the signal is first multiplexed to 12.8 Kbps, and further multiplexed to 5 (multiplicity 5) to 64 Kbps.

[0005] After the multiplexing of X. The 20 multiframe configuration at 50 is shown in FIG.
1 to # 5 are interleaved and multiplexed.
And this X. Each bit configuration of the bearer channels # 1 to # 5 in 20 multiframes at 50 is as shown in FIG.

[0006] Such X. When 50 frames are further multiplexed into n channels (n is an integer of 2 or more) in units of one channel to form a multiplex frame structure for n channel transmission, a transmission / reception block configuration as shown in FIG. 7 can be considered.

That is, the X.V. 50 frames are divided into n low-speed sections 1.1 to 1.. n, which are multiplexed by the multiplexing unit 1 as channels (CH) 1 to n to form a multiplexed frame structure for n-channel transmission, and transmitted to the high-speed transmission line 3.

A signal having a multiplex frame structure for n-channel transmission from a high-speed transmission line is separated by an X. Low-speed sections 1.1 to 1. n, respectively.

[0009]

As described above, in the configuration shown in FIG. In order to multiplex 50 frames into n (n channels) to form a multiplexed frame, a frame configuration as shown in FIG. 8 is obtained. F is required.

Accordingly, the remaining time slots of channel 1 are 7 bits (corresponding to a transmission capacity of 48 Kbps), and X.times. Bits which require time slots of 8 bits (corresponding to a transmission capacity of 64 Kbps). A 50 frame configuration cannot be achieved. As a result, the configuration shown in FIG. 7 has a disadvantage that it is impossible to multiplex a bearer channel and transmit a synchronous data signal.

The present invention has been made in order to solve the above-mentioned drawbacks of the prior art. 48 Kb of synchronous data in 50 frame format
An object of the present invention is to provide a synchronous data signal transmitting / receiving apparatus capable of transmitting and receiving synchronous data in a multiplex frame format by enabling transmission on a ps channel.

[0012]

SUMMARY OF THE INVENTION A synchronous data signal transmitting apparatus according to the present invention comprises a plurality of predetermined bit envelopes from a low-speed stage, and comprises a plurality of bit envelopes conforming to the CCITT-X recommendation. 50
Separation means for selectively separating the status bits in the envelope with a frame as input, storage means for temporarily storing the separated status bits, and a residual from which the status bits have been deleted via the separation means. Selection means for selectively deriving bits and the status bits stored in the storage means, and the predetermined bits while adding frame information for frame synchronization to each first bit of all envelopes of the selected output of the selection means. Transmission consisting of multiple envelopes
Transmitting means for transmitting in a frame configuration for use, and means for controlling the selecting means such that all of the status bits stored in the storing means are inserted into a specific envelope portion of the plurality of envelopes. It is characterized by.

A synchronous data signal receiving apparatus according to the present invention comprises:
CCITT- consisting of a plurality of envelopes of a predetermined bit
X. 50 frames are multiplexed as n first to n-th channels, and only in the first channel, frame information for frame synchronization is inserted into the first bit of each constituent envelope, and status bits are inserted into the specific envelope part. A receiving device for receiving a synchronization data signal, wherein the first to first signals are based on the frame synchronization information.
Each of X.n. Separation means for separating 50 frames, storage means for receiving and storing information of an envelope other than the specific envelope of the separated first channel, and status bit storage for receiving and storing the status bits of the specific envelope Means and the contents stored in these storage means. Means for reproducing 50 frames.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic block diagram of the present invention, and the same parts as those in FIG. 7 are denoted by the same reference numerals. Multiplicity 5
(Low-speed unit having bearer channels # 1 to # 5)
1-1. n is X.n of the first to n-th channels. Generating 50 frames is the same as the example of FIG. 7, but among the five bearer channels # 1 to # 5 which are inputs to the low-speed unit 1.1 corresponding to the first channel, for example, bearer channel # 5 For, an 8-bit time slot (8-bit envelope) containing no information is input.

The X.0 signal output from the low-speed section 1.1 corresponding to the first channel. For data in 50 frame format,
In transmitting section 4, 8 of each of four bearer channels # 1 to # 4
Bit information (f bits, 6 information bits and S
Only the S bits among the bits are separated and extracted and superimposed on a time slot having only 7 bits (see FIG. 3A). Further, the separated and extracted bearer channels # 1 to # 4
Are inserted into the time slot of the empty bearer channel # 5 (see FIG. 3B).

Thereafter, a framing bit F for frame synchronization is inserted into the first bit of each bearer channel, and the X. Data of 50 frame format is transmitted.

For the other 2 to n channels, the low speed sections 1.2 to 1.. 5 bearer channels as in X.n.
The data is directly transmitted to the multiplexing unit 1 as a 50-frame format. In this way, it is possible to transmit the n-channel multiplexed frame format synchronous data signal shown in FIG.

The synchronizing data signal in the n-channel multiplex frame format from the high-speed transmission path 3 is transmitted to the X.R. Each channel data of 50 frame format is separated. 2nd to nth
Channel data is directly supported by the low-speed sections 1.2-1. n and separated into five bearer channels, respectively.

The data of the first channel is input to the receiving unit 5 and subjected to a process reverse to that of the transmitting unit 4, so that the bearer channels # 1 to # 5 are separated.

X. of the first channel The details of the transmission unit 4 and the reception unit 5 that process a 50-frame transmission / reception signal will be described with reference to FIG.

For the first channel, as described above,
X. 7 bits. Since it is necessary to transmit 50 frames, information excluding the S bit in the four time slots of the bearer channels # 1 to # 4 is used. In the time slot of the bearer channel # 5, the S bit of the bearer channels # 1 to # 4 is used. Are transmitted, respectively. Generate a 50 frame format.

Therefore, the transmitting unit 4 selectively extracts and separates all the S bits of each of the bearer channels # 1 to # 4, and temporarily stores the separated S bits. An S-bit transmission register 12 to be stored, a selector 13 for selectively deriving the output of the S-bit separation unit 11 and the output of the S-bit transmission register 12, and using the selector output as an n-channel multiplex frame format for phrasing. A frame transmitting unit 14 for adding and transmitting an F bit,
Timing generator 15 for controlling these units 11 to 14
Are provided.

The 8-bit envelope signal from the low-speed section 1.1 is sent to the selector 13 by the S-bit separation section 11, that is, 7 bits including f bits and information bits. The separated S bit is sent to the S bit transmission register 12, and
S bits for several frames are temporarily stored.

The selector 13 selectively derives either the 7-bit signal from the S-bit separation unit 11 or the 7-bit signal from the S-bit transmission register according to the timing from the timing generation unit 15 and Transmission unit 1
4

The frame transmitting section 14 adds a 7-bit signal from the selector 13 after the framing bit F for n-channel multiplex transmission, and outputs it to the multiplexing section 1 as an 8-bit signal.

The structure of bearer channels # 1 to # 4 in 20 multiframes in the multiplex frame for n-channel multiplex transmission is as shown in FIG.
The configuration of No. 5 is as shown in FIG.

In the timing generator 15, 64 Kbps
3A and a clock signal corresponding to 0.4 Kbps (corresponding to the frame rate of the n-channel multiplex transmission frame format) from each of the bearer channels shown in FIGS. 3A and 3B. F bit, f
Various timing signals are generated such that bits, information bits and S bits are inserted respectively.

Since the signal of the first channel separated by the separation unit 2 includes F bits for n-channel multiplex transmission, the reception unit 5 first uses the F-bit deletion unit 16 to delete the 8-bit data. The leading F bit is deleted. Then, the remaining 7-bit signal is sent to the reception memory 17 and the S-bit reception register 18, respectively.

The reception memory 17 temporarily writes and stores the 7-bit signal from the F-bit deletion unit 16. Also, the S bit reception register 18 receives only the frame in which only the S bit is inserted and temporarily stores it. The S-bit adding unit 19 reproduces an 8-bit envelope signal from the read output of the receiving memory 17 and the output of the S-bit receiving register 18 and sends out the 8-bit envelope signal to the low-speed unit 1.1.

At this time, the bearer channel # 5 contains no information and is an empty time slot. This is because bearer channel # 5 is used intensively for transmitting S bits of other bearer channels # 1 to # 4. Although bearer channel # 5 is used for S-bit transmission of the first channel, other bearer channels # 1
To # 4 may be used.

Note that the timing generator 20 is 64 Kbp
The operation timing of each section 16 to 19 is generated from a clock equivalent to s and a clock equivalent to 0.4 Kbps.

[0033]

As described above, according to the present invention, X.264, which can be transmitted only by an 8-bit envelope, is used. X. 50 frames By intensively transmitting the S bits in the 50 frames using the specific bearer channel, there is an effect that even a channel that can use only 7 bits can be transmitted by multiplexing the bearer channel.

In this case, the transmission frame X. Since 50 frames can be used as they are and there is no need to use a dedicated frame, there is an effect that the system cost is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3A is a diagram showing the configuration of bearer channels # 1 to # 4 in 20 multiframes in an n-channel multiplex transmission multiplex frame according to an embodiment of the present invention, and FIG. FIG. 3 is a diagram showing the configuration of FIG.

[Fig. 4] X.11 of CCITT-X series recommendation. FIG. 5 is a diagram showing an 8-bit envelope conforming to F.50.

FIG. It is a figure which shows the structure of each bearer channel # 1- # 5 in 20 multi-frames of 50 frames.

FIG. FIG. 5 is a diagram showing a 20 multi-frame configuration at 50.

FIG. FIG. 2 is a system block diagram illustrating a case where 50 frames are transmitted by n-channel multiplexing.

FIG. 8 is a diagram illustrating a frame configuration for n-channel multiplex transmission.

[Explanation of symbols]

 1 Multiplexer 1.1-1. n Low-speed section 2 Separation section 3 High-speed transmission path 4 Transmission section 5 Receiving section 11 S-bit separation section 12 S-bit transmission register 13 Selector 14 Frame transmission section 15, 20 Timing generation section 16 F-bit deletion section 17 Reception memory 18 S-bit reception Register 19 S bit addition section

Claims (3)

(57) [Claims] 1. An X.400 system comprising a plurality of predetermined bit envelopes from a low-speed stage and conforming to CCITT-X recommendations. With 50 frames as input, separating means for selectively separating the status bits in the envelope, storage means for temporarily storing the separated status bits, and the status bits are deleted via the separating means. selection means for alternatively derive the state bit stored as residual bits in the storage unit, the predetermined while adding frame synchronization frame information to the respective first bit of all of the envelope of selection output of the selection means Transmitting means for transmitting in a transmission frame configuration comprising a plurality of bit envelopes , and all of the status bits stored in the storage means are inserted into a specific envelope portion of the plurality of envelopes. Means for controlling the selection means. 2. The low-speed stage is provided for n channels, and the synchronous data signal transmitting apparatus transmits an X.509 signal from the low-speed stage of the first channel. 50 frames as input, and each X.50 from the low-speed stage of the second to n-th channels. The transmitting apparatus according to claim 1, further comprising a multiplexing unit that multiplexes 50 frames and the transmission frame from the synchronous data signal transmitting apparatus. 3. An X.400 system comprising a plurality of envelopes of predetermined bits and conforming to CCITT-X recommendations. 50 frames to n
The multiplexed synchronization data signal in which the frame information for frame synchronization is inserted into the first bit of each constituent envelope and the status bit is inserted into the specific envelope portion only in the first channel only in the first channel. A receiving device for receiving each X.X. of the first to n-th channels based on the frame synchronization information. Separation means for separating 50 frames, storage means for receiving and storing information of an envelope other than the specific envelope of the separated first channel, and status bit storage for receiving and storing the status bits of the specific envelope Means and the contents stored in these storage means. Means for reproducing 50 frames.