JP2607664B2 - Equipment with noise elimination circuit - Google Patents
Equipment with noise elimination circuitInfo
- Publication number
- JP2607664B2 JP2607664B2 JP1021378A JP2137889A JP2607664B2 JP 2607664 B2 JP2607664 B2 JP 2607664B2 JP 1021378 A JP1021378 A JP 1021378A JP 2137889 A JP2137889 A JP 2137889A JP 2607664 B2 JP2607664 B2 JP 2607664B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- circuit
- line
- supply line
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Noise Elimination (AREA)
- Filters And Equalizers (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は、雑音除去回路を有する機器に関するもので
あり、電源線と情報線とを有するあらゆる機器、特にAV
関連機器や情報関連機器の分野において用いられるもの
である。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device having a noise elimination circuit, and any device having a power supply line and an information line, in particular, an AV device.
It is used in the field of related devices and information-related devices.
[従来の技術] 第3図は雑音除去回路を備える従来の機器の概略構成
を示している。図中、1は電源線であり、例えば、商用
交流電源に接続される。2は情報線であり、例えば電話
回線に接続される。電源回路10は電源線1から機器の駆
動用電源電圧を得ている。信号処理回路20は情報線2と
の間で信号を送受している。電源線1と情報線2には、
それぞれフェライトコアなどを用いて構成した妨害電圧
阻止回路3,4を挿入し、妨害電圧を除去している。[Prior Art] FIG. 3 shows a schematic configuration of a conventional device including a noise removing circuit. In the figure, reference numeral 1 denotes a power supply line, which is connected to, for example, a commercial AC power supply. An information line 2 is connected to, for example, a telephone line. The power supply circuit 10 obtains a power supply voltage for driving the device from the power supply line 1. The signal processing circuit 20 sends and receives signals to and from the information line 2. Power line 1 and information line 2
Disturbance voltage blocking circuits 3 and 4 each composed of a ferrite core or the like are inserted to remove the disturbance voltage.
[発明が解決しようとする課題] ところが、上述の従来例にあっては、電源線1に発生
するノイズ、情報線2に発生するノイズのみをそれぞれ
妨害電圧阻止回路3,4により阻止していたに過ぎず、電
源線1と情報線2との間に誘起される妨害電圧を除去す
ることはできなかった。ここで、電源線1と情報線2と
の間に誘起される妨害電圧が、いかなるものであるかは
特定することはできないが、例えば、高周波インバータ
式の照明器具や、コンピュータのディスプレイ装置、ス
イッチング電源装置、空調機その他のモータ、雷や放電
などの自然現象、自動車エンジンのスパークノイズ等々
の妨害電圧が空間中に無数に存在するので、これらが電
源線1と情報線2との間に妨害電圧として誘起されるも
のと推測される。そして、機器に接続された電源線1と
情報線2とは、空間中のノイズを拾って妨害電圧を誘起
したり、反対に、この妨害電圧を空間中に輻射したりす
るアンテナ作用を有するので、このような妨害電圧が信
号処理回路20の配線に混入することを避けられなかっ
た。このように、従来例にあっては、電源線1と情報線
2との間に誘起される妨害電圧が機器に及ぼす悪影響に
対しては無防備であったため、例えば、AV関連機器にお
ける受信画像の乱れや、情報関連機器における誤動作が
発生するという問題があった。[Problems to be Solved by the Invention] However, in the above-described conventional example, only the noise generated in the power supply line 1 and the noise generated in the information line 2 are blocked by the disturbance voltage blocking circuits 3 and 4, respectively. However, the disturbance voltage induced between the power supply line 1 and the information line 2 could not be removed. Here, it is not possible to specify what kind of disturbance voltage is induced between the power supply line 1 and the information line 2, but for example, a high frequency inverter type lighting device, a computer display device, There are countless disturbing voltages in the space, such as power supply devices, air conditioners and other motors, natural phenomena such as lightning and discharge, and spark noise of automobile engines, which interfere between the power line 1 and the information line 2. It is presumed to be induced as a voltage. The power supply line 1 and the information line 2 connected to the device have an antenna function of picking up noise in the space and inducing an interference voltage, and conversely, radiating the interference voltage into the space. However, it was inevitable that such an interference voltage would be mixed into the wiring of the signal processing circuit 20. As described above, in the conventional example, since the interference voltage induced between the power supply line 1 and the information line 2 is not vulnerable to the adverse effect on the device, for example, the reception image of the AV-related device is not protected. There has been a problem that disturbances and malfunctions in information-related devices occur.
本発明はこのような点に鑑みてなされたものであり、
その目的とするところは、電源線と情報線との間に誘起
される妨害電圧を効果的に除去できる雑音除去回路を有
する機器を提供することにある。The present invention has been made in view of such a point,
An object of the present invention is to provide a device having a noise elimination circuit that can effectively eliminate an interference voltage induced between a power supply line and an information line.
[課題を解決するための手段] 本発明にあっては、上記の課題を解決するために、第
1図に示すように、電源線1と情報線2とを有し、電源
線1に接続される第1の回路(電源回路10)と、情報線
2に接続される第2の回路(信号処理回路20)を内蔵す
る機器において、電源線1と情報線2の間に誘起される
高周波の妨害電圧に対して定常的に低インピーダンスを
呈するコンデンサ等よりなる妨害電圧バイパス回路5
を、電源線1と情報線2の間に介在するよに内蔵して成
るものである。[Means for Solving the Problems] In the present invention, in order to solve the above-mentioned problems, as shown in FIG. 1, a power supply line 1 and an information line 2 are provided and connected to the power supply line 1. In a device having a built-in first circuit (power supply circuit 10) and a second circuit (signal processing circuit 20) connected to the information line 2, high-frequency waves induced between the power line 1 and the information line 2 Voltage bypass circuit 5 composed of a capacitor or the like that constantly exhibits a low impedance with respect to the disturbance voltage
Are built in so as to be interposed between the power supply line 1 and the information line 2.
また、妨害電圧バイパス回路5と第1及び第2の回路
の間に、妨害電圧を阻止する妨害電圧阻止回路3,4をそ
れぞれ配すれば、より好ましい。It is more preferable to dispose disturbance voltage blocking circuits 3 and 4 for blocking a disturbance voltage between the disturbance voltage bypass circuit 5 and the first and second circuits.
[作 用] 本発明にあっては、このように、電源線1と情報線2
の間に誘起される高周波の妨害電圧に対して定常的に低
インピーダンスを呈するコンデンサ等よりなる妨害電圧
バイパス回路5を、電源線1と情報線2の間に介在する
ように内蔵しているので、電源線1と情報線2との間に
誘起される妨害電圧が機器内の電源回路10や信号処理回
路20のような回路に悪影響を与えることはなくなるもの
である。また、妨害電圧バイパス回路5と第1及び第2
の回路の間に、妨害電圧を阻止する妨害電圧阻止回路3,
4を配することにより、妨害電圧による悪影響をより完
全に除去することができる。[Operation] In the present invention, as described above, the power supply line 1 and the information line 2
Since a disturbance voltage bypass circuit 5 composed of a capacitor or the like that constantly exhibits a low impedance with respect to a high-frequency disturbance voltage induced between the power supply line 1 and the information line 2 is incorporated therein, In addition, the disturbance voltage induced between the power supply line 1 and the information line 2 does not adversely affect circuits such as the power supply circuit 10 and the signal processing circuit 20 in the equipment. Further, the disturbance voltage bypass circuit 5 and the first and second
Circuit, which blocks the disturbance voltage,
By arranging 4, it is possible to more completely eliminate the adverse effect due to the disturbance voltage.
[実施例] 第1図は、本発明をファクシミリやビジネスコンピュ
ータのような情報関連機器に適用した実施例の概略構成
図である。電源線1と情報線2との間に、妨害電圧バイ
パス回路5を介在させ、さらに、電源回路10と電源線端
子11との間に妨害電圧阻止回路3を挿入し、信号処理回
路20と情報線端子21との間に妨害電圧阻止回路4を挿入
している。妨害電圧バイパス回路5は、電源線1と情報
線2の間に誘起される高周波の妨害電圧に対して内部回
路よりも低インピーダンスを呈するコンデンサ等により
構成されている。したがって、電源線1と情報線2との
間に誘起された妨害電圧による電流は妨害電圧バイパス
回路5を介してのみ流れるものであり、電源線1と情報
線2のアンテナ作用により空間中に妨害電圧が複写され
ることはなく、信号処理回路20の配線に空間中の妨害電
圧が混入するような不都合は防止できる。また、妨害電
圧阻止回路3,4は妨害電圧に対して高インピーダンスを
呈するフィルタ回路により構成されており、フェライト
コアのような高透磁率の磁性材料を用いて小形軽量に構
成されている。上記の構成について、我々が試みに測定
した結果によると、最大で15dB、平均でも10dB程度の雑
音低減効果が認められた。これによって、妨害電圧によ
る伝送エラー等の誤動作を防止することができる。ま
た、雷のような突発的ノイズが混入しても、機器に悪影
響を及ぼさないという効果が期待できる。Embodiment FIG. 1 is a schematic configuration diagram of an embodiment in which the present invention is applied to an information-related device such as a facsimile or a business computer. An interfering voltage bypass circuit 5 is interposed between the power supply line 1 and the information line 2, and an interfering voltage blocking circuit 3 is inserted between the power supply circuit 10 and the power supply line terminal 11, so that the signal processing circuit 20 The disturbance voltage blocking circuit 4 is inserted between the terminal 21 and the wire terminal 21. The disturbing voltage bypass circuit 5 is configured by a capacitor or the like that exhibits a lower impedance than an internal circuit with respect to a high-frequency disturbing voltage induced between the power supply line 1 and the information line 2. Therefore, the current caused by the disturbing voltage induced between the power supply line 1 and the information line 2 flows only through the disturbing voltage bypass circuit 5, and is disturbed in the space by the antenna function of the power supply line 1 and the information line 2. The voltage is not copied, and the inconvenience of interfering voltage in the space into the wiring of the signal processing circuit 20 can be prevented. Further, the disturbance voltage blocking circuits 3 and 4 are constituted by filter circuits exhibiting a high impedance with respect to the disturbance voltage, and are made small and lightweight using a magnetic material having a high magnetic permeability such as a ferrite core. According to the results of our trial measurement, the noise reduction effect was 15 dB at the maximum and about 10 dB at the average. This can prevent a malfunction such as a transmission error due to an interference voltage. Further, even if sudden noise such as lightning is mixed, an effect that the device is not adversely affected can be expected.
次に、第2図はテレビ受像機に本発明を適用した実施
例の概略構成を示している。本実施例にあっては、信号
処理回路20に代えて、テレビジョンの受信回路22が接続
されている点を除けば、第1図の実施例と同様の構成を
有している。このように、テレビ受像機に本発明を適用
すれば、電源線1と情報線2の間に誘起される妨害電圧
が受信回路22に混入することを防止でき、受信画像の乱
れ等の不都合を解消することができるものである。Next, FIG. 2 shows a schematic configuration of an embodiment in which the present invention is applied to a television receiver. This embodiment has the same configuration as the embodiment of FIG. 1 except that a television receiving circuit 22 is connected instead of the signal processing circuit 20. As described above, if the present invention is applied to a television receiver, it is possible to prevent an interference voltage induced between the power supply line 1 and the information line 2 from being mixed into the receiving circuit 22, and to prevent inconvenience such as disturbance of a received image. It can be eliminated.
なお、実施例の説明においては、ファクシミリやビジ
ネスコンピュータのような情報処理関連機器と、テレビ
受像機のようなAV関連機器に本発明を適用する例を示し
たが、本発明は電源線と情報線との2つの線を有する全
ての機器に有効であることは言うまでもない。In the description of the embodiment, an example in which the present invention is applied to an information processing-related device such as a facsimile or a business computer and an AV-related device such as a television receiver has been described. It goes without saying that the present invention is effective for all devices having two lines.
[発明の効果] 本発明にあっては、このように、電源線と情報線の間
に誘起される高周波の妨害電圧に対して定常的に低イン
ピーダンスを呈するコンデンサ等よりなる妨害電圧バイ
パス回路を、電源線と情報線の間に介在するように内蔵
しているので、電源線と情報線との間に誘起される妨害
電圧が機器内の回路に悪影響を与えることはなくなると
いう効果がある。[Effects of the Invention] According to the present invention, as described above, a disturbance voltage bypass circuit including a capacitor or the like that constantly exhibits a low impedance with respect to a high-frequency disturbance voltage induced between a power supply line and an information line is provided. Since the power supply line and the information line are interposed between the power supply line and the information line, the interference voltage induced between the power supply line and the information line does not adversely affect the circuit in the device.
また、妨害電圧バイパス回路と少なくとも第1又は第
2の回路の間に、妨害電圧を阻止する妨害電圧阻止回路
を配することにより、妨害電圧による悪影響をより完全
に除去することができるという効果がある。Further, by disposing a disturbance voltage blocking circuit for blocking a disturbance voltage between the disturbance voltage bypass circuit and at least the first or second circuit, the effect that the adverse effect due to the disturbance voltage can be more completely eliminated. is there.
【図面の簡単な説明】 第1図は本発明の第1実施例の概略構成図、第2図は本
発明の第2実施例の概略構成図、第3図は従来例の概略
構成図である。 1は電源線、2は情報線、3,4は妨害電圧阻止回路、5
は妨害電圧バイパス回路、10は電源回路、11は電源線端
子、20は信号処理回路、21は情報線端子、22は受信回路
である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram of a first embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a second embodiment of the present invention, and FIG. 3 is a schematic configuration diagram of a conventional example. is there. 1 is a power line, 2 is an information line, 3 and 4 are disturbance voltage blocking circuits, 5
Is a disturbance voltage bypass circuit, 10 is a power supply circuit, 11 is a power supply line terminal, 20 is a signal processing circuit, 21 is an information line terminal, and 22 is a receiving circuit.
Claims (2)
れる第1の回路と、情報線に接続される第2の回路を内
蔵する機器において、電源線と情報線の間に誘起される
高周波の妨害電圧に対して定常的に低インピーダンスを
呈するコンデンサ等よりなる妨害電圧バイパス回路を、
電源線と情報線の間に介在するように内蔵して成ること
を特徴とする雑音除去回路を有する機器。1. An apparatus having a power supply line and an information line, wherein a first circuit connected to the power supply line and a second circuit connected to the information line are built in, between the power supply line and the information line. A disturbance voltage bypass circuit composed of a capacitor or the like that constantly exhibits a low impedance with respect to a high-frequency disturbance voltage induced in
A device having a noise elimination circuit, which is built in so as to be interposed between a power supply line and an information line.
は第2の回路の間に、妨害電圧を阻止する妨害電圧阻止
回路を配して成ることを特徴とする請求項1記載の雑音
除去回路を有する機器。2. The noise elimination circuit according to claim 1, further comprising an interference voltage blocking circuit for blocking an interference voltage between the interference voltage bypass circuit and at least the first or second circuit. Equipment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1021378A JP2607664B2 (en) | 1989-01-31 | 1989-01-31 | Equipment with noise elimination circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1021378A JP2607664B2 (en) | 1989-01-31 | 1989-01-31 | Equipment with noise elimination circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02202241A JPH02202241A (en) | 1990-08-10 |
JP2607664B2 true JP2607664B2 (en) | 1997-05-07 |
Family
ID=12053431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1021378A Expired - Lifetime JP2607664B2 (en) | 1989-01-31 | 1989-01-31 | Equipment with noise elimination circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2607664B2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61264916A (en) * | 1985-05-20 | 1986-11-22 | Matsushita Electric Ind Co Ltd | Surge absorbing circuit |
JPS63194526A (en) * | 1987-02-06 | 1988-08-11 | 富士通株式会社 | Surge protective circuit |
-
1989
- 1989-01-31 JP JP1021378A patent/JP2607664B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61264916A (en) * | 1985-05-20 | 1986-11-22 | Matsushita Electric Ind Co Ltd | Surge absorbing circuit |
JPS63194526A (en) * | 1987-02-06 | 1988-08-11 | 富士通株式会社 | Surge protective circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH02202241A (en) | 1990-08-10 |
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