JP2600357B2 - Digital signal processor - Google Patents
Digital signal processorInfo
- Publication number
- JP2600357B2 JP2600357B2 JP1008816A JP881689A JP2600357B2 JP 2600357 B2 JP2600357 B2 JP 2600357B2 JP 1008816 A JP1008816 A JP 1008816A JP 881689 A JP881689 A JP 881689A JP 2600357 B2 JP2600357 B2 JP 2600357B2
- Authority
- JP
- Japan
- Prior art keywords
- full adder
- digital signal
- significant bit
- input
- carry input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Complex Calculations (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、全加算器とフリップフロップによって構成
されるデジタル信号処理装置に関するものである。Description: TECHNICAL FIELD The present invention relates to a digital signal processing device including a full adder and a flip-flop.
従来の技術 第２図は従来の全加算器とフリップフロップを用い、
４ビットのディジタルフィルタで構成したデジタル信号
処理装置を示す。第２図において、00〜03,10〜13,20〜
23,30〜33はフリップフロップ、50〜54,60〜64,70〜74
は全加算器で、式（１＋Z-1）３で表される４ビットの
デジタルローパスフィルタは、フリップフロップ（以下
DFFと略す）の入力および出力を全加算器の二つの入力
A,Bに接続する回路を１単位としてビット数に応じて繰
り返し構成をとり、全加算器の桁上げ入力Ciは下位ビッ
トの全加算器の桁上げ出力と接続していた。そして最下
位ビット列の全加算器の桁上げ入力Ciは全て接地してい
た。FIG. 2 shows a conventional full adder and a flip-flop.
1 shows a digital signal processing device constituted by a 4-bit digital filter. In FIG. 2, 00-03,10-13,20-
23,30-33 are flip-flops, 50-54,60-64,70-74
Is a full adder, and a 4-bit digital low-pass filter expressed by the equation (1 + Z -1 ) 3 is a flip-flop (hereinafter, referred to as a flip-flop).
DFF) input and output are the two inputs of the full adder
A, a circuit connected to B takes a repeating configuration according to the number of bits as a unit, the carry input C i of the full adder was connected to the carry output of the full adder of the lower bits. And carry input C i of the full adder of the least significant bit column were all grounded.
発明が解決しようとする課題 しかしながら、上記従来の構成では最下位ビット列の
全加算器の桁上げ入力Ciはすべて接地されていたので、
加算処理を繰り返すことにより、データ全体の平均値が
処理を行うたびに低下していくという問題があった。SUMMARY OF THE INVENTION However, since the above-mentioned conventional configuration had all carry input C i of the full adder of the least significant bit sequence is grounded,
By repeating the addition process, there is a problem that the average value of the entire data decreases every time the process is performed.
本発明は上記従来の問題点を解決するもので、装置の
フィルタとしての特性を損なうことなく、データの平均
値の低下を低減できる装置を提供することを目的とす
る。SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned conventional problems, and has as its object to provide an apparatus capable of reducing a decrease in the average value of data without impairing the characteristics of the apparatus as a filter.
課題を解決するための手段 この目的を達成するために、本発明のデジタル信号処
理装置は、少なくとも１つの全加算器群の最下位ビット
の全加算器の桁上げ入力が前記デジタル信号処理装置の
少なくとも最上位ビットとともに前記最上位ビットの１
つ下位ビットを入力とする制御回路の出力に制御される
回路構成を有している。Means for Solving the Problems In order to achieve this object, a digital signal processing apparatus according to the present invention is arranged such that the carry input of the least significant bit full adder of at least one full adder group is the digital signal processing apparatus. At least one of the most significant bits
It has a circuit configuration that is controlled by the output of a control circuit that receives the lower-order bit as an input.
作用 この構成によって、上位ビット列の信号１つ又は、複
数個によって全加算器の桁上げ入力Ciに入る信号が制御
されるので、データ値の絶対値が大きいとき、すなわち
データの振幅値が大きいときに限り、全加算器の桁上げ
入力Ciにハイレベルの信号（正論理の場合は１）が入る
ように設定しておけば、装置のデジタルフィルタとして
の伝達関数は保持し、データ全体の振幅の平均値の低下
を低減することができる。Action This arrangement one signal 1 of upper bit string or the signal entering the carry input C i of the full adder is controlled by a plurality, when the absolute value of the data value is large, that a large amplitude of a data only when, by setting as carry input C i to the high-level signal of the full adder (in the case of positive logic 1) enters the transfer function of the digital filter device holds the entire data Can be reduced.
実施例 以下本発明の一実施例について図面を参照しながら説
明する。第１図は本発明の実施例で、全加算器とDFFを
用い、４ビットのディジタルフィルタを構成したデジタ
ル信号処理装置を示すものである。第１図において00〜
03,10〜13,20〜23,30〜33,40〜41はDFF,50〜54,60〜64,
70〜74は全加算器であり、従来例で示した１単位（１＋
Z-1）で表される全加算器群回路を直列に３段接続し、
（１＋Z-1）３で表されるデジタルフィルタの４ビット
構成を示している。１段目は、最上位２ビットの入力信
号X3,X2が排他的論理和（以下XORと記す）回路５に入力
し、その出力はDFF40のデータ入力端子に入力し、DFF40
の出力が全加算器50の桁上げ入力Ciに接続されている。
２段目の全加算器60の桁上げ入力Ciは従来通り接地され
ている。３段目は、１段目と同じく最上位２ビットの入
力信号がXOR回路25とDFF41を通して全加算器70の桁上げ
入力Ciに接続されている。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, which shows a digital signal processing device using a full adder and a DFF to constitute a 4-bit digital filter. In FIG. 1, 00 ~
03,10-13,20-23,30-33,40-41 is DFF, 50-54,60-64,
Reference numerals 70 to 74 denote full adders, each of which is 1 unit (1+
Z -1 ) are connected in series at three stages of full adder group circuits,
4 shows a 4-bit configuration of the digital filter represented by (1 + Z −1 ) 3 . In the first stage, the most significant two-bit input signals X 3 and X 2 are input to an exclusive OR (hereinafter referred to as XOR) circuit 5, and the output is input to the data input terminal of DFF 40.
Output is connected to the carry input C i of the full adder 50.
Carry input C i of the full adder 60 of the second stage is grounded conventionally. Third stage, also Saijoi 2-bit input signal and the first stage is connected to the carry input C i of the full adder 70 through a XOR circuit 25 and DFF41.
すなわち、上位ビットに信号のないとき、（信号が−
４から＋３までに制限されているような小振幅時）は、
平均値補正用の桁上げ入力を、低レベルのままにしてデ
ジタルフィルタの伝達関数特性を保持し、平均値補正用
の桁上げ入力が、伝達関数に影響を余り与えないような
大振幅の入力に対しては、桁上げ入力を高レベルにし
て、振幅の平均値の低下を低減させることが可能にな
る。That is, when there is no signal in the upper bits,
At small amplitudes that are limited to 4 to +3)
The carry input for the average value is kept at a low level to maintain the transfer function characteristics of the digital filter, and the input with a large amplitude so that the carry input for the average value does not significantly affect the transfer function. , It is possible to reduce the average amplitude value by setting the carry input to a high level.
なお、本実施例では、全加算器70の桁上げ入力Ciの制
御回路の入力は、全加算器群70〜74の直前のDFF22,23の
入力を制御して印加したが、回路の特性に応じてDFF02,
03,12,13等の入力信号により制御してもよいことは明ら
かである。In this embodiment, the input of the control circuit of the carry input C i of the full adder 70 is applied by controlling the DFF22,23 input immediately before the full adder group 70 to 74, circuit characteristics According to DFF02,
Obviously, the control may be performed by input signals such as 03, 12, and 13.
以上のように構成された本実施例のデジタル信号処理
装置について、以下その動作を説明する。The operation of the digital signal processing device of the present embodiment configured as described above will be described below.
ここでは、データとして、２の補数データを扱うもの
とする。Here, it is assumed that two's complement data is handled as data.
１段目において、最上位２ビットの入力信号X3,X2が
同じ状態のときは、XOR回路５の出力は低レベル（正論
理で０）となり、このとき全加算器50の桁上げ入力Ciは
低レベルとなり、異なる状態のときは、XOR回路５の出
力は高レベルとなり、このとき全加算器50の桁上げ入力
Ciは高レベルとなる。In the first stage, when the input signals X 3 and X 2 of the most significant 2 bits are in the same state, the output of the XOR circuit 5 becomes low level (0 in positive logic), and at this time, the carry input of the full adder 50 C i goes low, and in different states, the output of the XOR circuit 5 goes high, at which time the carry input of full adder 50
C i is at a high level.
２段目では、全加算器60の桁上げ入力Ciは接地されて
いるので従来通り常に低レベル状態となる。In the second stage, the carry input C i of the full adder 60 is always low state conventionally because it is grounded.
３段目では、１段目と全く同じようにして、全加算器
70の桁上げ入力Ciが制御されている。In the third stage, a full adder is performed in exactly the same way as in the first stage.
70 carry input C i of is controlled.
このように１つおきに１段目,2段目と同じ回路を接続
していくと、フィルタ特性を変えずに、データ全体の平
均値の低下を低減することができる。If the same circuits as the first and second stages are connected every other line in this way, it is possible to reduce the decrease in the average value of the entire data without changing the filter characteristics.
発明の効果 従来例のデジタルフィルタにおいては、接続される段
数が増加するにつれて、データ全体の平均値の低下が顕
著となるが、以上のように、本発明によれば、実施例の
１段目のような回路構成を適当な割合で、入れることに
より、この低下を低減することができる。Effects of the Invention In the digital filter of the conventional example, as the number of connected stages increases, the average value of the entire data decreases significantly. As described above, according to the present invention, the first stage of the embodiment is This reduction can be reduced by inserting a circuit configuration such as that described above at an appropriate ratio.
第１図は本発明の一実施例におけるデジタル信号処理装
置の回路図、第２図は従来のデジタル信号処理装置の回
路図である。 00〜03,10〜13,20〜23,30〜33,40〜41……フリップフロ
ップ、50〜54,60〜64,70〜74……全加算器、5,25……排
他的論理和回路、X0〜X3……入力信号、Z0〜Z3……出力
信号。FIG. 1 is a circuit diagram of a digital signal processing device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional digital signal processing device. 00-03,10-13,20-23,30-33,40-41 ... Flip-flop, 50-54,60-64,70-74 ... Full adder, 5,25 ... Exclusive OR circuit, X 0 ~X 3 ...... input signal, Z 0 ~Z 3 ...... output signal.
Claims (1)
リップフロップ群により構成され、最上位ビットが正ま
たは負の符号を表すデジタル信号処理装置において、全
加算器群回路が複数段直列に接続され、少なくとも全加
算器群回路の１つが、最上位ビットが正の符号を表しか
つ前記最上位ビットの１つ下位ビットが高レベルの時
と、最上位ビットが負の符号を表しかつ前記最上位ビッ
トの１つ下位ビットが低レベルの時は、最下位ビットの
桁上げ入力を高レベルにすることを特徴としたデジタル
信号処理装置。1. A digital signal processor in which a full adder group circuit of a unit is composed of a full adder group and a flip-flop group, and wherein the most significant bit represents a positive or negative sign, the full adder group circuit includes a plurality of full adder group circuits. Connected in series, at least one of the full adder group circuits is configured such that the most significant bit represents a positive sign and the least significant bit of the one most significant bit is high, and the most significant bit represents a negative sign. A digital signal processing apparatus characterized in that, when one lower bit of the most significant bit is low, the carry input of the least significant bit is high.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1008816A JP2600357B2 (en) | 1989-01-18 | 1989-01-18 | Digital signal processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1008816A JP2600357B2 (en) | 1989-01-18 | 1989-01-18 | Digital signal processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02189018A JPH02189018A (en) | 1990-07-25 |
| JP2600357B2 true JP2600357B2 (en) | 1997-04-16 |
Family
ID=11703336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1008816A Expired - Fee Related JP2600357B2 (en) | 1989-01-18 | 1989-01-18 | Digital signal processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2600357B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101915059B1 (en) | 2016-10-19 | 2019-01-14 | 조선대학교산학협력단 | Accurate adder consists of 14 transistors and DSP integrated with the adder |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56158525A (en) * | 1980-05-12 | 1981-12-07 | Nec Corp | Circulation type digital filter |
-
1989
- 1989-01-18 JP JP1008816A patent/JP2600357B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101915059B1 (en) | 2016-10-19 | 2019-01-14 | 조선대학교산학협력단 | Accurate adder consists of 14 transistors and DSP integrated with the adder |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02189018A (en) | 1990-07-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |